Timing Recovery in Digital Subscriber Loops Using Baud-Rate Sampling

Sampled-data techniques are the most practical means of obtaining the necessary signal processing functions for timing recovery in the VLSI implementation of a digital subscriber loop transceiver. The sampled-data timing recovery techniques described in this paper are applicable to both echo cancellation and time-compression multiplexing systems. Timing recovery using baud-rate sampling in conjunction with a special pulse-shaping and timing function fulfills all the objectives for timing recovery in this application. It recovers a timing phase that has minimum precursor intersymbol interference, and makes possible the combination of decision feedback equalizer and echo canceler, reducing the convergence time and increasing the step size. The pulse-shaping function can be performed either in the transmitter by means of digital coding, or in the receiver by means of analog filtering. In the latter case, the transmitted pulse is compatible with more conventional approaches. The proposed partial-response line coding, a special form of AMI coding, is less susceptible to line impairments if detected as a two-level signal. Performance by analysis, simulation, and experimental measurements is reported on a variety of cable configurations, some including bridged taps. Analysis of jitter performance leads to design techniques for reducing the jitter magnitude.     

Sliding window criterion codes and concatenation scheme formitigating timing-jitter-induced errors in WDM fiber transmissions

We propose a concatenated coding scheme, which effectively reduces bit errors induced by soliton-soliton collisions (SSC) in wavelength division multiplexing (WDM) soliton transmission systems. A block line coding scheme, the sliding window criterion (SWC) code, is developed based on the nature of SSC-induced timing jitter in soliton communications. We show, by simplified collision model simulations, that the SWC code alone can decrease the SSC-induced timing jitter and, by concatenation to a Reed-Solomon (RS) code, improve both the bit rate and the channel spacing capacity in WDM systems. We compare the performance of our scheme both analytically and by simulations with those of various RS codes and concatenated RS-convolutional code used in optical fiber transmission systems, and show that high redundancy (overhead) does not always give better code performance. Finally, by using full simulations, we show that the SWC code is an effective and promising technique for dispersion-managed fiber WDM systems     

Timing Recovery in Digital Synchronous Data Receivers

A new class of fast-converging timing recovery methods for synchronous digital data receivers is investigated. Starting with a worst-case timing offset, convergence with random binary data will typically occur within 10-20 symbols. The input signal is sampled at the baud rate; these samples are then processed to derive a suitable control signal to adjust the timing phase. A general method is outlined to obtain near-minimum-variance estimates of the timing offset with respect to a given steady-state sampling criterion. Although we make certain independence assumptions between successive samples and postulate ideal decisions to obtain convenient analytical results, our simulations with a decision-directed reference and baud-to-baud adjustments yield very similar results. Convergence is exponential, and for small loop gains the residual jitter is proportional and convergence time is inversely proportional to the loop gain. The proposed algorithms are simple and economic to implement. They apply to binary or multilevel PAM signals as well as to partial response signals.     

The effects of timing jitter and tracking on the performance of impulse radio

Impulse radio (IR) is a promising ultra-wideband technique for tactical military communications. A key feature of time-hopping IR are the very narrow pulses used to convey information. Analysis of such time-hopping schemes under a variety of assumptions have been reported in the literature. However, none of these studies to date consider the effects of timing jitter and tracking on time-hopping in a ultra-wideband (UWB) setting. We consider the effects of timing jitter and tracking on the performance of binary and 4-ary UWB communications. We find that the performance of IR is very sensitive to timing jitter and tracking, at least in part due to the very narrow pulses. We also find that in the presence of timing jitter and tracking, orthogonal 4-ary pulse position modulation (PPM) out performs binary offset PPM at all jitter levels in thermal and pulse noise. Simulation results are presented that quantify the sensitivity of binary and 4-ary IR to timing jitter and tracking error.     

Studies on Timing Jitter in WDM Dispersion-Managed System by Variational Method

The variational method is employed to describe the basic properties of soliton parameters and to evaluate the timing jitter by considering multi-perturbations in wavelength-division-multiplexing (WDM) dispersion-managed soliton (DMS) system. The bit error rates (BER) of different dispersion managed systems, which induced by the timing jitter are given and compared. From that, there exist optimizations for the design of high-speed and long-distance practical WDM soliton system.     

Analysis and equalization of data-dependent jitter

Data-dependent jitter limits the bit-error rate (BER) performance of broadband communication systems and aggravates synchronization in phase- and delay-locked loops used for data recovery. A method for calculating the data-dependent jitter in broadband systems from the pulse response is discussed. The impact of jitter on conventional clock and data recovery circuits is studied in the time and frequency domain. The deterministic nature of data-dependent jitter suggests equalization techniques suitable for high-speed circuits. Two equalizer circuit implementations are presented. The first is a SiGe clock and data recovery circuit modified to incorporate a deterministic jitter equalizer. This circuit demonstrates the reduction of jitter in the recovered clock. The second circuit is a MOS implementation of a jitter equalizer with independent control of the rising and falling edge timing. This equalizer demonstrates improvement of the timing margins that achieve 10/sup -12/ BER from 30 to 52 ps at 10 Gb/s.     

Investigation of Synchronization Parameters in a Digital Subscriber Loop Transmission System

The degree of echo reduction achieved in a digital subscriber loop (DSL) transceiver employing adaptive echo cancellation has previously been shown to be very sensitive to timing jitter. This paper reports the experimental study, by computer simulation, of a 144 kbit/s DSL timing recovery system incorporating a prefilter, nonlinearity, and second-order phase-locked loop. The simulations were carried out for a wide variety of line lengths, bridged-tap conditions, loop and filter parameters, and choice of nonlinearity. The results showed that a properly designed timing recovery system with a 20 khzwide prefilter allows satisfactory echo reduction performance, even for long loops with bridged taps. For shorter loops the achievable echo reduction is less, but is still sufficient to yield satisfactory performance.     

Minimum Mean-Square Error Timing Recovery Schemes for Digital Equalizers

Two algorithms are presented for optimum timing recovery in digitally implemented equalizers. The first one is a polarity-type algorithm based on the conventional minimum mean-square error criterion. A theoretical analysis is made to characterize the algorithm phase detector and evaluate its steady-state phase jitter variance. Influence of various channel and system design parameters on the algorithm performance is illustrated using phase jitter probability densities obtained by means of computer simulations. Interaction of the algorithm with decision-directed carrier recovery is also examined. It is shown that interaction with carrier recovery may considerably degrade the timing acquisition performance, and a second algorithm is then presented which eliminates this interaction. The second algorithm is based on the minimization of a modified mean-square error criterion which provides a measure of the intersymbol interference, independently of the carrier phase. Decision-directed timing and carrier recoveries are thus decoupled and the system startup period is considerably reduced. Phase detector characteristic and steady-state jitter performance of the second algorithm are evaluated by analytical means and computer simulations, as in the first algorithm.     

Analysis of a serial symbol timing recovery technique employingExclusive-OR circuit

An analysis is presented of the performance of a serial symbol timing recovery (STR) circuit which employs an Exclusive-OR circuit for conventional coherent digital modulated communication systems. The output of the timing circuit is a nearly sinusoidal wave whose zero crossings indicate the appropriate sampling instants for extraction of the data. Assuming that the data pulses entering the timing path are even symmetric, exact analytical expressions for the mean and mean-squared values of the timing wave and for the RMS phase jitter are derived as a function of various system parameters such as channel band limiting, postfiltering, delay element, and power spectral density of noise. Numerical results, also checked by computer simulations, show that considerable improvement can be obtained in jitter performance, in addition to the advantages over other STR techniques of lower cost and simpler hardware implementation     

定时综合的数字相位方法

本文提出了在相位量化下的高精度定时综合理论,并基于Ｖｉｔｅｒｂｉ算法提出一种最优合成方法,同时还给出了基于Ｔ－Ｖｉｔｅｒｂｉ的简化方法并对Ｔ－Ｖｉｔｅｒｂｉ和二阶Ｓｉｇｍａ－ＤｅｌｔａＭｏｄｕｌａｔｉｏｎ（ＳＤＭ）方法进行了分析和性能比较,仿真结果表明这两种方法在量化精度上大大优于传统的一阶ＳＤＭ的方法,最后,本文给出了一个最优化算法在ＳＤＨ漂移产生中的应用实例。     

Low-jitter digital timing recovery techniques for CAP-based VDSL applications

In this paper, a digital timing recovery technique for carrierless amplitude and phase modulation (CAP)-based very-high-speed digital subscriber line (VDSL) applications is presented. A digital spectral line method is proposed for the timing tone extraction. It avoids the bandwidth expansion normally caused by the nonlinear property of the timing tone extraction block, and lowers the required sampling clock frequency. Also, an adaptive loop gain control scheme is proposed to reduce the timing jitter, simultaneously achieving both fast locking and low steady-state jitter. A prototype timing recovery circuit in a 0.35-/spl mu/m CMOS technology achieves 12.02-ps and 86-ps rms and peak-to-peak jitter, respectively, at 40-MHz operation. This is equivalent to about 0.1% of the symbol rate, and suitable for VDSL applications. The prototype IC consumes about 55 mW with a 3.0-V power supply.     

Collision-induced timing jitter reduction by periodic dispersionmanagement in soliton WDM transmission

The authors propose to use dispersion management to reduce collision-induced timing jitter in soliton WDM transmission. The performance of dispersion-managed fibres is compared numerically to dispersion-decreasing and uniform dispersion fibres with up to eight channels, and it is shown that dispersion management can provide the best performance     

Symbol rate timing recovery for higher order partial responsechannels

This paper provides a framework for analyzing and comparing timing recovery schemes for higher order partial response (PR) channels. Several classes of timing recovery schemes are analyzed. Timing recovery loops employing timing gradients or phase detectors derived from the minimum mean-square error (MMSE) criterion, the maximum likelihood (ML) criterion, and the timing function approach of Mueller and Muller (1976) (MRI) are analyzed and compared. The paper formulates and analyzes MMSE timing recovery in the context of a slope look-up table (SLT), which is amenable for an efficient implementation. The properties and performance of the SLT-based timing loop are compared with the ML and MM loops. Analysis and time step simulations for a practical 16-state PR magnetic recording channel show that the output noise jitter of the ML phase detector is worse than that of the SLT-based phase detector. This is primarily due to the presence of self-noise in the ML detector. Consequently, the SLT-based phase detector is to be preferred. In comparing the SLT and MM based timing loops, it is found that both schemes have similar jitter performance     

Coding, decoding, and recovery of clock synchronization in digital multiplexing system

High-speed broadband digital communication networks rely on digital multiplexing technology where clock synchronization, including processing, transmission, and recovery of the clock, is the critical technique. This paper interprets the process of clock synchronization in multiplexing systems as quantizing and coding the information of clock synchronization, interprets clock justification as timing sigma-delta modulation (T/spl Delta/-/spl Sigma/M), and interprets the jitter of justification as quantization error. As a result, decreasing the quantization error is equivalent to decreasing the jitter of justification. Using this theory, the paper studies the existing jitter-reducing techniques in transmitters and receivers, presents some techniques that can decrease the quantization error (justification jitter) in digital multiplexing systems, and presents a new method of clock recovery.     

A performance analysis of an all-optical clock extraction circuitbased on Fabry-Perot filter

A performance analysis of an optical clock extraction circuit based on a Fabry-Perot filter (FPF) is presented. Two analytical methods, time-domain and frequency-domain analysis, are developed in this paper. Time-domain analysis shows that there is no phase jitter in the extracted optical clock if the free spectral range (FSR) of the FPF is exactly equal to the signal clock frequency. Based on this, we obtain an analytical expression for root mean square (rms) amplitude jitter of the extracted optical clock in time domain, in which we have taken the impacts of carrier frequency drift and carrier phase noise into account. When the FSR of the FPF deviates from the signal clock frequency, both phase jitter and amplitude jitter will occur in the extracted optical clock. In this situation, a more general frequency-domain method is developed to deal with the timing performance under the assumption that carrier phase noise is negligible. This method allows us to calculate both rms phase jitter and rms amplitude jitter of the extracted optical clock. Using the developed two methods, we present a detailed numerical investigation on the impacts of finesse of the FPF, carrier frequency drift, resonator detuning, carrier phase noise, and optical pulse chirp on the timing performance. Finally, the application of this circuit in multiwavelength clock recovery is discussed     

Accurate System Voltage and Timing Margin Simulation in High-Speed I/O System Designs

Accurate analysis of system timing and voltage margin including deterministic and random jitter is crucial in high-speed I/O system designs. Traditional SPICE-based simulation techniques can precisely simulate various deterministic jitter sources, such as intersymbol interference (ISI) and crosstalk from passive channels. The inclusion of random jitter in SPICE simulations, however, results in long simulation time. Innovative simulation techniques based on a statistical simulation framework have been recently introduced to cosimulate deterministic and random jitter effects efficiently. This paper presents new improvements on this statistical simulation framework. In particular, we introduce an accurate jitter modeling technique which accounts for bounded jitter with arbitrary spectrum in addition to Gaussian jitter. We also present a rigorous approach to model duty cycle distortion (DCD). A number of I/O systems are considered as examples to validate the proposed modeling methodology.      

全数字接收机平方定时恢复环路

本文着重研究全数字接收机中定时恢复环路的设计,该环路由内插滤波器,预滤波器,平方定时误差检测,环路滤波和 定时控制单元组成,仿真结果表明,通过预滤波明显减小了定时抖动,该算法可以达到较好的性能,并由单片FPGA实现, 该芯片已成功用于QAM全数字接收机中。     

Timing Jitter Effects on Digital Subscriber Loop Echo Cancellers: Part I--Analysis of the Effect

We analyze the effect of Subscriber-end timing recovery Circuit jitter on the performance of two types of adaptive echo cancellers that can be used for full-duplex digital transmission on two-wire subscriber loops. Under severe echo-to-far-end signal ratios, echo canceller performance is found to be quite sensitive to high-frequency jitter components. Satisfactory performance with respect to jitter requires that a narrow-band phase-locked loop, rather than a single-tuned high-Qfilter, be employed for timing recovery.     

对2R全光再生器时间抖动抑制的研究

研究了利用二次再生结构来抑制光纤自相位调制全光再生器引起的时间抖动。根据转移函数的输出特性,分析了A-A、B-B和C-C 3种类型的二次再生器对时间抖动抑制的性能,并利用分布傅里叶算法进行了仿真。理论和数值结果表明:C-C结构的二次再生器对时间抖动抑制效果最好,B-B型次之,而A-A型则会加剧再生信号的时间抖动。造成二次再生器对抑制时间抖动性能差异的主要原因是,第一级再生器会通过输出脉冲幅度的变化对第二级再生器的时间抖动造成影响。