An ultra high-speed 8-bit timing interleave folding＆interpolating analog-to-digital converter with digital foreground calibration technology

A 2-Gsample/s 8-b analog-to-digital converter in 0.35μm BiCMOS process technology is presented. The ADC uses the unique folding and interpolating algorithm and dual-channel timing interleave multiplexing technology to achieve a sampling rate of 2 GSPS.Digital calibration technology is used for the offset and gain corrections of the S/H circuit,the offset correction of preamplifier,and the gain and clock phase corrections between channels.As a result of testing,the ADC achieves 7.32 ENOB at an analog input of 484 MHz and 7.1 ENOB at Nyquist input after the chip is self-corrected.     

A 1.2-V, 84-dB Σ△ ADM in 0.18-μm digital CMOS technology

A low power and low voltage∑△analog-to-digital modulator is realized with digital CMOS technology, which is due to full compensated depletion mode capacitors.Compared with mixed signal technology,this type of modulator is more compatible for pure digital applications.A pseudo-two-stage class-AB OTA is used in switchedcapacitor integrators for low voltage and low power.The modulator is realized in standard SMIC 0.18μm 1P6M digital CMOS technology.Measured results show that with 1.2 V supply voltage and a 6 MHz sample clock,the dynamic range of the modulator is 84 dB and the total power dissipation is 2460μW.     

A 10-bit 50-MS/s reference-free low power SAR ADC in 0.18-μm SOI CMOS technology

正A 10-bit 50-MS/s reference-free low power successive approximation register(SAR) analog-to-digital converter(ADC) is presented.An energy efficient switching scheme is utilized in this design to obtain low power and high frequency operation performance without an additional analog power supply or on-chip/off-chip reference. An on-chip calibration DAC(CDAC) is implemented to cancel the offset of the latch-type sense amplifier(SA) to ensure precision whilst getting rid of the dependence on the pre-amplifier,so that the power consumption can be reduced further.The design was fabricated in IBM 0.18-μm 1P4M SOI CMOS process technology.At a 1.5-V supply and 50-MS/s with 5-MHz input,the ADC achieves an SNDR of 56.76 dB and consumes 1.72 mW,resulting in a figure of merit(FOM) of 61.1 fJ/conversion-step.     

A 6.25 Gb/s equalizer in 0.18μm CMOS technology for high-speed SerDes

This paper presents a 0.18μm CMOS 6.25 Gb/s equalizer for high speed backplane communication. The proposed equalizer is a combined one consisting of a one-tap feed-forward equalizer （FFE） and a two-tap half-rate decision feedback equalizer （DFE） in order to cancel both pre-cursor and post-cursor ISI. By employing an active-inductive peaking circuit for the delay line, the bandwidth of the FFE is increased and the area cost is minimized. CML-based circuits such as DFFs, summers and multiplexes all help to improve the speed of DFEs. Measurement results illustrate that the equalizer operates well when equalizing 6.25 Gb/s data is passed over a 30-inch channel with a loss of 22 dB and consumes 55.8 mW with the supply voltage of 1.8 V. The overall chip area including pads is 0.3 × 0.5 mm^2.     

A 1-GS/s 6-bit folding and interpolating ADC in 0.13-μm CMOS

A 1-GS/s 6-bit two-channel time-interleaved folding and interpolating analog-to-digital converter (ADC) is presented in this article. For low voltage applications, input-connection-improved active interpolating amplifiers and cascaded folding amplifiers have been applied. A single front-end track-and-hold (T/H) circuit is used to avoid the sampling-time mismatches between the channels. When supplied with 1.4 V, the circuit achieves signal-to-noise-plus-distortion ratio (SNDR) of 30.74 dB and spurious free dynamic range (SFDR) of 36.91 dB and consumes a power of 66 mW with 500-MHz input and 1-GS/s sampling rate. Differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.57 and 0.81 LSB, respectively. The figure of merit (FoM) is 1.75 pJ/conversionstep. The ADC circuit is prototyped in 0.13-μm CMOS process and occupies a core area of 0.45 mm².     

A 5-GHz programmable frequency divider in 0.18-μm CMOS technology

正A 5-GHz CMOS programmable frequency divider whose modulus can be varied from 2403 to 2480 for 2.4-GHz ZigBee applications is presented.The divider based on a dual-modulus prescaler(DMP) and pulse-swallow counter is designed to reduce power consumption and chip area.Implemented in the 0.18-μm mixed-signal CMOS process,the divider operates over a wide range of 1-7.4 GHz with an input signal of 7.5 dBm;the programmable divider output phase noise is -125.3 dBc/Hz at an offset of 100 kHz.The core circuit without test buffer consumes 4.3 mA current from a 1.8 V power supply and occupies a chip area of approximately 0.015 mm~2.The experimental results indicate that the programmable divider works well for its application in frequency synthesizers.     

A 7-GHz multiloop ring oscillator in 0.18-μm CMOS technology

A novel delay stage for ring oscillator utilizing multiloop technique is presented in this paper. Different conventional delay stages for the multiloop ring oscillators have been reviewed and analyzed in this work. By using push-pull inverter as the secondary input in its delay cell, the proposed oscillator demonstrates a frequency improvement of up to 17% when compared with conventional designs. The fabricated oscillator is measured to cover a frequency range of 6.24–7.04 GHz. Operating in 1.8-V power supply, the oscillator manifests itself a phase noise of ?107.7 dBc/Hz@10 MHz offset from a center frequency of 6.25 GHz. The proposed oscillator consumes a current of 40–51 mA from the 1.8-V supply and occupies an area of 440 μm ×  430 μm.     

A 5.25-GHz low-power down-conversion mixer in 0.18-μm CMOS technology

A 5.25 GHz low voltage, high linear and isolated mixer using TSMC 0.18 μm CMOS process for WLAN receiver was investigated. The paper presents a novel topology mixer that leads to better performance in terms of linearity, isolation and power consumption for low supply voltage. The measuring results of the proposed mixer achieve: 7.6 dB power conversion gain, 11.4 dB double side band noise figure, 3 dBm input third-order intercept point, and the total dc power consumption of this mixer including output buffers is 2.45 mW from a 1 V supply voltage. The current output buffer is about 2 mW, the excellent LO-RF, LO-IF and RF-IF isolation achieved up to 37.8, 54.8 and 38.2 dB, respectively.     

A 900 MHz fractional-N synthesizer for UHF transceiver in 0.18μm CMOS technology

A 900 MHz fractional-N synthesizer is designed for the UHF transceiver. The VCO with a 4 bits capacitor bank covers 823–1061 MHz that implements 16(24)sub-bands. A 7/8 dual-modulus prescaler is implemented with a phase-switching circuit and high-speed flip–flops, which are composed of source coupled logic. The proposed synthesizer phase-locked loop is demonstrated with a 50 k Hz band width by a low 12.95 MHz reference clock, and offers a better phase noise and band width tradeoff. To reduce the out-band phase noise, a 4-levels 3-order single-loop sigma–delta modulator is applied. When its relative frequency resolution is settled to 10-6, the testing results show that the phase noises are –120.6 d Bc/Hz at 1 MHz and –95.0 d Bc/Hz at 100 k Hz. The chip is2.1 mm2 in UMC 0.18μm CMOS. The power is 36 m W at a 1.8 V supply.     

A fully integrated direct-conversion digital satellite tuner in 0.18μm CMOS

A fully integrated direct-conversion digital satellite tuner for DVB-S/S2 and ABS-S applications is presented.A broadband noise-canceling Balun-LNA and passive quadrature mixers provided a high-linearity low noise RF front-end,while the synthesizer integrated the loop filter to reduce the solution cost and system debug time.Fabricated in 0.18μm CMOS,the chip achieves a less than 7.6 dB noise figure over a 900-2150 MHz L-band, while the measured sensitivity for 4.42 MS/s QPSK-3/4 mode is -91 dBm at the PCB connector.The fully integrated integer-N synthesizer operating from 2150 to 4350 MHz achieves less than 1℃integrated phase error. The chip consumes about 145 mA at a 3.3 V supply with internal integrated LDOs.     

A threshold inverter quantization based folding and interpolation ADC in 0.18 μm CMOS

Data converters are needed to interface between the physical world of analog signals and the digital world of signal processing, computing and data processing. Full flash converter is considered as the fastest converter type. The problems associated with small signal and clock delays of larger size structures limit the accuracy and introduce distortion and therefore improved converter systems with a reduced chip area are desirable. With few comparators compared to flash, folding and interpolation architectures are good option for low-power implementations of medium resolution (4b to 10b), high speed (tens or hundreds mega samples per second (MSample/s)) analog-to-digital converters (ADCs). This paper describes the concept of threshold inverter quantization based folding amplifier. The reference ladder using resistors is replaced by inverters and as a result the area and static power dissipations are expected to be lower. Introduction of inverters would reduce the node capacitances and the transition of signals would be faster. The proposed method is very sensitive to process variations and their impact on the ADC performance is investigated.     

High linearity technique for ultra-wideband low noise amplifier in 0.18 μm CMOS technology

A linearization technique for ultra-wideband low noise amplifier (UWB LNA) has been designed and fabricated in standard 0.18 μm CMOS technology. The proposed technique exploits the complementary characteristics of NMOS and PMOS to improve the linearity performance. A two-stage UWB LNA is optimized to achieve high linearity over the 3.1-10.6 GHz range. The first stage adopts inverter topology with resistive feedback to provide high linearity and wideband input matching, whereas the second stage is a cascode amplifier with series and shunt inductive peaking techniques to extend the bandwidth and achieve high gain simultaneously. The proposed UWB LNA exhibits a measured flat gain of 15 dB within the entire band, a minimum noise figure of 3.5 dB, and an IIP3 of 6.4 dBm while consuming 8 mA from a 1.8 V power supply. The total chip area is 0.39 mm², including all pads. The measured input return loss is kept below −11 dB, and the output return loss is −8 dB, from 3.1 to 10.6 GHz.     

A 3-5 GHz TH-UWB transmitter in 0.18-μm RF CMOS technology

5 mV at a 50 Ω load from a 1.8-V supply, the return loss (S11) at the output port is less than -10 dB, and the chip size is 0.7 × 0.8 mm2, with a power consumption of 12.3 mW.     

A 3-5 GHz BPSK transmitter for IR-UWB in 0.18μm CMOS

This paper presents a transmitter IC with BPSK modulation for an ultra-wide band system.It is based on up-conversion with a high linearity passive mixer.Unlike the traditional BPSK modulation scheme,the local oscillator (LO) is modulated by the baseband data instead of the pulse.The chip is designed and fabricated by standard 0.18μm CMOS technology.The transmitter achieves a high data rate up to 400 Mbps.The amplitude of the pulse can be adjusted by the amplitude of the LO and the bias current of the dri...     

A 1.4-V 25-mW 600-MS/s 6-bit folding and interpolating ADC in 0.13-μm CMOS

A 600-MSample/s 6-bit folding and interpolating analog-to-digital converter(ADC) is presented.This ADC with single track-and-hold(T/H) circuits is based on cascaded folding amplifiers and input-connection-improved active interpolating amplifiers.The prototype ADC achieves 5.55 bits of the effective number of bits(ENOB) and 47.84 dB of the spurious free dynamic range(SFDR) at 10-MHz input and 4.3 bit of ENOB and 35.65 dB of SFDR at 200-MHz input with a 500 MS/s sampling rate;it achieves 5.48 bit of ENOB a...     

A RF receiver frontend for SC-UWB in a 0.18-μm CMOS process

正A radio frequency(RF) receiver frontend for single-carrier ultra-wideband(SC-UWB) is presented. The front end employs direct-conversion architecture,and consists of a differential low noise amplifier(LNA),a quadrature mixer,and two intermediate frequency(IF) amplifiers.The proposed LNA employs source inductively degenerated topology.First,the expression of input impedance matching bandwidth in terms of gate-source capacitance, resonant frequency and target S_(11) is given.Then,a noise figure optimization strategy under gain and power constraints is proposed,with consideration of the integrated gate inductor,the bond-wire inductance,and its variation.The LNA utilizes two stages with different resonant frequencies to acquire flat gain over the 7.1-8.1 GHz frequency band,and has two gain modes to obtain a higher receiver dynamic range.The mixer uses a double balanced Gilbert structure.The front end is fabricated in a TSMC 0.18-/im RF CMOS process and occupies an area of 1.43 mm~2.In high and low gain modes,the measured maximum conversion gain are 42 dB and 22 dB,input 1 dB compression points are -40 dBm and -20 dBm,and S_(11) is better than -18 dB and -14.5 dB.The 3 dB IF bandwidth is more than 500 MHz.The double sideband noise figure is 4.7 dB in high gain mode.The total power consumption is 65 mW from a 1.8 V supply.     

A 1.4-V 25-Mw 600-MS/s 6-bit folding and interpolating ADC in 0.13-μm CMOS

A 600-MSample/s 6-bit folding and interpolating analog-to-digital converter (ADC) is presented. This ADC with single track-and-hold (T/H) circuits is based on cascaded folding amplifiers and input-connection-improved active interpolating amplifiers. The prototype ADC achieves 5.55 bits of the effective number of bits (ENOB) and 47.84 dB of the spurious free dynamic range (SFDR) at 10-MHz input and 4.3 bit of ENOB and 35.65 dB of SFDR at 200-MHz input with a 500 MS/s sampling rate; it achieves 5.48 bit of ENOB and 43.52 dB of SFDR at 1-MHz input and 4.66 bit of ENOB and 39.56 dB of SFDR at 30. 1-MHz input with a 600-MS/s sampling rate. This ADC has a total power consumption of 25 mW from a 1.4 V supply voltage and occupies 0.17 mm~2 in the 0.13-μm CMOS process.