一种用于短距离无线通信并集成频率合成器的多模式多频带发射机

A reconfigurable multi-mode direct-conversion transmitter(TX) with integrated frequency synthesizer(FS) is presented. The TX as well as the FS is designed with a flexible architecture and frequency plan, which helps to support all the 433/868/915 MHz ISM band signals, with the reconfigurable bandwidth from 250 kHz to 2 MHz. In order to save power and chip area, only one 1.8 GHz VCO is adopted to cover the whole frequency range. All the operation modes can be regulated in real time by configuring the integrated register-bank through an SPI interface. Implemented in 180 nm CMOS, the FS achieves a frequency coverage of 320-460 MHz and 620- 920 MHz. The lowest phase noise can be -107 dBc/Hz at a 100 kHz offset and -126 dBc/Hz at a 1 MHz offset. The transmitter features a C10:2 dBm peak output power with a C9:5 dBm 1-dB-compression point and 250 kHz/500 kHz/1 MHz/2 MHz reconfigurable signal bandwidth.     

一种用于无线接收机的噪声整形可重构复数带通/低通滤波器的设计

A reconfigurable complex band-pass （CBP）/low-pass （LP） active-RC filter with a noise-shaping technique for wireless receivers is presented. Its bandwidth is reconfigurable among 500 kHz, 1 MHz and 4 MHz in LP mode and 1 MHz, 2 MHz and 8 MHz in CBP mode with 3 MHz center frequency. The Op-Amps used in the filter are realized in cell arrays in order to obtain scalable power consumption among the different operation modes. Furthermore, the filter can be configured into the 1st order, 2nd order or 3rd order mode, thus achieving a flexible filtering property. The noise-shaping technique is introduced to suppress the flicker noise contribution. The filter has been implemented in 180 nm CMOS and consumes less than 3 mA in the 3rd 8 MHz-bandwidth CBP mode. The spot noise at 100 Hz can be reduced by 14.4 dB at most with the introduced noise-shaping technique.     

A 100-kHz to 20-MHz Reconfigurable Power-Linearity Optimized $G_m$–$C$ Biquad in 0.13-$mu$ m CMOS

Fully reconfigurable transceivers are required to answer the low-power high flexibility demand of future mobile applications. This paper presents a fully reconfigurable G_m-C biquadratic low-pass filter which offers a large range of both frequency and performance flexibility. First, a design approach is proposed focusing on linearity properties by extending Volterra analysis from circuit to architectural level in order to optimize the filters performance. Secondly, a novel switching technique is discussed that allows a bandwidth tuning over more than two orders of magnitude starting from 100 kHz up to 20 MHz and which uses only gate transistor capacitance. Fundamental to this technique is that the power consumption can be traded with the desired performance. Furthermore, the quality factor, noise level and linearity are all programmable over a very wide range. The biquad is processed in a 0.13-mum CMOS technology and operates at different supply voltages down to less than 0.8 V. For a 1.2-V supply, the filter consumes between 103 muA (100 kHz) and 11.85 mA (20 MHz) for a low noise setting around 25 to 35 muVrms integrated over the filter bandwidth achieving an third-order intermodulation intercept point of 10 dBVp.     

Flexible Baseband Analog Circuits for Software-Defined Radio Front-Ends

This paper presents a novel approach to design a digitally programmable low pass filter (LPF) and variable gain amplifier (VGA) intended for a software-defined radio (SDR) front-end. These flexible analog circuits are driven by a network-on-chip (NoC) that is able to set performance parameters like cut-off frequency, selectivity, noise, and gain guaranteeing at any time a near-optimal power/performance trade-off. A design approach is proposed to tackle the challenges imposed by flexibility in analog design. A silicon prototype is realized in 0.13-mum CMOS technology with 1.2-V supply voltage to prove the validity of the proposed solution. The LPF provides a frequency tuning range between 0.35 MHz and 23.5 MHz with an adaptive integrated noise level between 85 muVrms and 163 muVrms whereby the power consumption conveniently varies from 0.72 mW to 21.6 mW according to the required performance. The VGA is made up of two cascaded gain stages and provides a gain range from about 0 dB to 39 dB with a reconfigurable power/bandwidth.     

A novel analog/digital reconfigurable automatic gain control with a novel DC offset cancellation circuit

An analog/digital reconfigurable automatic gain control(AGC) circuit with a novel DC offset cancellation circuit for a direct-conversion receiver is presented.The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips.What’s more,a novel DC offset cancellation(DCOC) circuit with an HPCF(high pass cutoff frequency) less than 10 kHz is proposed.The AGC is fabricated by a 0.18μm CMOS process.Under analog control mode,the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz.Under digital control mode,through a 5-bit digital control word,the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB.The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV,while the offset voltage of 40 mV is introduced into the input.The overall power consumption is less than 3.5 mA,and the die area is 800×300μm~2.     

超宽带低噪声放大器的计算机辅助设计

叙述了超宽带低噪声放大器的计算机辅助设计方法，提出了利用普通微带混合集成电路．工艺设计超宽带低噪声放大器的方法和关键技术，并且用带封装的ＢＪＴ和ＦＥＴ实现了两个超宽带低噪声放大器。实验结果和设计结果吻合较好。一个利用２ＳＣ３３５８，放大器为三级，频带为３０ｋＨＺ～１６００ＭＨＺ，增益Ｇ＝２０±１ｄＢ，噪声系数ＮＦ≤３．５ｄＢ；另一个利用ＡＴＦ１０２３５（６），放大器为二级，频带为５００ｋＨＺ～６０００ＭＨＺ，增益Ｇ＝２０±２ｄＢ，噪声系数ＮＦ≤２ｄＢ。     

CPT铷原子钟锁相环频率合成器设计和分析

基于CPT(相干布局囚禁)87铷原子钟设计出输出频率为3417 MHz的锁相环频率合成器,通过ADIsimPLL仿真出最佳环路带宽,环路滤波器参数以及相位噪声等,并通过STM32对锁相环芯片进行控制。对频率合成器进行了测试,电路尺寸为40 mm×40 mm,输出信号功率范围为-4 dBm^+5 dBm可调,输出信号噪声满足要求-88.65 dBc/Hz@1 kHz,-92.31 dBc/Hz@10 kHz,-104.63 dBc/Hz@100 kHz,杂散和谐波得到抑制,设计的频率合成器能很好的应用于原子钟的射频信号源。     

一种多频多模接收机低功耗信道选择滤波器

基于GSMC 0.18μm RF CMOS工艺,实现了一种8阶有源RC信道选择滤波器,其截止频率在200kHz～10MHz范围内可调,能覆盖GSM,UHF RFID,TD-SCDMA,IEEE 802.11a/b/g等不同频段。提出一种增益带宽积可变的运算放大器,以优化不同模式下的功耗。正交两路信道选择滤波器的芯片尺寸为1.5mm×0.36mm。测试结果表明,在1.8V电源下,滤波器消耗8.6mA,4mA和2.6mA电流,等效输入噪声为20nV/Hz～(1/2),输入3阶交调为15dBm。     

A reconfigurable OTA-C baseband filter with wide digital tuning for GNSS receivers

The design of a digitally-tunable sixth-order reconfigurable OTA-C filter in a 0.18-μm RFCMOS process is proposed.The filter can be configured as a complex band pass filter or two real low pass filters.An improved digital automatic frequency tuning scheme based on the voltage controlled oscillator technique is adopted to compensate for process variations.An extended tuning range(above 8:1) is obtained by using widely continuously tunable transconductors based on digital techniques.In the complex band pas...     

片上自动调谐的可编程有源RC滤波器

研制了一款可编程6阶巴特沃斯有源RC滤波器.为提高滤波器中运算放大器的增益带宽积,设计了一种新型的前馈补偿运算放大器.为消除工艺偏差和环境变化对截止频率的影响,设计了一种片上数字控制频率调谐电路,并采用TSMC 0.18 μm CMOS工艺进行了流片.滤波器采用低通滤波结构,测试结果表明,3 dB截止频率为1～32 MHz,步进1 MHz,带内增益0 dB,带内纹波0.8 dB,2倍带宽处带外抑制不小于24 dBc,5倍带宽处带外抑制不小于68 dBc,滤波器等效输入噪声为340 nV/√Hz@1MHz,调谐误差为±3％.滤波器裸芯片面积0.87 mm×1.05 mm.采用1.8V电源电压,滤波器整体功耗小于20 mW.     

A low-power reconfigurable analog-to-digital converter

A low-power CMOS reconfigurable analog-to-digital converter that can digitize signals over a wide range of bandwidth and resolution with adaptive power consumption is described. The converter achieves the wide operating range by (1) reconfiguring its architecture between pipeline and delta-sigma modes; (2) varying its circuit parameters, such as size of capacitors, length of pipeline, and oversampling ratio, among others; and (3) varying the bias currents of the opamps in proportion to the converter sampling frequency, accomplished through the use of a phase-locked loop (PLL). This converter also incorporates several power-reducing features such as thermal noise limited design, global converter chopping in the pipeline mode, opamp scaling, opamp sharing between consecutive stages in the pipeline mode, an opamp chopping technique in the delta-sigma mode, and other design techniques. The opamp chopping technique achieves faster closed-loop settling time and lower thermal noise than conventional design. At a converter power supply of 3.3 V, the converter achieves a bandwidth range of 0-10 MHz over a resolution range of 6-16 bits, and parameter reconfiguration time of twelve clock cycles. Its PLL lock range is measured at 20 kHz to 40 MHz. In the delta-sigma mode, it achieves a maximum signal-to-noise ratio of 94 dB and second and third harmonic distortions of 102 and 95 dB, respectively, at 10 MHz clock frequency, 9.4 kHz bandwidth, and 17.6 mW power. In the pipeline mode, it achieves a maximum DNL and INL of ±0.55 LSBs and ±0.82 LSBs, respectively, at 11 bits, at a clock frequency of 2.6 MHz and 1 MHz tone with 24.6 mW of power     

四极点LGS晶体滤波器的研制

介绍了了一种四极点单片式硅酸鎵镧(La_3Ga_5SiO_(14),LGS)晶体滤波器的设计方法.该滤波器中心频率为5 MHz,3 dB带宽20 kHz,工作温度范围为-55～+125 ℃,体积只有32.0 mm×16.0 mm×8.5 mm.实验证明,LGS晶体能实现相对带宽为0.3%～0.8%,频率温度稳定性好,体积小的晶体滤波器,具有广泛的应用价值.     

Wide‐Band Fine‐Resolution DCO with an Active Inductor and Three‐Step Coarse Tuning Loop

This paper presents a wide‐band fine‐resolution digitally controlled oscillator (DCO) with an active inductor using an automatic three‐step coarse and gain tuning loop. To control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. To cover the wide tuning range, a three‐step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO tuning range is 58% at 2.4 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The phase noise of the DCO output at 2.4 GHz is –120.67 dBc/Hz at 1 MHz offset.     

C波段微波低相位噪声介质振荡源

介绍了微波低相位噪声介质振荡器的设计方法。就影响介质振荡器相位噪声的因素进行了讨论,从谐振回路有载Q值、有源器件、增益压缩量、电路模式等几个方面提出了降低相位噪声的方法,并给出了一个C波段微波低相噪振荡器的设计实例。测试结果表明:该振荡器工作频率3 900 MH z,输出功率大于10 dBm,相位噪声达到-102 dB c/H z@1 kH z;-128 dB c/H z@10 kH z。     

A positive-feedback transconductance amplifier with applications tohigh-frequency, high-Q CMOS switched-capacitor filters

The authors describe a high-bandwidth amplifier that simultaneously achieves high gain by using internal positive feedback. The results obtained when the amplifier is used in a general-purpose switched-capacitor biquadratic building block are also presented. This device achieves 150-kHz center-frequency operation with Q accuracy of 15% when clocked at 7.5 MHz with 10-V ±10% supplies from -55°C to +125°C. With a minimum power supply of 4.5 V, this filter operates with center frequencies up to 100 kHz when clocked at 5 MHz, while performing with the same accuracy and across the same temperature range as above     

具有带外抑制特性的Ka波段低功耗低噪声放大器

基于0.15μm GaAs赝配高电子迁移率晶体管(PHEMT)工艺,成功研制了一款30~34 GHz频带内具有带外抑制特性的低功耗低噪声放大器(LNA)微波单片集成电路(MMIC)。该MMIC集成了滤波器和LNA,其中滤波器采用陷波器结构,可实现较低的插入损耗和较好的带外抑制特性;LNA采用单电源和电流复用结构,实现较高的增益和较低的功耗。测试结果表明,该MMIC芯片在30~34 GHz频带内,增益大于28 dB,噪声系数小于2.8 dB,功耗小于60 mW,在17~19 GHz频带内带外抑制比小于-35 dBc。芯片尺寸为2.40 mm×1.00 mm。该LNA MMIC可应用于毫米波T/R系统中。     

一种UHF频段小数分频频率综合器设计与实现

基于130 nm CMOS工艺设计了一款特高频(UHF)频段的锁相环型小数分频频率综合器.电感电容式压控振荡器(LC VCO)片外调谐电感总值为2 nH时,其输出频率范围为1.06～1.24 GHz,调节调谐电感拓宽了频率输出范围,并利用开关电容阵列减小了压控振荡器的增益.使用电荷泵补偿电流优化了频率综合器的线性度与带内相位噪声.此外对电荷泵进行适当改进,确保了环路的稳定.测试结果表明,通过调节电荷泵补偿电流,频率综合器的带内相位噪声可优化3 dB以上,中心频率为1.12 GHz时,在1 kHz频偏处的带内相位噪声和1 MHz频偏处的带外相位噪声分别为-92.3和-120.9 dBc/Hz.最小频率分辨率为3 Hz,功耗为19.2 mW.     

基于锁相环技术的UHF频段宽带频率源设计

针对UHF频段的通信系统,研制了一种UHF频段的宽带频率源。采用锁相环频率合成的方法,通过对器件选型、参数设定、环路滤波器等关键部分详细分析的方式,完成了UHF频段频率源的设计。测试结果表明,该频率源的工作频率范围为300MHz-350MHz,步进频率为10kHz,杂散抑制优于45dBc,相位噪声优于50dBc/Hz@100kHz,输出功率大于-15dBm,各项指标满足实际工程应用要求。     

A 35-mW 3.6-mm/sup 2/ fully integrated 0.18-/spl mu/m CMOS GPS radio

A single-chip CMOS Global Positioning System (GPS) radio has been integrated using only a couple of external passive components for the input matching network and one external reference for the synthesizer. The receiver downconverts the GPS L1 signal at 1575.42 MHz to an IF of 9.45 MHz. The complete front-end and frequency synthesizer section have been integrated: low noise amplifier, image rejection mixer, IF active filter, and the full phase-locked loop synthesizer, including voltage-controlled oscillator and loop filter. The front-end measured performances are 81-dB maximum gain, 5.3-dB noise figure, and >30-dB image rejection. The synthesizer features a phase noise of -95 dBc/Hz at 1-MHz offset and a total integrated phase noise of less than 7/spl deg/ rms in the 500-Hz-1.5-MHz band. The front-end and the synthesizer draw, respectively, 11 and 9 mA from a 1.8-V supply. The architecture of the front-end and synthesizer has been geared to high level of integration and reduction of silicon area at the lowest possible power consumption. Consequently, the one reported here is the smallest and most integrated CMOS GPS receiver reported so far.     

U波段小数分频锁相环型频率综合器

使用0.18μm1.8VCMOS工艺实现了U波段小数分频锁相环型频率综合器,除压控振荡器(VCO)的调谐电感和锁相环路的无源滤波器外,其他模块都集成在片内。锁相环采用了带有开关电容阵列(SCA)的LC-VCO实现了宽频范围,使用3阶MASHΔ-Σ调制技术进行噪声整形降低了带内噪声。测试结果表明,频率综合器频率范围达到650～920MHz;波段内偏离中心频率100kHz处的相位噪声为-82dBc/Hz,1MHz处的相位噪声为-121dBc/Hz;最小频率分辨率为15Hz;在1.8V工作电压下,功耗为22mW。