一种宽带低功耗低相位噪声的双模预分频器

本文设计了应用SCL、TPSC和CMOS静态三种类型的触发器配合工作的新型双模预分频器。与传统使用单一种类型触发器的双模预分频器相比,该双模预分频器更容易获得高速、宽带、低功耗和低相位噪声的性能。为了验证此设计的性能,采用了SMIC 0.18um CMOS 工艺流片实现。在电源电压为1.8V的条件下测试,此双模预分频器的工作频率范围从0.9 GHz 到 3.4 GHz ;当输入信号为 3.4 GHz时,其功耗为2.51mW,相位噪声为-134.78 dBc/Hz @ 1 MHz. 其核心面积为 is 57um*30um。鉴于其良好的性能,可以应用于许多射频系统的频率综合器中,特别在多标准无线通信系统中。     

A novel wideband low phase noise 2:1 frequency divider

This paper describes a novel low-power wideband low-phase noise divide-by-two frequency divider.Hereby,a new D-latch topology is introduced.By means of conventional dynamic source-coupled logic techniques,the divider demonstrates a wideband with low phase noise by adding a switch transistor between the clock port and the couple node of the input NMOS pair in the D latch.The chip was fabricated in the 90-nm CMOS process of IBM.The measurement results show that the frequency divider has an input frequency range from 0.05 to 10 GHz and the phase noise is-159.8 dBc/Hz at 1 MHz offset from the carrier.Working at 10 GHz,the frequency divider dissipates a total power of 9.12 mW from a 1.2 V supply while occupying only 0.008 mm2 of the core die area.     

一种新型的宽带低相位噪声2分频器

通过对各种2分频器结构的研究,提出一种新结构的D触发器。由此触发器组成的2分频器具有宽带低相位噪声的特点。与传统的动态SCL结构的D触发器相比,通过在D触发器的输入对管的耦合端口和时钟端口之间加一个开关管,扩展了工作带宽并同时保持了低的相位噪声。此芯片采用IBM 的90nm CMOS工艺。测试结果表明,此2分频器工作的频率范围为：0.05-10GHz。工作频率为10GHz时,输出信号的相位噪声在频偏1MHz处为-159.8 dBc/Hz 。工作电压为1.2V,功耗为9.12mW。核心芯片面积仅为0.008mm2。     

3.1~4.9 GHz宽带低相位噪声频率源的研制

基于LTC6946-2频率合成器设计了3.1~4.9 GH频率源,给出了参数设计过程和实物测试结果。该频率源具有宽带、低相位噪声、低杂散、低成本和占用面积小等特点。经过硬件调试达到的主要指标为:输出频率3.1~4.9 GHz,步进10 MHz,相位噪声优于-97.8 dBc/Hz@1 kHz和-99.3 dBc/Hz@10 kHz,杂散优于-90 dBc。     

A dual-band frequency synthesizer for CMMB application with low phase noise

A wide-band frequency synthesizer with low phase noise is presented.The frequency tuning range is from 474 to 858 MHz which is compatible with U-band CMMB application while the S-band frequency is also included. Three VCOs with selectable sub-band are integrated on chip to cover the target frequency range.This PLL is fabricated with 0.35μm SiGe BiCMOS technology.The measured result shows that the RMS phase error is less than 1°and the reference spur is less than -60 dBc.The proposed PLL consumes 20 mA cu...     

一种应用于CMMB的双频段低噪声频率合成器

A wide-band frequency synthesizer with low phase noise is presented. The frequency tuning range is from 474 to 858 MHz which is compatible with U-band CMMB application while the S-band frequency is also included. Three VCOs with selectable sub-band are integrated on chip to cover the target frequency range. This PLL is fabricated with 0.35 μ m SiGe BiCMOS technology. The measured result shows that the RMS phase error is less than 1^o and the reference spur is less than –60 dBc. The proposed PLL consumes 20 mA current from a 2.8 V supply. The silicon area occupied without PADs is 1.17 mm².     

5V单电源供电的低噪声宽带放大器

以单片机MSP430F449为控制核心,设计了一个5 V单电源供电的低噪声宽带放大器。采用单位增益稳定低噪声运放OPA820作为前级放大,高速运放THS3091作为末级放大,其中利用DC-DC变换器TPS61087将5 V电压转化为18 V从而为末级放大电路供电。此外,系统还采用12位高速A/D转换器ADS803实现了测量并数字显示放大器输出电压峰峰值的功能,测量误差小于5%。本系统最高电压增益达到43 dB,上限及下限截止频率达到15 MHz和20 Hz,在50Ω负载上,最大不失真输出电压峰峰值为4.2 V。系统的输出噪声小于200 mV。     

一种应用于GNSS接收机的低噪声和低杂散频率综合器

A low phase noise and low spur phase locked loop （PLL） frequency synthesizer for use in global navigation satellite system （GNSS） receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector （PFD） produces four control signals, which can reach the charge pump （CP） simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc.     

A wideband frequency synthesizer for a receiver application at multiple frequencies

An integer-N frequency synthesizer for a receiver application at multiple frequencies was implemented in 0.18 μm IP6M CMOS technology. The synthesizer generates 2.57 GHz, 2.52 GHz, 2.4 GHz and 2.25 GHz local signals for the receiver. A wide-range voltage-controlled oscillator (VCO) based on a reconfigurable LC tank with a binary-weighted switched capacitor array and a switched inductor array is employed to cover the desired frequencies with a sufficient margin. The measured tuning range of the VCO is from 1.76 to 2.59 GHz. From the carriers of 2.57 GHz,2.52 GHz, 2.4 GHz and 2.25 GHz, the measured phase noises are -122.13 dBc/Hz, -122.19 dBc/Hz, -121.8 dBc/Hz and -121.05 dBc/Hz, at 1 MHz offset, respectively. Their in-band phase noises are -80.09 dBc/Hz, -80.29 dBe/Hz,-83.05 dBc/Hz and -86.38 dBc/Hz, respectively. The frequency synthesizer including buffers consumes a total power of 70 Mw from a 2 V power supply. The chip size is 1.5 × 1 mm~2.     

一种应用于多频接收机的宽带频率综合器

采用0.18µm 1P6M CMOS工艺实现了一种应用于多频接收机的整数分频频率综合器。该频率综合器为接收机提供频率分别为2.57GHz, 2.52GHz, 2.4GHz 和 2.25GHz的本振信号。为了覆盖要求的频点,其宽带压控振荡器同时采用了可变电容阵列和可变电感阵列。经测试,压控振荡器的频率调谐范围为1.76GHz~2.59GHz。对于频率为2.57GHz, 2.52GHz, 2.4GHz 和 2.25GHz的载波,在1MHz频偏处,相位噪声分别为-122.13dBc/Hz、-122.19dBc/Hz、-121.8dBc/Hz和-121.05dBc/Hz。其带内相位噪声分别为-80.09dBc/Hz、-80.29dBc/Hz、-83.05dBc/Hz 和-86.38dBc/Hz。包括驱动电路在内的芯片功耗约为70mW。芯片面积为1.5mm×1mm。     

超宽带低相噪频率合成器的实现

介绍了1种频率范围4~16GHz,步进1MHz的超宽带、小步进、低相噪频率合成器的实现方法。通过混频式锁相环方案,大大降低了环内分频比,选用低相噪器件,以及采用了梳状谱发生器代替传统的大步进环等措施,使输出实现了低相噪指标。在16GHz输出时,相位噪声指标小于-90dBc/Hz(@10kHz)。并通过对合成器指标的分析,阐述了在混频环设计过程中需要注意的一些问题。     

适用于超宽带系统的低功耗CMOS频率合成器研究

针对脉冲无线电超宽频(IR-UWB)接收系统,提出了一种低功耗频率合成器设计。合成器的设计以一个整数N分频II型四阶锁相环结构为基础,包括一个调谐范围为31%的7位压控振荡器,一组基于单相时钟逻辑的高速分频器。分频器能够合成八个由IEEE标准802.15.4a定义的频率。该集成频率合成器运用65 nm CMOS技术制造而成,面积为0.33 mm2,工作频率范围为7.5–10.6 GHz。测试结果显示,在1.2 V供电下,该合成器的3-dB闭环带宽为100 kHz,稳定时间为15 。测量相位噪声低于-103 dBc/Hz@1MHz,抵消频率为1 MHz。杂散信号功率低于低于-58 dBc。相比其他先进的合成器,提出合成器的工作电流为5.13 mA,功耗仅为6.23mW。     

一种用于IR-UWB收发器的4GHz正交输出小数频率综合器

本文针对工作于3.1GHz到5GHz频段的IR-UWB收发器,设计了一种4GHz小数频率综合器。该频率综合器采用0.18μm混合&射频CMOS工艺实现,其输出频率范围为3.74GHz到4.44GHz。通过使用多比特量化的∑-△调制器,该频率综合器在参考频率为20MHz时的输出频率分辨率达到15Hz。测试结果表明,该频率综合器的正交信号输出幅度失配和相位误差分别低于0.1dB和0.8º。该频率综合器的输出相位噪声达到-116dBc/Hz@3MHz,频谱杂散低于-60dBc。在1.8V电源电压下,该频率综合器的核心电路功耗仅为38.2mW。     

A 4 GHz quadrature output fractional-N frequency synthesizer for an IR-UWB transceiver

This paper describes a 4 GHz fractional-N frequency synthesizer for a 3.1 to 5 GHz IR-UWB transceiver.Designed in a 0.18μm mixed-signal & RF 1P6M CMOS process, the operating range of the synthesizer is 3.74 to 4.44 GHz. By using an 18-bit third-order ∑-△ modulator, the synthesizer achieves a frequency resolution of 15 Hz when the reference frequency is 20 MHz. The measured amplitude mismatch and phase error between I and Q signals are less than 0.1 dB and 0.8° respectively. The measured phase noise is -116 dBc/Hz at 3 MHz offset for a 4 GHz output.Measured spurious tones are lower than -60 dBc. The settling time is within 80 μs. The core circuit conupSigmaes only 38.2 mW from a 1.8 V power supply.     

一种采用噪声抵消及多重功耗优化技术的UWB-LNA

采用噪声抵消及多重功耗优化技术,提出了一种超宽带低噪声低功耗放大器。它主要包括采用RL网络的共栅输入级、电流复用型噪声抵消级、放大输出级以及偏置电路四个部分。验证结果表明,该放大器,在2-6GHz频带内,增益(S21)可以在14dB以上;输入回波损耗(S11)小于-10dB;输出回波损耗(S22)小于-25dB;噪声系数(NF)小于3.2dB;在3.8V的工作电压下,功耗仅为14mW。     

一种新型7.5GHz 3.4mA相位切换三模预分频器

提出了一种新型基于相位选择结构的三模预分频器,与传统结构相比,提供了更多可选的分频比和更宽的输出频率覆盖范围,同时不增加电路复杂度与功耗,可以应用于支持多种无线标准的超高频频率合成器.设计采用了TSMC 0.18μm Analog/RF CMOS工艺,电源电压2.0V.仿真结果表明,电路最高工作频率为7.5GHz,最大电流消耗小于3.4mA.     

宽带高斯型功率谱噪声信号相关特性分析

宽带噪声雷达具有良好的抗干扰和低截获性能.传统的窄带相关函数由于忽略了运动目标的多普勒色散效应而无法准确分析宽带信号的相关特性.本文以宽带噪声调频雷达测量高速目标为研究背景,推导了宽带相关函数均值的解析表达式,并对其进行了仿真验证.在此基础上分析得出,当多普勒色散积较大时宽带相关函数具有双峰特性,并揭示了其产生原因,指出了双峰位置与多普勒色散积及相对带宽之间的关系.为宽带高斯谱噪声雷达的分辨力和检测性能分析以及系统的参数设计提供了理论基础.     

一种适用于便携式多模式全球卫星导航系统接收机的低功耗宽带频率合成器设计

本文提出了一种适用于便携式多模式全球卫星导航系统（GNSS）接收机的低功耗宽带频率合成器,并分析了GNSS接收机频率合成器的设计要点。该频率合成器通过采用具有调谐曲线补偿功能的单一VCO实现了较宽的频率范围,同时具有较低的功耗和好的相位噪声性能。该频率合成器在CMOS 0.18um 1P6M工艺上流片验证成功。测试表明,带内相位噪声小于-95dBc@200KHz,频率调谐范围为1.47-1.83GHz,而整个电路面积仅为0.55mm2,整个频率合成器功耗小于11.2mw。     

一种用于数字电视调谐器的宽带CMOS无电感噪声抵消低噪声放大器

A wideband inductorless low noise amplifier for digital TV tuner applications is presented. The proposed LNA scheme uses a composite NMOS/PMOS cross-coupled transistor pair to provide partial cancellation of noise generated by the input transistors. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed LNA achieves 12.2-15.2 dB voltage gain from 300 to 900 MHz, the noise figure is below 3.1 dB and has a minimum value of 2.3 dB, and the best input-referred 1-dB compression point(IP1dB) is - 17 dBm at 900 MHz. The core consumes 7 mA current with a supply voltage of 1.8 V and occupies an area of 0.5×0.35 mm2.     

A 5 GHz CMOS frequency synthesizer with novel phase-switching prescaler and high-Q LC-VCO

A phase-locked loop(PLL) frequency synthesizer with a novel phase-switching prescaler and a high-Q LC voltage controlled oscillator(VCO) is presented.The phase-switching prescaler with a novel modulus control mechanism is much more robust on process variations.The Q factor of the inductor,I-MOS capacitors and varactors in the VCO are optimized.The proposed frequency synthesizer was fabricated by SMIC 0.13μm 1P8M MMRF CMOS technology with a chip area of 1150×2500μm~2.When locking at 5 GHz,the current consumption is 15 mA from a supply voltage of 1.2 V and the measured phase noise at a 1 MHz offset is -122.45 dBc/Hz.