Investigation of interface traps in LDD pMOST's by the DCIV method

Interface traps in submicron buried-channel LDD pMOSTs, generated under different stress conditions, are investigated by the direct-current current-voltage (DCIV) technique. Two peaks C and D in the DCIV spectrum are found corresponding to interface traps generated in the channel region and in the LDD region respectively. The new DCIV results clarify certain issues of the underlying mechanisms involved on hot-carrier degradation in LDD pMOSTs. Under channel hot-carrier stress conditions, the hot electron injection and electron trapping in the oxide occurs for all stressing gate voltage. However, the electron injection induced interface trap spatial location changes from the LDD region to the channel region when the stressing gate voltage changes from low to high     

A comparison of hot-carrier degradation in tungsten polycide gateand poly gate p-MOSFETs

A study is made of hot-carrier immunity of tungsten polycide and of non-polycide, n⁺ poly gate, buried-channel p-MOSFETs, under conditions of maximum gate current injection. Increased hot-carrier degradation is observed for WSi_x p-MOSFETs under low drain voltage stress, where trap filling by injected electrons is the dominant degradation process. Stress-induced damage evaluated by gate-to-drain capacitance C_gd^s measurement shows increased susceptibility to electron trapping in the WSi_x device. F-induced oxide bulk defects introduced during polycidation may be responsible for the increased trapping observed. In addition, a significant decrease in electron detrapping rate is observed, which suggests a deeper energy distribution of F-related traps. The greater susceptibility to electron trapping, coupled with a decrease in electron detrapping rate, result in the reduction in DC hot-carrier lifetime over four orders of magnitude (based on ΔV_t=50 mV criterion) under normal operating voltages. As hot-carrier effects in p-MOSFETs continue to be a concern for effective channel lengths less than 0.5 μm, the reduced hot-carrier lifetime of WSi_x p-MOSFETs suggests that WF₆-based silicidation may not be appropriate for deep submicrometer CMOS devices     

Hot-carrier degradation phenomena in lateral and vertical DMOS transistors

The hot-carrier degradation behavior of both a lateral and a vertical integrated DMOS transistor is investigated in detail by the analysis of the electrical data, charge pumping measurements and two-dimensional device simulations. Upon hot-carrier stress, two different, and competing degradation mechanisms are present: channel electron mobility reduction due to interface trap formation, and injection and trapping of hot holes in the accumulation region of the transistor. It will be shown that the latter mechanism is absent in the vertical DMOS.     

Hot carrier effects in n-MOSFETs with SiO2/HfO2/HfSiO gate stack and TaN metal gate

Charge trapping and trap generation in field-effect transistors with SiO₂/HfO₂/HfSiO gate stack and TaN metal gate electrode are investigated under uniform and non-uniform charge injection along the channel. Compared to constant voltage stress (CVS), hot carrier stress (HCS) exhibits more severe degradation in transconductance and subthreshold swing. By applying a detrapping bias, it is demonstrated that charge trapping induced degradation is reversible during CVS, while the damage is permanent for hot carrier injection case.     

Transconductance increase due to charge trapping during hot-carrier stress of nMOSFETs

An unusual hot-carrier degradation mode characterised by a transconductance increase during hot-carrier ageing of nMOS transistors is analysed. By measuring the effects of hot-carrier stress on drain and substrate characteristics and applying alternate static injection phases performed at different gate regimes, it is proved that the degradation is mainly due to negative charge trapping in a localised region near the drain. The transconductance increase is explained in terms of an exchange of the dominant role between the damaged and undamaged portions of the channel. This model is fully corroborated by 2D device electric simulation results.     

Channel hot-carrier stressing of reoxidized nitrided silicondioxide

The mechanisms of channel hot-carrier-induced degradation in short n-channel MOSFETs with reoxidized nitrided oxide as the gate dielectric are discussed. Charge pumping measurements, supported by observations on the gate voltage dependence of degradation and the power law dependence of Δg_m on stress time, demonstrate that virtually no interface trap generation occurs in reoxidized nitrided oxides and that electron trapping is the dominant degradation mechanism. Although electron trapping can be enhanced in these dielectrics, this mechanism is not as important for device degradation as interface trap generation, and the net effect is substantially improved resistance to hot-carrier stress. A three-orders-of-magnitude improvement in device lifetime (versus conventional oxide) is demonstrated     

Submicrometer MOSFET structure for minimizing hot-carrier generation

This paper reports on investigation of channel hot-carrier generation for various device structures. The dependences of channel hot-carrier generation on MOSFET structure are characterized by measuring the gate current and the substrate current as low as on the order of 10^-15A. The measured gate current due to hot-electron injection into the oxide is modeled numerically as thermionic emission from heated electron gas over the Si-SiO2energy barrier. The substrate current due to hot-hole injection into the substrate is also modeled analytically. On the basis of the experiments and analyses, two device structures are proposed for minimizing hot-carrier generation and associated problems in submicrometer MOSFET: a graded drain junction structure and an offset gate structure. The proposed device structures provide remarkable improvements, raising by 2 V the highest applicable voltages as limited by hot-electron injection, as well as raising by 1-3 V the drain sustaining voltages as determined by the substrate hot-hole current. The influence of electron-beam radiation on the gate oxide is also discussed in relation to the trapping of hot electrons.     

Electrical stress on irradiated thin gate oxide partially depleted SOI nMOSFETs

The effect of hot-carrier stress on 60 MeV proton irradiated thin gate oxide partially depleted SOI nMOSFETs has been studied. The results are compared with those from the electrical stress of non-irradiated devices. Whereas no significant differences are observed for the front channel degradation, hot-electron trapping in the buried oxide is found to be enhanced in the irradiated devices. This hot-electron trapping leads to a compensation or neutralization of the effects caused by the radiation-induced positive trapped charges. It is shown that a similar hot-electron trapping enhancement can be achieved in non-irradiated devices stressed under certain back gate bias conditions.     

On the time-dependent degradation of LDD n-MOSFETs under hot-carrier stress

A unified model for hot-carrier-induced degradation in LDD n-MOSFETs is presented. A novel oxide spacer charge pumping method enables interface trap generation in the spacer and overlap/channel regions to be distinctly separated. An excellent correlation between trap generation in the spacer region and linear drain current degradation at high gate voltage is observed. Moreover, trap generation in the overlap/channel region is found to correlate well with linear drain current degradation at low gate voltage. The results point unambiguously to a two-mechanism degradation model involving drain resistance increase by trap generation in the spacer region, and carrier mobility reduction by trap generation in the overlap/channel region. The combined effect of a time-independent lateral electron temperature profile and a finite density of interface trap precursors within the LDD region leads to a self-limiting degradation behavior. This insight forms the basis of a time-dependent trap generation model, which indicates the existence of a single degradation curve. The fact that the degradation curves at different stress drain voltages fall onto a time-scaled version of the single degradation curve provides strong support for the model. This also offers a straightforward and yet accurate means by which the hot-carrier lifetime corresponding to a specific failure criterion may be extracted. Finally, a power-law relationship between hot-carrier lifetime and substrate current is also observed for the LDD devices, thus preserving the physical essence based on which earlier lifetime models for conventional drain devices are established.     

The effect of externally imposed mechanical stress on thehot-carrier-induced degradation of deep-sub micron nMOSFET's

The influence of externally imposed mechanical stress (MS) on the hot-carrier-induced degradation of MOSFET's is studied. For nMOSFET's, tensile (compressive) stress increases (decreases) degradation. This effect is ascribed to the piezoresistance effect which causes a change of the hot-carrier generation. It is demonstrated that, in contradiction with earlier reports in literature, externally imposed mechanical stress has no influence on carrier trapping, nor on interface trap creation. Also, since the piezoresistance coefficient is reduced in deep-sub micron transistors, the effect of mechanical stress on hot-carrier degradation becomes negligible for 0.35-μm transistors     

The degradation mechanisms in high voltage pLEDMOS transistor with thick gate oxide

The hot-carrier degradation behavior in a high voltage p-type lateral extended drain MOS (pLEDMOS) with thick gate oxide is studied in detail for different stress voltages. The different degradation mechanisms are demonstrated: the interface trap formation in the channel region and injection and trapping of hot electrons in the accumulation and field oxide overlapped drift regions of the pLEDMOS, depending strongly on the applied gate and drain voltage. It will be shown that the injection mechanism gives rise to rather moderate changes of the specific on-resistance (Ron) but tiny changes of the saturation drain current (Idsat) and the threshold voltage (Vth). CP experiments and detailed TCAD simulations are used to support the experimental findings. In this way, the abnormal degradation of the electrical parameters of the pLEDMOS is explained. A novel structure is proposed that the field oxide of the pLEDMOS transistor is used as its gate oxide in order to minish the hot-carrier degradation.     

热载流子应力下超薄栅pMOS器件氧化层陷阱电荷的表征

利用电荷泵技术研究了4nm pMOSFET的热载流子应力下氧化层陷阱电荷的产生行为.首先,对于不同沟道长度下的热载流子退化,通过直接的实验证据,发现空穴陷阱俘获特性与应力时间呈对数关系.然后对不同应力电压、不同沟道长度下氧化层陷阱电荷(包括空穴和电子陷阱俘获)的产生做了进一步的分析.发现对于pMOSFET的热载流子退化,氧化层陷阱电荷产生分两步过程:在较短的应力初期,电子陷阱俘获是主要机制;而随着应力时间增加,空穴陷阱俘获作用逐渐显著,最后主导了氧化层陷阱电荷的产生.     

Hot carrier degradation modeling of short-channel n-FinFETs suitable for circuit simulators

The hot-carrier (HC) degradation of short-channel n-FinFETs is investigated. The experiments indicate that interface trap generation over the entire channel length, which is enhanced near the drain region, is the main degradation mechanism. The relation of the hot-carrier degradation with stress time, channel length, fin width and bias stress voltages at the drain and gate electrodes is presented. A HC degradation compact model is proposed, which is experimentally verified. The good accuracy of the degradation model makes it suitable for implementation in circuit simulation tools. The impact of the hot-carriers on a CMOS inverter is simulated using HSPICE.     

Impact of snapback-induced hole injection on gate oxide reliabilityof N-MOSFETs

N-channel MOSFETs associated with CMOS output driver circuits are often driven deep into snapback during electrostatic discharge (ESD) events. The charge-pumping technique is used to show significant hole trapping in the oxide resulting from snapback bias conditions. Floating-gate measurements verify that significant hole current flows through the oxide during snapback. It is noted that snapback-induced hole injection can dramatically reduce gate oxide charge to breakdown and explains reduced hot-carrier lifetimes after snapback stress. Snapback stress results in oxide damage that is in many ways similar to that found during hot-carrier stress and radiation damage. These long-term reliability concerns limit the maximum allowable snapback current     

热载流子应力下超薄栅p MOS器件氧化层陷阱电荷的表征

利用电荷泵技术研究了 4nmpMOSFET的热载流子应力下氧化层陷阱电荷的产生行为 .首先 ,对于不同沟道长度下的热载流子退化 ,通过直接的实验证据 ,发现空穴陷阱俘获特性与应力时间呈对数关系 .然后对不同应力电压、不同沟道长度下氧化层陷阱电荷 (包括空穴和电子陷阱俘获 )的产生做了进一步的分析 .发现对于 pMOSFET的热载流子退化 ,氧化层陷阱电荷产生分两步过程 :在较短的应力初期 ,电子陷阱俘获是主要机制 ;而随着应力时间增加 ,空穴陷阱俘获作用逐渐显著 ,最后主导了氧化层陷阱电荷的产生.     

A comprehensive study of hot-carrier instability in p- and n-typepoly-Si gated MOSFET's

A comprehensive comparison of hot-carrier instability between p- and n-type poly Si-gated MOSFET's is presented in this paper. The electron trapping and interface state generation in the 7 nm gate oxide of MOSFET's are investigated using uniform hot-electron injection from a buried junction injector (BJI) and channel-hot-carrier stress. From BJI experiments, electron trapping (instead of oxide trap generation) and interface state generation are shown to be the major effects of hot-electron injection. Electron trapping and interface state generation are found to be similar in both p- and n-type poly-Si gated MOSFET's. The dependences of interface state generation by hot electrons on oxide voltages and temperatures are observed to be similar between n- and p-type poly-Si gated MOSFET's. From the results of channel-hot-carrier stress on surface-channel n- and p-channel MOSFET's, it was also found that the channel-hot-carrier instabilities of p- and n-type poly-Si gated MOSFET's are comparable     

Hot-carrier stress effects on gate-induced-drain leakage current in n-channel MOSFETs studied by hydrogen/deuterium isotope effect

The degradation of gate-induced-drain leakage (GIDL) current under hot-carrier stress (HCS) has been studied in n-channel MOSFETs that were annealed in hydrogen (H) or deuterium (D). It is found that the degradation of GIDL current (I/sub GIDL/) can be effectively suppressed by deuterium passivation of interface traps. By using the H/D isotope effect, the impacts of oxide charge trapping (/spl Delta/N/sub ox/) and interface trap generation (/spl Delta/N/sub it/) on I/sub GIDL/ are successfully separated. The results indicate that, depending on stress and measurement conditions, I/sub GIDL/ may increase or decrease under HCS. /spl Delta/N/sub ox/ alters I/sub GIDL/ at high electric fields by varying the band-to-band tunneling current. /spl Delta/N/sub it/ alters I/sub GIDL/ at a low electric field by introducing a trap-assisted leakage component. Furthermore, evidence of hole trapping at the peak substrate current stress is indisputably presented for the first time and its impact on I/sub GIDL/ is discussed.     

Comparison of neutral electron trap generation by hot-carrierstress in n-MOSFET's with oxide and oxynitride gate dielectrics

A comparative study of neutral electron-trap generation due to hot-carrier stress in n-MOSFETs with pure oxide, NH₃-nitrided oxide (RTN), and reoxidized nitrided oxide (RTN/RTO) as gate dielectrics is reported. Results show that neutral electron trap generation is considerably suppressed by nitridation and reoxidation. The nature of neutral traps is described based on the kinetics of trap filling by electron injection into the gate dielectrics immediately after channel hot-electron stress (CHES). Improved endurance of the RTN and RTN/RTO oxides is explained using physical models related to interfacial strain relaxation     

Charge trapping in ultrathin hafnium silicate/metal gate stacks

Charge trapping characteristics of MOCVD HfSi/sub x/O/sub y/ (20% SiO/sub 2/) gate stack of n-MOSFETs during substrate injection have been investigated. Positive constant voltage stress (CVS) and constant current stress (CCS) were applied at the gate of TiN-HfSi/sub x/O/sub y/-SiO/sub 2//p-Si n-MOSFETs having EOT of 2 nm. Significant electron trapping is observed from the positive shift of threshold voltage (/spl Delta/V/sub t/) after stress. Curve fitting of the threshold voltage shift data confirms power law dependence for Hf-silicate gate stacks. Charge pumping measurements for both cases showed significant electron trapping at bulk Hf-silicate while interface trap generation was comparatively insignificant. A turn-around effect is noticed for /spl Delta/V/sub t/ as the stress current and voltage increases under CCS and CVS. Dependence of spatial distribution of charge trapping at shallow traps on stress level in the Hf-silicate film and redistribution of trapped charges during and after removal of stress is possibly responsible for the turn-around effect.     

A STUDY ON HOT-CARRIER-INDUCED GATE OXIDE BREAKDOWN IN PARTIALLY DEPLETED SIMOX MOSFET''''S

The hot-carrier-induced oxide regions in the front and back interfaces are systemati-cally studied for partially depleted SOI MOSFET's. The gate oxide properties are investigated forchannel hot-carrier effects. The hot-carrier-induced device degradations are analyzed using stressexperiments with three typical hot-carrier injection, i.e., the maximum gate current, maximumsubstrate current and parasitic bipolar transistor action. Experiments show that PMOSFET's