基于时域算法面积优化的RS解码器VLSI设计

在分析RS解码算法的基础上,使用便于VLSI实现和流水线设计的矢量运算对该算法进行了全新的剖析和推演,并依据所采用矢量法则的运算特征提出一种面积优化的RS解码器体系结构.通过流水线、部件复用、折叠以及共享电路等设计,该体系结构大大提高了解码器主要运算部件的复用率,降低了电路复杂度,删减了冗余电路,缩减了电路规模.基于该体系结构设计的RS(204,188)解码器规模约为27,000门,与同类设计相比电路规模可降低39%,其已集成到一款HDTV信道调制解调芯片中并在实际中得到应用.     

分段三次多项式逼近初等函数的硬件实现

针对分段二次多项式逼近初等函数需要较大的查找表面积和电路面积的问题,提出基于极大极小分段三次多项式逼近单精度浮点初等函数的算法,实现了单精度浮点倒数、平方根、平方根倒数、指数、对数和三角函数的逼近运算.首先缩小参数范围到一个特定的区间,并对该区间进行均匀分段,在每一分段区间上采用极大极小分段三次多项式逼近;然后在对应分段上综合考虑各种误差,在满足精度要求的情况下,通过多次Remes算法迭代优化出多项式系数的最优截取位宽,使查找表的面积最小;再对乘法器、平方器和立方器的输出位宽进行最优截取,使电路的面积最小;最后设计出硬件电路的整体架构.实验结果表明,与分段二次多项式逼近相比较,在同等精度要求下,该算法能够使电路时延减少17.25%,同时使查找表的面积减少53.60%、电路的总面积减少19.73%.     

低复杂度Log-MAP译码算法的研究

提出用插值函数来计算Log-MAP算法中的校正函数,并在AWGN信道上采用分段差值方法实现了Turbo译码。该算法解决了校正函数计算复杂度较大的问题,消除了译码计算中的指数和对数运算。仿真结果表明：用2段二次样条函数实现的Turbo译码器,其译码性能与Log-MAP算法等价,而计算的复杂度明显降低,运算时间大幅度减少。     

基于旋转模式的改进型CORDIC算法

传统CORDIC算法需要通过查找表和许多乘法器才能实现多种超越函数的计算,这会导致硬件电路实现复杂,运算速度降低,此外它能够计算的角度范围也有限.针对传统CORDIC算法的缺陷,在旋转模式下提出一种改进型CORDIC算法,它不需要查找表和模校正因子,只需通过简单的移位和加减运算就能实现多种超越函数的计算,从而能够减少硬件的开销,提高运算的性能,并通过重复迭代和区域变换使得该算法能够适用于所有的旋转角度.误差分析表明该算法具有很小的误差.     

有效的JPEG2000小波变换VLSI结构设计

基于提升的小波变换算法,提出了一种有效的JPEG2000小波变换的VLSI实现结构。采用了时分复用技术优化结构设计,实现了数据变换的细节分量和近似分量交替输出,以及有效减少了所用乘法器、加法器运算单元和寄存器单元数量,从而有效减少系统占用面积和功耗。该结构实现简单、规则,具有很好的扩展性,非常适合于VLSI设计实现。     

各向异性滤波器的硬件实现

在计算机图形学中,通常采用各项同性滤波器逼近异性滤波器以减少纹理映射中发生纹理走样,逼近算法中实现MIP-MAP层级包含计算覆盖区域边长以及求对数等操作,用二次逼近或者Cordic算法等实现时电路较大.为了易于算法的硬件实现,提出用线性逼近计算覆盖区域边长和对数的算法.该算法用一次移位和一次加法实现覆盖区域边长计算,用一次加法实现对数计算,降低了硬件实现成本.在Xilinx的ZC706开发板上实现了文中算法,实验结果表明,该算法所计算MIP-MAP的层级数与原算法的计算误差绝对值为1的概率为7%.     

基于泰勒展开的低成本e指数函数电路设计

针对e指数函数运算中常见硬件实现方法资源消耗大的问题,提出基于泰勒展开的指数函数的优化实现。首先,通过对输入值进行区间压缩以减小泰勒展开计算的求解误差;其次,对e指数函数泰勒展开公式的系数进行修正;最后,在硬件实现中通过合并化简运算实现资源的精简。实验表明。该方法在TSMC 65nm工艺下的面积为11068μm2,折合1976门,运算结果的相对误差仅有10-2~10-3。相比于通常泰勒展开式法,关键电路少了3个加法器和3个乘法器,节省60%的硬件资源,具有硬件资源消耗少、输入值范围宽、性能面积比高等优点。     

基于SD数据表示的大数除法VLSI高速实现

在诸如信息安全应用领域中,除法运算特别是大数（多个机器字长整数）除法运算速度是制约公钥密码算法运算速度提高的瓶颈。针对公钥密码算法VLSI实现需要,本文在介绍SD数据表示的基础提出了一种新的大数除法算法,并给出了其VLSI实现逻辑结构。实验结果表明,这种除法器的VLSI实现具有很好的性价比。     

基于硬件优化的H.264 VBSME SAD算法及其VLSI结构

以硬件代价优化为目的,对H.264宏块级的VBSME SAD VLSI结构进行了详细的分析,提出一种像素平滑重采样的SAD算法及其VLSI结构.该算法先将当前块和参考块像素划分成2×2的子块进行平滑和重采样,再进行7种可变块大小的SAD运算,以有效地降低SAD运算中级联加法器的深度和宽度,减少硬件代价.实验结果表明,该算法的编码性能与SAD标准算法的RDO曲线相比偏差小于1%, 而硬件面积和功耗在不同的综合时钟频率下可节省53%以上.鉴于其优良的硬件性能,文中算法及其结构非常适合高并行度的H.264 VLSI解决方案.     

二维NLMS自适应算法的结构设计

针对TDNLMS（Two-Dimmsional Normalized Least Mean Square）自适应算法VLSI实现中工作速度的问题,提出两种解决方案。一种是对标准算法中的某些参数进行量化处理,以移位操作代替除法运算;一种是采用流水线结构,提高数据通过率。实验证明,这两种结构能有效的缩短运算时间,提高工作速度,使设计方案更加具有实用性,而且采用两种结构设计的电路仍然能够保持较好的算法性能。     

一种改进的基于FPGA的32位对数变换器的设计与实现

对数变换器是对数乘法器的重要组成部分,它们以精度换取更快的速度.设计并实现了一种基于FPGA的32位二进制对数变换器,主要由先导"1"检测电路、移位逻辑和误差校正电路组成,通过有效的误差校正算法提高了计算精度;给出了一种新的4位、16位和32位的基于FPGA的并行先导"1"检测电路PLOD,在保持低延时的同时,减小了先导"1"检测电路的功耗和面积;改进了现有的6-域校正算法,在提高精度的同时保持了硬件电路的规整性,降低了系统复杂度及面积和功耗开销;分两站流水实现校正操作,提高了系统的吞吐率;改进后的校正电路将对数操作的最大误差由30%降低到20%,区域1的平均误差大幅度降低.     

浮点加法运算器前导1预判电路的实现

提出了一种应用于浮点加法器设计中前导1预判电路(LOP)的实现方案。此方案的提出是针对进行浮点加减运算时,尾数相减的结果可能会产生若干个头零,对于前导1的判断将直接影响规格化左移的位数而提出的。前导1的预判与尾数的减法运算并行执行,而不是对减法结果的判断,同时,并行检测预判中可能产生的1位误差,有效缩短了整个加法器的延时。LOP电路设计采用VHDL语言门级描述,已通过逻辑仿真验证,并在浮点加法器的设计中得到应用。     

2D Vector field approximation using linear neighborhoods

We present a vector field approximation for two-dimensional vector fields that preserves their topology and significantly reduces the memory footprint. This approximation is based on a segmentation. The flow within each segmentation region is approximated by an affine linear function. The implementation is driven by four aims: (1) the approximation preserves the original topology; (2) the maximal approximation error is below a user-defined threshold in all regions; (3) the number of regions is as small as possible; and (4) each point has the minimal approximation error. The generation of an optimal solution is computationally infeasible. We discuss this problem and provide a greedy strategy to efficiently compute a sensible segmentation that considers the four aims. Finally, we use the region-wise affine linear approximation to compute a simplified grid for the vector field.     

Padé error estimates for the logarithm of a matrix

The error of Padé approximations to the logarithm of a matrix and related hypergeometric functions is analysed. By obtaining an exact error expansion with positive coefficients, it is shown that the error in the matrix approximation at X is always less than the scalar approximation error at x, when ∥X∥ < x. A more detailed analysis, involving the interlacing properties of the zeros of the Padé denominator polynomials, shows that for a given order of approximation, the diagonal Padé approximants are the most accurate. Similarly, knowing that the denominator zeros must lie in the interval (1,∞) leads to a simple upper bound on the condition number of the matrix denominator polynomial, which is a crucial indicator of how accurately the matrix Padé approximants can be evaluated numerically. In this respect the Padé approximants to the logarithm are very well conditioned for ∥X∥ < 0·25. This latter condition can be ensured by using the ‘inverse scaling and squaring’ procedure for evaluating the logarithm.     

Accurate estimation of decay coefficients for dynamic range compressors in hearing aids and a hardware level comparison of different architectures

Dynamic Range Compression (DRC) algorithm helps to protect the residual hearing ability of hearing aid users by compressing the signal levels which go above a particular threshold. This paper addresses two different aspects of DRC for hearing aid applications. In the first part, methods to estimate the decay coefficients corresponding to the required time constants for a feed-forward DRC architecture accurately, to meet the hearing aid specifications are proposed. The effect of compression on the attack and release time parameters are compensated with the new formula. The hardware implementation of four different DRC architectures is explained in the second part of the paper. The estimated decay coefficients for a test signal were used for the corresponding hardware implementations and verified the validity of proposed algorithmic modifications. The architectures were implemented using UMC 65 nm standard cell libraries and the power and error results were compared. The proposed methods to estimate the decay coefficients for both attack and release phases show close to 0 dB error from expected output values, while conventional methods are not meeting the specifications. Hardware implementation shows that there is not much improvement in power performance, between a lower resolution Look-Up Table (LUT) based logarithm implementation and a higher resolution one. From the results, we propose using the absolute level detector based DRC with higher resolution logarithm without a gain smoothing stage at the output for lowest power consumption and better approximation error performance.     

智能CO探测器设计

设计了一种基于电化学传感器的CO探测器,探测器使用CO—7G燃料电池型电化学CO传感器,分析了CO电化学传感器的工作原理与探测器的电路组成。其中,探测器的硬件电路由电化学传感器的信号调理电路、数码管显示电路、单片机数据处理与控制电路、4~20mA模拟输出电路、继电器控制电路等组成。对采集的数据采用均值滤波算法,提高了系统的灵敏度,减少了探测器的响应时间,降低了误报警率。实验结果表明:该CO探测器的误差小于0.001 16 mg/L,在1个月的时间内其误差没有超过0.005 82 mg/L。该CO探测器灵敏度高,响应时间短,测量精度高,稳定性好,具有很高的实用价值。     

Evolutionary design of complex approximate combinational circuits

Functional approximation is one of the methods allowing designers to approximate circuits at the level of logic behavior. By introducing a suitable functional approximation, power consumption, area or delay of a circuit can be reduced if some errors are acceptable in a particular application. As the error quantification is usually based on an arithmetic error metric in existing approximation methods, these methods are primarily suitable for the approximation of arithmetic and signal processing circuits. This paper deals with the approximation of general logic (such as pattern matching circuits and complex encoders) in which no additional information is usually available to establish a suitable error metric and hence the error of approximation is expressed in terms of Hamming distance between the output values produced by a candidate approximate circuit and the accurate circuit. We propose a circuit approximation method based on Cartesian genetic programming in which gate-level circuits are internally represented using directed acyclic graphs. In order to eliminate the well-known scalability problems of evolutionary circuit design, the error of approximation is determined by binary decision diagrams. The method is analyzed in terms of computational time and quality of approximation. It is able to deliver detailed Pareto fronts showing various compromises between the area, delay and error. Results are presented for 16 circuits (with 27–50 inputs) that are too complex to be approximated by means of existing evolutionary circuit design methods.     

语音MFCC特征提取的FPGA实现

提出了在FPGA上实现语音MFCC特征提取的方法,巧妙设计了FFT、三角滤波、取对数和DCT的硬件结构,采hl多时钟、状态机、模块复用、IP核和多级流水技术,大大提高了运算速度,实验表明与软件相比,结果误差在l%以内,50M时钟频率下每秒语音数据计算时间仅为8.5 ms,与VQ、HMM结合后,对系统识别率影响可以忽略,达到了嵌入式实时系统的应用要求.     

Design of BCD adder with five input majority gate for QCA

In the digital world BCD numbers play a pivotal role in constituting decimal numbers. New different technologies are emerging in order to obtain low area/power/delay factors to replace the CMOS technology. One such technology is quantum cellular automata (QCA) realization, through which many arithmetic circuits can be designed. This paper deals with the implementation of BCD adder with 5 input majority gates for QCA. The 3 input majority gate and an inverter are basic elements of QCA. In this project amalgamation of majority gates with 3 and 5 inputs are used instead of implementing the entire circuit using 3 input majority gate in the BCD i.e. mainly comprised by partly consumed gates and entirely consumed gates. The proposed is designed and functional verification is done by Verilog HDL and Modelsim version 10.4a. The proposed design has been verified and the delay of existing and proposed design is analysed using Xilinx tool. The numbers of partly consumed and entirely consumed gates are less when compared to the existing method of implementation. The delay is reduced compared to the existing system which shows the improvement of 9.84%. The drawback of crossovers that leads the difficulty in implementation and reduces the efficiency of the circuit is reduced in the proposed implementation.     

自动纠错CRO PUF密钥生成方案

针对射频识别(Radio Frequency Identification,RFID)安全问题中的加密技术,设计了自动纠错CRO PUF密钥生成方案。该方案将数字通信系统中重复码的纠错思想应用到可配置环形振荡器物理不可克隆函数(Configurable Ring-oscillator Physical Unclonable Function,CRO PUF)结构中,对相邻CRO的最终振荡频率进差行分运算得到3位输出响应值,然后对输出响应值进行纠错处理,得到一位自动纠错CRO PUF输出信息,从而实现CRO PUF电路自动纠错;利用模糊提取器中注册阶段和重构阶段的纠错码编解码技术的纠错特性来纠正复现输出信息向量存在的比特跳变误差,然后使用Hash模块对纠错后的PUF复现输出信息向量进行数据加密以生成密钥。基于Linux系统,利用Cadence virtuoso中specture环境下的TSMCO 0.18 um,1.8 V CMOS0工艺库对自动纠错CRO PUF电路进行Monte Carlo模拟仿真,使用MATLAB对PUF电路复现输出信息向量进行模糊提取器处理。由仿真实验数据可得,自动纠错CRO PUF电路在电源电压影响下的最高、最低可靠性分别为98.96%和92.71%;在温度影响下的最高、最低可靠性分别为99.10%和93.75%。实验结果表明,相对于CRO PUF电路,自动纠错CRO PUF的可靠性与均匀性有了明显提高;从整体情况看,自动纠错CRO PUF与CRO PUF电路的唯一性没有一方处于明显的优势或劣势,但对两组数据进行方差计算和比较后发现,自动纠错CRO PUF的唯一性与标准值50%之间有着更好的逼近效果。经模糊提取器处理后的PUF复现输出响应向量的可靠性进一步提高,且高达99.8%,其受环境因素干扰非常小,可直接用作密钥。