A Fine-Grained Software-Implemented DMA Fault Tolerance for SoC Against Soft Error

In system-on-chips (SoCs), DMA, as a peripheral module, plays an important role in data transmission. However, the structure shrinking of SoC leads to its proneness to radiation-induced soft errors, especially for DMA. This paper presents a fine-grained software-implemented fault tolerance for SoC, named DCRH, to enhance the reliability of DMA against soft errors. DCRH achieves fine-grained selective fault tolerance, protecting DMA without interfering other modules of SoC. Furthermore, it is transparent to the user application because it performs on driver layer. In this paper, we present our fault source analysis for DMA based on Xilinx Zynq-7010 SoC and the detailed design of DCRH. The method is then applied to bare-metal MicroZed so that a DCRH-enhanced DMA driver is developed. Finally, SSIFFI is engaged in the simulated DMA fault injection experiments to validate DCRH. The experimental results prove that DCRH can achieve high fault coverage for DMA, above 97%, with stable performance.     

Online Fault Tolerance for FPGA Logic Blocks

Most adaptive computing systems use reconfigurable hardware in the form of field programmable gate arrays (FPGAs). For these systems to be fielded in harsh environments where high reliability and availability are a must, the applications running on the FPGAs must tolerate hardware faults that may occur during the lifetime of the system. In this paper, we present new fault-tolerant techniques for FPGA logic blocks, developed as part of the roving self-test areas (STARs) approach to online testing, diagnosis, and reconfiguration . Our techniques can handle large numbers of faults (we show tolerance of over 100 logic faults via actual implementation on an FPGA consisting of a 20 times 20 array of logic blocks). A key novel feature is the reuse of defective logic blocks to increase the number of effective spares and extend the mission life. To increase fault tolerance, we not only use nonfaulty parts of defective or partially faulty logic blocks, but we also use faulty parts of defective logic blocks in nonfaulty modes. By using and reusing faulty resources, our multilevel approach extends the number of tolerable faults beyond the number of currently available spare logic resources. Unlike many column, row, or tile-based methods, our multilevel approach can tolerate not only faults that are evenly distributed over the logic area, but also clusters of faults in the same local area. Furthermore, system operation is not interrupted for fault diagnosis or for computing fault-bypassing configurations. Our fault tolerance techniques have been implemented using ORCA 2C series FPGAs which feature incremental dynamic runtime reconfiguration     

Optimization Technique for Dynamic Reconfiguration of Programmable Analog/Digital Arrays

This paper presents an investigation of dynamically reconfigurable mixed-signal circuit constructed using a digital control system and the new technology of Field Programmable Analog Arrays (FPAA). A Motorola FPAA described in this paper can be used to build filters for analog signals as well as other kinds of analog applications implemented in switched capacitor technology (S/C-technology). The experimental studies described, take advantage of performance and programmability of the FPAA for filtering of an analog signal. The circuit structure is based on 2 parallel FPAA chips, analog multiplexer and multiplexer's control logic controlled by a digital system such as a PC or a Field Programmable Gate Array (FPGA). Dynamic reconfiguration is used in this system for adaptive filtering, or adaptive processing in general. Modeling and measurements of the transition behavior of the switching process between the 2 FPAA chips and analysis of limitations imposed by hardware imperfections will be presented. The experimental system assembled in this work is an excellent vehicle to learn about intricacies in performance of mixed-signal circuits and is used for verification of theoretical predictions and model validation/modification.     

Fault Tolerance of Switch Blocks and Switch Block Arrays in FPGA

A new application-independent approach for evaluating the fault tolerance of field-programmable gate-array (FPGA) interconnect structures is presented. Signal routing in the presence of faulty resources at switch block and FPGA levels is analyzed; this problem is directly related to the fault tolerance of FPGA interconnects for testing and reconfiguration at manufacturing and run-time applications. Two criteria are proposed and used as figure-of-merit for evaluating different FPGA interconnect architectures. The proposed approach is based on the number of available paths between pairs of end points and the probability to establish a one-to-one mapping between all input and output end points. A probabilistic approach is also presented to evaluate the fault-tolerant routing of the entire FPGA by connecting switch blocks in chains, as required for testing and to account for the input–output (I/O) pin restrictions of an FPGA chip. All possible interconnect faults for programmable switches and wiring channels are considered in the fault model. The proposed method is applicable to arbitrary switch block structures. Experimental results on commercial as well as academic designed FPGAs are presented and analyzed.     

IC Cost Reduction by Applying Embedded Fault Tolerance for Soft Errors

Fault tolerant design is a technique emerging in Integrated Circuits (ICs) to deal with the increasing error susceptibility (Soft Errors, Single Event Upsets, (SEUs)) caused by e.g. alpha particles. A side effect of these methods is that they also compensate for manufacturing defects, thereby increasing the yield and lowering the production cost in certain conditions. In this paper, it is shown that increasing the IC area (by applying fault tolerant design techniques for SEUs) leads to a synergistic advantage under certain conditions: lower production costs because of a better yield. To guide designers in deciding when the fault tolerant techniques are beneficial, break-even points between fault tolerant and regular designs are presented as function of IC area, fault tolerant overhead and defect density.     

PSoC的动态重配置

本文通过对PSoC的动态重配置方案的探讨,分析了如何充分利用资源,实现硅芯片性能的最大化.     

基于FPGA实现随机逻辑的混合不确定性故障树分析研究

文中提出一种基于随机逻辑的故障树分析方法,即使用混合故障树分析(HFTA)来兼顾客观不确定性和主观不确定性。该方法将每个故障树逻辑门转换为其对应的随机逻辑模块,然后在现场可编程门阵列(FPGA)中实现。随后在a截集置信度水平等于0的情况下比较常规方法和本文方法的精度和性能。分析结果表明,相较于常规混合不确定性分析方法,文中提出的方法缩短了分析时间。由于与常规混合方法的顶事件概率累积分布函数基本相容,可以认为新方法与常规混合方法的结果精度基本一致。     

航空发动机传感器故障诊断与自适应重构控制

针对航空发动机控制系统中最易发生故障的传感器,提出了基于状态观测器的故障诊断与自适应重构控制方法.设计了多个状态观测器用于传感器的状态估计,采用阈值判别法对传感器进行实时故障监视与诊断,并用正常传感器测量值的加权均值代替故障传感器测量值反馈回闭环系统,实现了对发动机闭环系统的自适应重构控制.数字仿真结果表明,该方法能及时准确地定位故障,并进行有效的自适应重构控制,将其应用于航空发动机的故障诊断与自适应重构控制是可行、有效的.     

Preprocessing and Partial Rerouting Techniques for Accelerating Reconfiguration of Degradable VLSI Arrays

This paper presents novel techniques to accelerate the reconfiguration of degradable very large scale integration arrays. A preprocessing step is used to derive the upper and lower size bounds of the maximum logical array (MLA) such that only those subarrays that possibly contain the MLA are reconfigured, thereby reducing the reconfiguration time and also obtaining a same-sized logical array. In addition, the partial rerouting approach is generalized so that as many as possible previous routing results can be reused in the current rerouting step. The reconfiguration time is reduced from $ O((1-rho)cdot beta cdot m cdot n)$ to its lower bound $ O((1-rho)cdot mcdot n)$ for $ mtimes n$ host arrays with small fault density $ rho $, where $ beta $ is the expected routing length required per logical column.      

Dynamic Virtual Topology Reconfiguration Algorithms for Groomed WDM Networks

In a Wavelength Division Multiplexing (WDM) optical network, in which the traffic changes dynamically, the virtual topology designed for an old traffic set needs to be reconfigured for a new demand set in order to route more connections. Though reconfiguration increases the throughput, the resulting disruption in traffic is a cause for concern. We present a simple and flexible framework to evaluate the gain achieved by reconfiguration, based on the two conflicting objectives of increasing throughput and reducing disruption. We present adaptive reconfiguration algorithms which determine the change in the virtual topology with a corresponding change in the demand set. These algorithms incrementally add lightpaths to a given virtual topology and delete a minimum number of lightpaths to facilitate their addition. One of the algorithms improves throughput by making changes to the existing virtual topology and another one reduces disruption by making changes to the virtual topology suited for the new demand set. However, in order to reduce the gap in bandwidths between what a wavelength channel can provide and what an individual connection requires, several low-speed connections need to be groomed onto a single wavelength. As our algorithms aim at increasing the throughput with as few lightpath changes as possible, more connections will be accepted without considerable increase in number of lightpaths. This means, more connections are groomed onto the lightpaths. One nice feature of our approach is that it fits not only for groomed networks where traffic demands are at the sub wavelength level, but also for networks where connection demands are at the wavelength level. The extensive simulation studies, wherein we compared the performance of our algorithms with that of two other possible schemes, demonstrated their flexibility and robustness. This work was supported by the Department of Science and Technology, New Delhi, India.     

Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration

The research described in this paper shows how the runtime relocation of a reconfigurable component can be obtained using a system component that is able to update the bitstream information, moving the reconfigurable module in the desired position. This scenario defines the so-called partial bitstream relocation activity. This paper proposes a relocation filter that can be implemented both as a hardware and a software component. The former is hosted in the static part of the reconfigurable architecture, while the latter is made to be run on the processor placed on the field-programmable gate array (FPGA). The proposed approach has also been validated over different FPGAs, i.e., Virtex II Pro, Virtex 4, and Virtex 5, proposing a runtime relocation support that can be customized to meet all the different constraints associated with these different target architectures.     

FPGA动态局部可重构中基于TBUF总线宏设计

FPGA动态局部可重构技术通常将系统划分为固定模块和可重构模块,可重构模块与其他模块之间的通信都是通过使用特殊的总线宏实现的.总线宏的正确设计是实现FPGA动态局部可重构技术的关键.在研究了FPGA动态局部可重构技术中基于三态缓冲器(Tri-state Buffer,TBUF)总线宏结构的基础上,采用Xilinx ISE FPGA Editor可视化的方法实现总线宏的设计,并借助可重构硬件平台--XCV800验证板,通过设计动态可重构实验,论证总线宏设计的正确性.     

双机容错方案设计

介绍了双机容错的两种基本构架模式：双机互备援模式和双机热备份模式,利用马尔科夫模型对两者的可靠性进行了分析、比较;针对不同的用户给出了相应的双机窖错设计方案．并对两种方案的优缺点进行了分析。     

具有容错功能的OLED有源驱动电路

以有机电致发光器件(OLED)为基础的显示或照明器件,通常会受到短路故障的影响,从而使得像素失效,降低面板的亮度,进而严重地影响亮度的均匀性,并且会产生大量的功耗.本文介绍了一种新的有源OLED驱动电路,以自动检测在OLED中发生的短路故障并切换至备用OLED.该电路采用p型低温多晶硅薄膜晶体管制造.当发生短路故障时,本电路可以在不改变驱动电流的情况下,保持OLED像素的亮度维持不变.实验结果表明,本电路不仅具有容错功能,而且与标准电路相比可以显著地降低功耗.     

低冗余并行总线容错技术

本文将从分析Ｍｕｌｔｉｂｕｓ总线功能入后，讨论多种总线容错技术及实时重构总线系统的方法，并具体分析各种容错技术对可靠性指标的影响程度。     

具有容错功能的OLED有源驱动电路

以有机电致发光器件(OLED)为基础的显示或照明器件,通常会受到短路故障的影响,从而使得像素失效,降低面板的亮度,进而严重地影响亮度的均匀性,并且会产生大量的功耗.本文介绍了一种新的有源OLED驱动电路,以自动检测在OLED中发生的短路故障并切换至备用OLED.该电路采用p型低温多晶硅薄膜晶体管制造.当发生短路故障时,本电路可以在不改变驱动电流的情况下,保持OLED像素的亮度维持不变.实验结果表明,本电路不仅具有容错功能,而且与标准电路相比可以显著地降低功耗.     

网络服务器容错技术

网络服务器通常处理的是关键性任务,不允许信息丢失及异常停机等情况出现,介绍了目前广泛使用的ＲＡＩＤ（廉价磁盘冗余阵列技术）,探讨了双机容错技术和群集技术,给出了典型的应用实例。