基于IIR抗混叠干扰滤波器的相干跳频同步技术研究

无线通信波形设计中,扩频通信是常用的抗干扰设计体制。其中,相干跳频波形因为具有更好的抗干扰性能而受到广泛研究,相干跳频波形的抗干扰性能也与抗干扰滤波器的性能成正相关。受限于传统的FPGA资源和AD采样率,相干跳频波形研究方法是结合射频前端多频点下变频+软件无线电平台窄带同步的设计与实现架构,本文采取射频前端全带宽采样+软件无线电平台宽带同步的设计与实现架构。抗干扰滤波器通常设计基于FIR的低通滤波器结构,但是相比于IIR滤波器,其资源占用高。本文提出基于IIR的低通滤波器结构和作为抗干扰滤波器,采用相位非线性补偿,确保施加不同干扰情况下相干跳频波形的抗干扰性能保持不变。     

基于FPGA的IIR数字滤波器的设计与实现

介绍一种使用二阶节级联方法在FPGA上实现任意阶数的IIR（无限脉冲响应）数字滤波器的原理和方法。首先在Matlab软件的Simulink仿真工具箱上设计了符合要求的滤波器,进一步通过VerilogHDL硬件描述语言加以描述,最后在Altera公司的QuartusⅡ软件上实现了IIR滤波器的设计、综合和仿真。这种设计方案的选择使得最终的设计产品具有更好的灵活性和适应范围。     

IIR滤波器的设计研究

对比了IIR滤波器和FIR滤波器的性能,选择IIR滤波器进行设计,利用MATLAB对设计进行了仿真,并转化为HDL语言在ISE中进行了综合;在ModelSim中进行了仿真,验证了HDL代码的正确性,并进行了波形的测试。结果表明:利用MAT-LAB、ISE和ModelSim三个软件,可以对所设计的IIR滤波器进行验证,通过这种方法,可以大大缩短电子产品的研发周期。     

A New Design Approach for Nearly Linear Phase Stable IIR Filter using Fractional Derivative

In this paper,a new design method for digital infinite impulse response(IIR)filters with nearly linear-phase response is presented using fractional derivative constraints(FDCs).In the proposed method,design problem of an IIR frlter is constructed as the minimization of phase error between the desired and designed phase response of an allpass filter(APF)such that the designed lowpass filter(LPF)or highpass frlter(HPF)yields less passband(ep),and stopband errors(es)with optimal stopband attenuation(As).In order to have accurate passband(pb)response,FDCs are imposed on appropriate reference frequency,where the optimality of these FDCs are ensured by using a new greedy based sorting mechanism.The simulated results reflect the efficiency of the proposed method in term of improved passband response along with better transition width.However,small reduction in^is observed within the allowable limit,when compared to noin-fractional design approach,but the designed filter remains immune to wordlength(WL)effect.     

Transformation to implement computationally efficient IIR decimation filters

A new technique is proposed to transform an IIR filter into a computationally efficient decimation filter. In this technique, the recursive transfer function is transformed and noble identity is invoked to get sample rate reduction. The magnitude and phase response of the original filter are unaltered after the transformation. A higher order IIR transfer function is decomposed into parallel first-order sections and each section is transformed for sample rate reduction. The transformation is computationally efficient since current output can be directly computed from single Mth old output and M inputs processed using polyphase decomposition. Filtering and down sampling are performed in the same stage. Filters are designed and mapped on FPGA. Hardware and computational complexities are reduced and throughput is enhanced.     

AN OPTIMAL DESIGN OF IIR DIGITAL FILTER USING PARTICLE SWARM OPTIMIZATION

In this article, a novel approach for infinite-impulse response (IIR) digital filters using particle swarm optimization (PSO) is presented. IIR filter is essentially a digital filter with recursive responses. Because the error surface of digital IIR filters is generally nonlinear and multimodal, so global optimization techniques are required in order to avoid local minima. This study is based on a heuristic way to design IIR filters. PSO is a powerful global optimization algorithm introduced in combinatorial optimization problems. This study finds the optimum coefficients of the IIR digital filter through PSO. It is found that the calculated values are more optimal than the FDA tool and GA available for the design of the filter in MATLAB. Design of low-pass and high-pass IIR digital filters is proposed in order to provide an estimate of the transition band. The simulation results of the employed examples show an improvement on the transition band. The stability of designed filters is described by the position of Pole-Zeros.     

自适应IIR滤波器设计策略研究

根据IIR滤波器存在突出的缺点,对自适应IIR滤波器设计进行策略性研究。分别讨论输出误差法(OEM)和方程误差法(EEM)在设计自适应滤波器的应用。通过对仿真结果进行分析比较,修正的EEM克服OEM在设计结果中存在多个局部极小值的不足,优于OEM。从而提出设计自适应滤波器的策略和实现途径。     

IIR滤波器结构分析和Blackfin DSP定点优化实现

ADI公司推出的Blackfin系列DSP获得了广泛的应用,其开发软件VisualDSP++提供了大量定点函数库可供用户使用,但其中的IIR滤波器函数iir_fr16要求滤波器系数必须在[-1,+1]范围内,这在应用上有很大的局限性。本文对IIR滤波器的结构和实现进行全面的分析后提出了优化方法,并设计一个8阶定点IIR低通滤波器进行验证,经仿真和实际测试,其性能指标完全达到设计要求。     

脑电反馈系统中精度扩展的IIR数字滤波器实现

在脑电反馈系统中,对脑电进行滤波以获取系统处理所需频段信号是实现系统功能的一个重要部分,考虑到脑电信号的特点和无限冲击响应（IIR）滤波器具有的各种优点,在系统中该功能采用IIR滤波器实现,同时由于系统硬件的字长精度有限,直接在其上实现滤波器会导致出现较大误差以及工作不稳定的现象,需要对滤波器进行精度扩展。本文介绍了在脑电反馈系统上实现的精度扩展皿滤波器的设计原理,并对实现的细节系统地进行了描述。     

Digital IIR Filter Design Using Adaptive Simulated Annealing

Chen, S., Istepanian, R., and Luk, B. L., Digital IIR Filter Design Using Adaptive Simulated Annealing, Digital Signal Processing11 (2001) 241–251Adaptive infinite-impulse-response (IIR) filtering provides a powerful approach for solving a variety of practical problems. Because the error surface of IIR filters is generally multimodal, global optimization techniques are required in order to avoid local minima. We apply a global optimization method, called the adaptive simulated annealing (ASA), to digital IIR filter design. An important advantage of the ASA is the simplicity in software programming. Simulation study involving system identification application shows that the proposed approach is accurate and has a fast convergence rate, and the results obtained demonstrate that the ASA offers a viable tool to digital IIR filter design.     

IIR滤波器的测试及可测性设计

基于加法器测试生成,提出了无限脉冲响应(IIR)滤波器的一种通用可测性设计、测试方案.在测试模式下,通过切断IIR滤波器中的反馈回路提高了该设计的可测性.通过复用原电路中的部分寄存器和加法器来提高其可测性,降低了额外的测试硬件面积开销.该方法能在真速下高效地侦测到IIR滤波器基本组成单元内的任意固定型组合失效,没有降低电路性能.     

一种基于电力系统保护的模型化数字滤波器的设计

提出了基于FPGA的新型电力载波继电保护系统的滤波器设计方法,充分利用FPGA的优势,设计了一种高性能的IIR滤波器,在FPGA中加以实现.仿真结果表明,所设计的滤波器具有速度快、滤波效果好、修改灵活等优点.     

Fixed-point digital IIR filter design using two-stage ensemble evolutionary algorithm

The research on optimal design of infinite-impulse response (IIR) filter design based on various optimization techniques, including evolutionary algorithms (EAs), has gained much attention in recent years. Previously, the parameters of digital IIR filters are encoded with floating-point representations. It is known that a fixed-point representation can effectively save computational resources and is more convenient for direct realization on hardware. Inherently, compared with the floating-point representation, the fixed-point representation would make the search space miss much useful gradient information and therefore, surely rises new challenges for continuous EAs. In this paper, we first analyze the fitness landscape properties of optimal digital IIR filter design. Based on the fitness landscape investigation, a two-stage ensemble evolutionary algorithm (TEEA) is applied to digital IIR filter design with fixed-point representation. In order to fully evaluate the performance of TEEA, we experimentally compare it with five state-of-the-art EAs on four types of digital IIR filters with different settings. Based on the experimental results, we can conclude that TEEA has higher convergence speed, better exploration, and higher success rate. In order to benchmark TEEA further, we apply it to some more difficult problems with shorter word length or higher order. We can find that TEEA can provide satisfying performance on these hard tasks as well.     

Miniature on-chip band pass filter for RF applications

Multilayer on-chip inductor and capacitor are proposed in this paper. These passive on-chip components are combined to form series LC on-chip band pass filter and are designed based on VLSI multilayer design concepts to operate at high frequency range applications. Development in RF-VLSI circuits demanded low size on-chip filters to operate at higher order frequency range with better tuning response. Design and simulation of on-chip passive components is carried out in high frequency structural simulator to obtain scattering parameters required for analysis. The designed filter model has good compromise between S ₁₁ and S ₂₁ parameters against frequency satisfying basic conditions of on-chip band pass filter. Proposed filter circuit has centre frequency at 39.5 GHz, bandwidth of 3.17 GHz, loaded Q value of 12.5, fractional bandwidth of 8 % which is suitable for narrow band operations and occupies an on-chip area of 0.0256 mm². This miniature on-chip band pass filter reduces the size and cost of the chip significantly at radio frequencies when compared with existing models.

     

Through-silicon via technologies for interconnects in RF MEMS

In this paper, we describe the application of through-silicon via (TSV) interconnects in Radio Frequency Micro-electro-mechanical systems (RF MEMS). Using TSV technologies as grounding connections, a Ku band miniature bandpass filter is designed and fabricated. Measured results show an insertion loss of 1.9 dB and a bandwidth of 20%. The chip size is 9.6 × 4 × 0.4 mm³. Using TSV as interconnections for 3 dimensional millimeter-wave integrated circuits, a silicon micromachined vertical transition with three layers is presented. TSV, alignment, bonding and wafer thinning technologies are used to fabricate the sample. This transition has an insertion loss of less than 6.7 dB from 26 to 34 GHz and its amplitude variation is less than 2 dB. The total size of the chip is 6.3 × 3.2 mm².     

基于FPGA的IIR数字滤波器的设计与仿真

提出一种在FPGA中实现高速IIR数字滤波器的方法,在理论上分析了IIR数字滤波器系数取整后的稳定性问题;利用FDATool设计滤波器,在Matlab中编程仿真;使用实验仿真的方法确定IIR滤波器系数量化字长,保证了IIR滤波器性能和硬件资源的优化,使IIR滤波器能适用高速场合,研究了FPGA中运算部件的运算特点,采用Verilog硬件描述语言实现迭代运算及有符号数乘法;最后编程实现IIR数字滤波器,通过Quartusll仿真并在FPGA上实现.通过试验验证,该方法设计的IIR数字滤波器收敛,能适用于对实时性要求高的系统中.     

基于MATLAB的IIR数字滤波器设计与仿真

依据IIR型数字滤波器设计的传统方法,利用MATLAB信号处理工具箱(Signal Processing Toolbox),分别用三种不同的方法快速有效地实现了对IIR数字滤波器的设计与仿真.给出了使用MATLAB语言进行程序设计和利用信号处理工具箱的FDATool工具进行界面设计的详细步骤.进一步说明了如何利用MATLAB环境下的仿真软件Simulink对所设计的滤波器进行动态仿真.     

基于FPGA的ⅡR滤波器整数设计

提出了一种在FPGA中以整数方式实现IIR滤波器的方法，讨论了取整舍入误差对IIR滤波器的稳定性影响．针对df2形式及FPGA迭代运算提出以变量T的传函增益限定输入信号范围的方法，使得IIR滤波器在FPGA中稳定运行；最后给出编程方法。通过实验验证，该方法设计的IIR滤波器收敛，具有广泛的工程应用。     

改进的结构进化无限冲激响应数字滤波器设计方法

为了进一步提高无限冲激击响应（IIR）数字滤波器的性能,提出了一种基于结构和参数同时进化的IIR数字滤波器设计方法。首先,通过遗传算法（GA）得到初始滤波器结构;然后,利用差分进化（DE）算法优化滤波器参数;最后,通过动态调整个体搜索步长和双向试探搜索的改进寻优算法对滤波器参数进一步优化,并将该算法用于低通、高通数字滤波器的设计。同基于遗传算法结构进化的IIR滤波器方法相比,继续利用差分进化算法和改进的寻优算法优化乘法器参数得到的低通数字滤波器的通带性能相差不大,但是过渡带宽度减小了65%,阻带最小衰减下降了36.48 dB;得到的高通数字滤波器通带波纹减少了75%,过渡带宽度减小了44%,阻带最小衰减下降了12.13 dB。实验仿真结果表明,所提方法可以获得性能更佳的滤波器,是一种有效可行的IIR数字滤波器的设计方法。