高性能的EBCOT编码及其VLSI结构

提出了比特平面与编码过程全并行处理的EBCOT(embedded block coding with optimizedtruncation)编码结构.通过分析JPEG2000和国内外提出的EBCOT编码结构,指出不仅每一个比特平面,而且对应的编码过程的编码信息可以同时获得,从而给出了比特平面与编码过程全并行处理的块编码方法,并且详细说明了实现的VLSI结构.理论分析以及具体实验结果表明,比特平面与编码过程全并行处理所需的时钟周期最少,FPGA原型系统最高时钟频率可达65MHz,对于512×512的灰度图像,处理速度可达30fps,完全可以实时处理,图像质量达到了公布的JPEG2000标准.     

Multi-scale neural texture classification using the GPU as a stream processing engine

A neural architecture for texture classification running on the Graphics Processing Unit (GPU) under a stream processing model is presented in this paper. Textural features extraction is done in three different scales, it is based on the computations that take place on the mammalian primary visual pathway and incorporates both structural and color information. Feature vectors classification is done using a fuzzy neural network which introduces pattern analysis for orientation invariant texture recognition. Performance tests are done over a varying number of textures and the entire VisTex database. The intrinsic parallelism of the neural system led us to implement the whole architecture to run on GPUs, providing a speed-up between × 16 and × 25 for classifying textures of sizes 128 × 128 and 512 × 512 px with respect to an implementation on the CPU. A comparison of classification rates obtained with other methods is included and shows the great performance of the architecture. An average classification rate of 85.2% is obtained for 167 textures of size 512 × 512 px.     

An economical tonal display for interactive graphics and image analysis data

The use of tonal displays in image analysis and interactive graphics has always dictated the use of expensive refresh memories for the display output device. This has involved the use of high speed digital drums, multiple head discs, and analog storage tubes. Recently, the introduction of very long shift registers has allowed the designer to consider their use for refresh memories. A prototype display using 1024 bit MOS static shift registers has been developed. It has been shown that a reasonable cost versus performance tradeoff can be obtained. The first efforts has resulted in a 128 × 128 × 4 bit (64k) memory; it is now in the process of being expanded to 256 × 256 × 8 bits (512k). This memory is cost competitive with digital disc memories and both cost and performance competitive with storage tube scan converters.     

景象匹配区选取方法研究

景象匹配定位是精确制导的重要技术,随着武器系统日益精确化,影响匹配制导精度的匹配区选择得到了广泛的关注。基于景象信息量、稳定性和区域唯一性对景象特征指标进行了分析研究,讨论了各特征参数对匹配性能的影响;给出了由粗到细的分层选取方案,并对特征指标进行了量化;提出了一种由粗到细的分层多尺度匹配区选取方法。实验结果表明该方法具有较大的抗鲁棒性,能够在复杂基准图上有效地选取出满足要求的景象匹配区。     

VLSI Implementation of Discrete Wavelet Transform for Lossless Compression of Medical Images

This paper presents a VLSI architecture to implement the forward and inverse two dimensional Discrete Wavelet Transform (DWT), to compress medical images for storage and retrieval. Lossless compression is usually required in the medical image field. The word length required for lossless compression makes too expensive the area cost of the architectures that appear in the literature. Thus, there is a clear need for designing a cost-effective architecture to implement the lossless compression of medical images using DWT. The data path word length has been selected to ensure the lossless accuracy criteria leading a high speed implementation with small chip area. The pyramid algorithm is reorganized and the algorithm locality is improved in order to obtain an efficient hardware implementation. The result is a pipelined architecture that supports single chip implementation in VLSI technology. The implementation employs only one multiplier and 352 memory elements to compute all scales what results in a considerable smaller chip area (45 mm²) than former implementations. The hardware design has been captured by means of the VHDL language and simulated on data taken from random images. Implemented in a 0.7 μm technology, it can compute both the forward and inverse DWT at a rate of 3.5 512×512 12 bit images/s corresponding to a clock speed of 33 MHz. This chip is the core of a PCI board that will speedup the DWT computation on desktop computers.     

Space-Time Domain Expansion Approach to VLSI and Its Application to Hierarchical Scene Matching

VLSI technology has recently received increasing attention due to its high performance and high reliability. Designing a VLSI structure systematically for a given task becomes a very important problem to many computer engineers. In this paper, we present a method to transform a recursive computation task into a VLSI structure systematically. The main advantages of this approach are its simplicity and completeness. Several examples, such as vector inner product, matrix multiplication, convolution, comparison operations in relational database and fast Fourier transformation (FFT), are given to demonstrate the transformation procedure. Finally, we apply the proposed method to hierarchical scene matching. Scene matching refers to the process of locating or matching a region of an image with a corresponding region of another view of the same image taken from a different viewing angle or at a different time. We first present a constant threshold estimation for hierarchical scene matching. The VLSI implementation of the hierarchical scene matching is then described in detail.     

A Fast Panoptic Segmentation Network for Self-Driving Scene Understanding

In recent years, a gain in popularity and significance of science understanding has been observed due to the high paced progress in computer vision techniques and technologies. The primary focus of computer vision based scene understanding is to label each and every pixel in an image as the category of the object it belongs to. So it is required to combine segmentation and detection in a single framework. Recently many successful computer vision methods has been developed to aid scene understanding for a variety of real world application. Scene understanding systems typically involves detection and segmentation of different natural and manmade things. A lot of research has been performed in recent years, mostly with a focus on things (a well-defined objects that has shape, orientations and size) with a less focus on stuff classes (amorphous regions that are unclear and lack a shape, size or other characteristics Stuff region describes many aspects of scene, like type, situation, environment of scene etc. and hence can be very helpful in scene understanding. Existing methods for scene understanding still have to cover a challenging path to cope up with the challenges of computational time, accuracy and robustness for varying level of scene complexity. A robust scene understanding method has to effectively deal with imbalanced distribution of classes, overlapping objects, fuzzy object boundaries and poorly localized objects. The proposed method presents Panoptic Segmentation on Cityscapes Dataset. Mobilenet-V2 is used as a backbone for feature extraction that is pre-trained on ImageNet. MobileNet-V2 with state-of-art encoder-decoder architecture of DeepLabV3+ with some customization and optimization is employed Atrous convolution along with Spatial Pyramid Pooling are also utilized in the proposed method to make it more accurate and robust. Very promising and encouraging results have been achieved that indicates the potential of the proposed method for robust scene understanding in a fast and reliable way.     

A novel architecture design for VLSI implementation of integer DCT in HEVC standard

This paper presents novel hardware of a unified architecture to compute the 4?×?4, 8?×?8, 16?×?16 and 32?×?32 efficient two dimensional (2-D) integer DCT using one block 1-D DCT for the HEVC standard with less complexity and material design. As HEVC large transforms suffer from the huge number of computations especially multiplications, this paper presents a proposition of a modified algorithm reducing the computational complexity. The goal is to ensure the maximum circuit reuse during the computation while keeping the same quality of encoded videos. The hardware architecture is described in VHDL language and synthesized on Altera FPGA. The hardware architecture throughput reaches a processing rate up to 52 million of pixels per second at 90 MHz frequency clock. An IP core is presented using the embedded video system on a programmable chip (SoPC) for implementation and validation of the proposed design. Finally, the proposed architecture has significant advantages in terms of hardware cost and improved performance compared to related work existing in the literature. This architecture can be used in ultra-high definition real-time TV coding (UHD) applications.

     

基于IOCP的数字城市网络用户服务器的研究

本文首先提出在数字城市网络化进程中为满足大型虚拟场景以及多用户同时访问的需求,从而首次引入了P2P网络架构,继而提出在混合式P2P架构中服务器既要维护大量的客户连接又要使性能最优的要求,从而首次引进了IOCP模型,本文的重点是通过研究分析IOCP模型的优良机制以及建立IOCP程序软件的流程,设计了P2P网络数字城市系统中基于IOCP的用户资源协调服务器原型系统,并对服务器软件的功能及相关实现技术进行了介绍,最后应用当前最流行的测试软件LoadRunner对服务器进行了大量用户同时在线登录的性能测试,测试结果正常。     

A real-time motion estimation FPGA architecture

A motion estimation architecture allowing the execution of a variety of block-matching search techniques is presented in this paper. The ability to choose the most efficient search technique with respect to speeding up the process and locating the best matching target block leads to the improvement of the quality of service and the performance of the video encoding. The proposed architecture is pipelined to efficiently support a large set of currently used block-matching algorithms including Diamond Search, 3-step, MVFAST and PMVFAST. The proposed design executes the algorithms by providing a set of instructions common for all the block-matching algorithms and a few instructions accommodating the specific actions of each technique. Moreover, the architecture supports the use of different search techniques at the block level. The results and performance measurements of the architecture have been validated on FPGA supporting maximum throughput of 30 frames/s with frame size 1,024 × 768.     

A pipelined array architecture for Euclidean distance transformation and its FPGA implementation

The Euclidean Distance Transform (EDT) is an important tool in image analysis and machine vision. This paper provides an area-efficient hardware solution to the computation of EDT on a binary image. An O(n) hardware algorithm for computing EDT of an n×n image is presented. A pipelined 2D array architecture for harware implementation is designed. The architecture has a regular structure with locally connected identical processing elements. Further, pipelining reduces hardware resources. Such an array architecture is easily scalable to handle images of different sizes and is suitable for implementation on reconfigurable devices like FPGAs. Results of FPGA-based implementation shows that the hardware can process about 6000 images of size 512×512 per second which is much higher than the video rate of 30 frames per second.     

景象匹配算法研究进展与展望

景象匹配是精确制尊武器精确定位目标的重要方法,景象匹配算法决定了精确制导武器系统的作战性能。论文介绍了景象匹配算法实现的关键要素,详细综述了具有代表性的基于区域、基于特征、基于变换域以及基于模型的四类匹配算法的不同原理、适用性及其改进算法,探讨了景象匹配算法中有待进一步研究的问题和未来发展的方向,为未来的景象匹配制导研究工作提供技术参考和依据。景象匹配制导技术正朝着更稳定可靠、更智能、更快捷、更精确的方向发展,必将推动精确制导武器装备实现现代化和自动化。     

基于仿射不变约束与快速EKF滤波的航拍图像稳像

考虑到航拍机载成像平台抖动严重、视频稳像匹配环节精度不一致的特点以及航拍图像稳像技术快速、准确的要求,提出了一种结合仿射不变约束与快速扩展卡尔曼(Extend Kalman Filter,EKF)滤波的图像稳像算法。该算法首先以视频参考帧中的角点量作为特征点,通过Harris检测器选择出稳定角点;然后对待配准点构建Delaunay三角网进行初始匹配,提出利用仿射不变约束方法筛选出精确匹配点;最后利用快速EKF运动滤波方法实时估计和修正噪声的统计特性,从而解决摄像机扫描运动中存在的抖动问题。在对大量分辨率为640×480pixel的航拍图像的仿真实验中,可通过仿射不变约束实现精确的模型估计,采用的快速运动补偿方法在补偿过程中耗时为5.054ms,比传统的运动补偿方法节约了69.5%的时间。实验结果表明,该算法能够实时稳定航拍视频帧间的抖动现象,并能有效跟随场景的真实扫描。     

一种基于上升缘与下降缘的语音分割方法

听觉场景分析（Auditory Scene Analysis,ASA）系统能将一个场景分解为与不同声源对应的语音流。分割是ASA的主要步骤,借助分割可将一个听觉场景分解成多个片断。实现基于上升缘和下降缘分析的语音分割系统需检测上升缘与下降缘,通过匹配对应的上升缘与下降缘的波前来生成语音片断,将这些片断重构成语音流。     

基于几何信息先验分布的似物性推荐方法

似物性推荐是计算机视觉研究中的热门问题,其目的是用尽可能少的推荐窗口涵盖可能的兴趣目标,以显著地提升目标检测任务的计算效率。从组合几何学角度对该问题进行了分析,一种“完全窗口覆盖”的方法被提出,用少量窗口即可覆盖所有可能目标区域。对于尺寸不大于512×512的图像,约19000个窗口即可覆盖所有尺寸不小于16×16的目标区域。基于目标矩形的位置、尺寸的先验分布,可以使用贪心策略进一步地缩减窗口数量。为了适应不同图像集在小概率样本上的差异,提出了一种融合了贪心和随机方法的混合机制,其所需的计算量非常小,而且具有很好的泛化能力。在VOC2007测试集上,该混合机制可以在1000个推荐窗口上取得94.52%的召回率,其中在前10个热点推荐窗口上的召回率比其他方法平均高出13.99%~40.29%。     

An ART1 microchip and its use in multi-ART1 systems

Recently, a real-time clustering microchip neural engine based on the ART1 architecture has been reported. However, that chip rendered an extremely high silicon area consumption of 1 cm(2), and consequently an extremely low yield of 6%. Redundant circuit techniques can be introduced to improve yield performance at the cost of further increasing chip size. In this paper we present an improved ART1 chip prototype based on a different approach to implement the most area consuming circuit elements of the first prototype: an array of several thousand current sources which have to match within a precision of around 1%. Such achievement was possible after a careful transistor mismatch characterization of the fabrication process (ES2-1.0 mum CMOS). A new prototype chip has been fabricated which can cluster 50-b input patterns into up to ten categories. The chip has 15 times less area, shows a yield performance of 98%, and presents the same precision and speed than the previous prototype. Due to its higher robustness multichip systems are easily assembled. As a demonstration we show results of a two-chip ART1 system, and of an ARTMAP system made of two ART1 chips and an extra interfacing chip.     

存储有效的多模式匹配算法和体系结构

多模式匹配是基于内容检测的网络安全系统的重要功能,同时,它在很多领域具有广泛的应用.实际应用中,高速且性能稳定的大规模模式匹配方法需求迫切,尤其是能够在线实时处理网络包的匹配体系结构.介绍了一种存储有效的高速大规模模式匹配算法及相关体系结构.研究从算法所基于的理论入手,提出了缓存状态机模型,并结合状态机中转换规则分类,提出了交叉转换规则动态生成的匹配算法ACC(Aho-Corasick-CDFA).该算法通过动态生成转换规则降低了生成状态机的规模,适用于大规模模式集.进一步提出了基于该算法的体系结构设计.采用网络安全系统中真实模式集进行的实验结果表明,该算法相比其他状态机类模式匹配算法,可以进一步减少80%~95%的状态机规模,存储空间降低40.7%,存储效率提高近2 倍,算法单硬件结构实现可以达到11Gbps 的匹配速度.     

Image compression sensor based on column parallel architecture

We propose a novel image sensor which has compression function on its sensor plane. The image compression sensor can significantly reduce the amount of pixel data output from the sensor. The proposed sensor is intended to overcome the communication bottle neck for high pixel rate imaging such as high frame rate imaging and high resolution imaging.

The compression algorithm is based on conditional replenishment. It detects motion and encodes only the pixels in moving areas. We have been investigating pixel parallel and column parallel architectures of the image compression sensor. In this paper, we present the column parallel architecture of the proposed sensor. In this architecture, fill factor and power dissipation are comparable to conventional MOS sensors in spite of integration of the processing circuits. We have fabricated a prototype chip based on the column parallel architecture. We describe the circuit and layout design and the results of some experiments using the prototype.     

Intelligent indexing of crime scene photographs

The Scene of Crime Information System's automatic image-indexing prototype goes beyond extracting keywords and syntactic relations from captions. The semantic information it gathers gives investigators an intuitive, accurate way to search a database of cases for specific photographic evidence. Intelligent, automatic indexing and retrieval of crime scene photographs is one of the main functions of SOCIS, our research prototype developed within the Scene of Crime Information System project. The prototype, now in its final development and evaluation phase, applies advanced natural language processing techniques to text-based image indexing and retrieval to tackle crime investigation needs effectively and efficiently.