高效太阳电池硅衬底特性对原子层沉积Al2O3薄膜钝化性能的影响

Atom layer deposition （ALD）-Al2O3 thin films are considered effective passivation layers for p-type silicon surfaces. A lower surface recombination rate was obtained through optimizing the deposition parameters. The effects of some of the basic substrate characteristics including material type, bulk resistivity and surface morphology on the passivation performance of ALD-Al2O3 are evaluated in this paper. Surface recombination velocities of 7.8 cm/s and 6.5 cm/s were obtained for p-type and n-type wafers without emitters, respectively. Substrates with bulk resistivity ranging from 1.5 to 4 Ω · cm were all great for such passivation films, and a higher implied Voc of 660 mV on the 3 Ω · cm substrate was achieved. A minority carrier lifetime （MCL） of nearly 10 μs higher was obtained for cells with a polished back surface compared to those with a textured surface, which indicates the necessity of the polishing process for high-efficiency solar cells. For n-type semi-finished solar cells, a lower effective front surface recombination velocity of 31.8 cm/s was acquired, implying the great potential of （ALD）-Al2O3 thin films for high-efficiency n-type solar cells.     

Research on the properties of ZnO1-xSx thin films modified by sulfur doping for CIGS solar cells

ZnO1-xSx thin films modified by sulfur doping were prepared on glass substrates by chemical bath deposition (CBD) for studying the effect of thiourea concentration on the thin film properties. The obtained ZnO1-xSx thin films were characterized by scanning electron microscopy (SEM), which shows the surfaces of ZnO1-xSx thin films deposited under the thiourea concentration of 0.14 M are more compact. X-ray diffraction (XRD) measurement shows that the ZnO1-xSx thin films with hexagonal crystal structure had strong diffraction peaks and better crystallinity. The optical transmittance of the ZnO1-xSx thin films with 0.14 M thiourea concentration is above 80% in the wavelength range of 300—900 nm. According to the measurement results from spectrophotometer, the ZnO1-xSx band gap energy value Eg varies nonlinearly with different S/(S+O) ratio x, and increases with the increase of x. There is a band gap value of 2.97 eV in the ZnO1-xSx thin films deposited under 0.14 M thiourea concentration. Therefore, the thin films have better structural, optical and electric properties, and are more suitable for the buffer layers of copper indium gallium selenide (CIGS) thin film solar cells.     

化学抛光处理和低温退火对硅异质结太阳电池性能的影响

Amorphous/crystalline silicon heterostructure solar cells have been fabricated by hot wire chemical vapor deposition （HWCVD） on textured p-type substrates. The influence of chemical polish （CP） etching and the post annealing process on the solar cell performance have been studied. The CP treatment leads to a reduction of stress in the i-layer by the slight rounding of the pyramid peaks, therefore improving the deposition coverage and the contact by each layer, which is beneficial for the performance of the solar cells. An optimized etching time of 10-15 s has been obtained. A post annealing process leads to a considerably improved open voltage （Voc）, filled factor （FF）, and conversion efficiency （η） by restructuring the deposited film and reducing the series resistance. An efficiency of 15.14% is achieved that represents the highest result reported in China for an amorphous/crystalline heterostructure solar cells based on the textured p-type substrates.     

Growth Front Evolution of GaN Thin Films on Sapphire Substrate During HVPE

The growth front evolution of GaN thin films deposited on sapphire substrate by hydride vapor phase epitaxity has been studied with atomic force microscope. The evolution of the surface morphology presents four features of stage with the growth process. In initial growth stage, the surface is granular, and the typical grain diameter is about 250nm for t =0.1min. 3D growth plays a key role before the films come up to full coalescence, which causes a rough surface. After 0.1min the growth dimension decreases with the increase of lateral over growth, the surface roughness obviously decreases. From 0.4min to 3min, the growth front roughness increases gradually, and the evolution of the surface roughness exhibits the characteristics of self-affined fractal. Beyond 3min, the root-mean-square decreases gradually, which means the deposition behavior from hyper-2D growth gradually turns into layer growth mode with the increase of growth time.     

Optimization of n/i and i/p buffer layers in n-i-p hydrogenated microcrystalline silicon solar cells

Hydrogenated microcrystalline silicon （μc-Si：H） intrinsic films and solar cells with n-i-p configuration were prepared by plasma enhanced chemical vapor deposition （PECVD）. The influence of n/i and i/p buffer layers on the μc-Si：H cell performance was studied in detail. The experimental results demonstrated that the efficiency is much improved when there is a higher crystallinity at n/i interface and an optimized a-Si：H buffer layer at i/p interface. By combining the above methods, the performance of μc-Si：H single-junction and a-Si：H/μc-Si：H tandem solar cells has been significantly improved.     

图形衬底对InGaN/GaN多量子阱太阳能电池性能的提升

In this paper, the enhanced performance of InGaN/GaN multiple quantum well solar cells grown on patterned sapphire substrates （PSS） was demonstrated. The short-circuit current （Jsc） density of the solar cell grown on PSS showed an improvement of 60%, compared to that of solar cells grown on conventional sapphire substrate. The improved performance is primarily due to the reduction of edge dislocations and the increased light absorption path by the scattering from the textured surface of the PSS. It shows that the patterned sapphire technology can effectively alleviate the problem of high-density dislocations and low Jsc caused by thinner absorption layers of the InGaN based solar cell, and it is promising to improve the efficiency of the solar cell.     

High haze textured surface B-doped ZnO-TCO films on wet-chemically etched glass substrates for thin film solar cells

Textured glass substrates with crater-like feature sizes of ~5-30 μm were obtained using the chemical etching method through adjusting the treatment round (R). Pyramid-like boron-doped zinc oxide (ZnO:B) films with feature sizes of ~300-800 nm were deposited on the etched glass substrates by the metal organic chemical deposition (MOCVD) technique using water, diethylzinc and 1%-hydrogen-diluted diborane. The ZnO:B films on the etched glass with micro/nano double textures presented a much stronger light-scattering capability than the conventional ZnO:B on the flat glass and their electrical properties changed little. Typical etched glass-3R/ZnO:B exhibited a high root mean square (RMS) roughness of ~160 nm. The haze values at the wavelengths of 550 nm and 850 nm for etched glass-3R/ZnO:B sample were 61% and 42%, respectively. Finally, the optimized etched glass/ZnO:B was applied in the silicon (Si) based thin film solar cells. The high haze etched glass/ZnO:B substrates have potential merits for thin film solar cells.     

硼掺杂硅薄膜及其在叠层电池隧道结中的应用

Boron-doped hydrogenated silicon films with different gaseous doping ratios（B2H6/SiH4） were deposited in a plasma-enhanced chemical vapor deposition（PECVD） system.The microstructure of the films was investigated by atomic force microscopy（AFM） and Raman scattering spectroscopy.The electrical properties of the films were characterized by their room temperature electrical conductivity（σ） and the activation energy（Ea）.The results show that with an increasing gaseous doping ratio,the silicon films transfer from a microcrystalline to an amorphous phase,and corresponding changes in the electrical properties were observed.The thin boron-doped silicon layers were fabricated as recombination layers in tunnel junctions.The measurements of the I-V characteristics and the transparency spectra of the junctions indicate that the best gaseous doping ratio of the recombination layer is 0.04,and the film deposited under that condition is amorphous silicon with a small amount of crystallites embedded in it.The junction with such a recombination layer has a small resistance,a nearly ohmic contact,and a negligible optical absorption.     

Optimization of Al_2O_3/SiN_x stacked antireflection structures for N-type surface-passivated crystalline silicon solar cells

In the case of N-type solar cells,the anti-reflection property,as one of the important factors to further improve the energy-conversion efficiency,has been optimized using a stacked Al₂O₃/SiN_x layer.The effect of SiN_x layer thickness on the surface reflection property was systematically studied in terms of both experimental and theoretical measurement.In the stacked Al₂O₃/SiN_x layers,results demonstrated that the surface reflection property can be effectively optimized by adding a SiN_x layer,leading to the improvement in the final photovoltaic characteristic of the N-type solar cells.     

掺氮ZnO薄膜的光电特性及其薄膜晶体管研究

Using NH3 as nitrogen source gas, N-doped ZnO （ZnO：N） thin films in c-axis orientation were deposited on glass substrates by radio frequency magnetron sputtering at room temperature. The ZnO：N thin films display significant increase of resistivity and decrease of photoluminescence intensity. As-grown ZnO：N material was used as active channel layer and Si3N4 was used as gate insulator to fabricate thin-film transistor. The fabricated devices on glasses demonstrate typical field effect transistor characteristics.     

Ranking Potential Reply-Providers in Community Question Answering System

Community Question Answering （CQA） websites have greatly facilitated users＇ lives, with an increasing number of people seeking help and exchanging ideas on the Internet. This newlymerged community features two characteristics： social relations and an ask-reply mechanism. As users＇ behaviours and social statuses play a more important role in CQA services than traditional answer retrieving websites, researchers＇ concerns have shifted from the need to passively find existing answers to actively seeking potential reply providers that may give answers in the near future. We analyse datasets derived from an online CQA system named ＂Quora＂, and observed that compared with traditional question answering services, users tend to contribute replies rather than questions for help in the CQA system. Inspired by the findings, we seek ways to evaluate the users＇ ability to offer prompt and reliable help, taking into account activity, authority and social reputation char- acteristics. We propose a hybrid method that is based on a Question-User network and social network using optimised PageRank algorithm. Experimental results show the efficiency of the proposed method for ranking potential answer-providers.     

一个全差分可编程的多通道神经信号记录芯片

A multi-channel,fully differential programmable chip for neural recording application is presented.The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain,eight 4thorder Bessel switch capacitor filters,an 8-to-1 analog time-division multiplexer,a fully differential successive approximation register analog-to-digital converter(SAR ADC),and a serial peripheral interface for communication.The neural recording amplifier presents a programmable gain from 53 dB to 68 dB,a tunable low cut-off frequency from 0.1 Hz to 300 Hz,and 3.77 μVrms input-referred noise over a 5 kHz bandwidth.The SAR ADC digitizes signals at maximum sampling rate of 20 kS/s per channel and achieves an ENOB of 7.4.The integrated circuit is designed and fabricated in 0.18-μm CMOS mix-signal process.We successfully performed a multi-channel in-vivo recording experiment from a rat cortex using the neural recording chip.     

A power-efficient 12-bit analog-to-digital converter with a novel constant-resistance CMOS input sampling switch

Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter（ADC）implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two op- amp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode （RFC） amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC＇s performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range （SFDR） of 75.7 dB and a signal-to-noise-plus-distortion ratio （SNDR） of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity （DNL） and integral nonlinearity （INL） are -0.43 to ＋0.48 LSB and -1.62 to ＋ 1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure- of-merit （FOM） of 0.63 pJ per conversion-step.     

Low power high gain gain-controlled LNA and mixer for GNSS receivers Wei Binbin(魏斌斌)1, Jiang Jinguang(江金光)1,2,3*

A low power high gain gain-controlled LNA ＋ mixer for GNSS receivers is reported. The high gain LNA is realized with a current source load. Its gain-controlled ability is achieved using a programmable bias circuit. Taking advantage of the high gain LNA, a high noise figure passive mixer is adopted. With the passive mixer, low power consumption and high voltage gain of the LNA ＋ mixer are achieved. To fully investigate the performance of this circuit, comparisons between a conventional LNA ＋ mixer, a previous low power LNA ＋ mixer, and the proposed LNA ＋ mixer are presented. The circuit is implemented in 0.18 #m mixed-signal CMOS technology. A 3.8 dB noise figure, an overall 45 dB converge gain and a 10 dB controlled gain range of the two stages are measured. The chip occupies 0.24 mm2 and consumes 2 mA current under 1.8 V supply.     

一种应用于GPS接收机的高线性度SiGe HBT低噪声放大器

A high linearity 1.575 GHz SiGe：HBT low noise amplifier （LNA） for global positioning system applications is described. The bipolar cascoded with an MOSFET LNA was fabricated in a commercial 0.18 μm SiGe BiCMOS process, A resistor bias feed circuit with a feedback resistor was designed for the LNA input transistor to improve its intermodulation and compression performance. The packaged chip tested on board has displayed a noise figure of 1. I 1 dB, a power gain of 18 dB, an output 1 dB compression point of ＋7.8 dBm and an input third-order intercept point of ＋1.8 dBm. The chip occupies a 500 × 560μm^2 area and consumes 3.6 mA from a 2.85 V power supply.     

一种应用于GNSS接收机的低噪声和低杂散频率综合器

A low phase noise and low spur phase locked loop （PLL） frequency synthesizer for use in global navigation satellite system （GNSS） receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector （PFD） produces four control signals, which can reach the charge pump （CP） simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc.     

用于U波段移动数字电视的宽带大动态范围高线性度射频前端

A wideband large dynamic range and high linearity U-band RF front-end for mobile DTV is introduced,and includes a noise-cancelling low-noise amplifier(LNA),an RF programmable gain amplifier(RFPGA) and a current communicating passive mixer.The noise/distortion cancelling structure and RC post-distortion compensation are employed to improve the linearity of the LNA.An RFPGA with five stages provides large dynamic range and fine gain resolution.A simple resistor voltage network in the passive mixer decreases the gate bias voltage of the mixing transistor,and optimum linearity and symmetrical mixing is obtained at the same time.The RF front-end is implemented in a 0.25 μm CMOS process.Tests show that it achieves an ⅡP3(third-order intercept point) of –17 dBm,a conversion gain of 39 dB,and a noise figure of 5.8 dB.The RFPGA achieves a dynamic range of –36.2 to 23.5 dB with a resolution of 0.32 dB.     

一种电流复用共栅低噪声放大器的低功耗433/915-MHz射频前端的设计

This paper presents a wideband RF front-end with novel current-reuse wide band low noise amplifier(LNA),current-reuse V –I converter,active double balanced mixer and transimpedance amplifier for short range device(SRD) applications.With the proposed current-reuse LNA,the DC consumption of the front-end reduces considerably while maintaining sufficient performance needed by SRD devices.The RF front-end was fabricated in 0.18 μm RFCMOS process and occupies a silicon area of just 0.11 mm2.Operating in 433 MHz band,the measurement results show the RF front-end achieves a conversion gain of 29.7 dB,a double side band noise figure of 9.7 dB,an input referenced third intercept point of –24.9 dBm with only 1.44 mA power consumption from 1.8 V supply.Compared to other reported front-ends,it has an advantage in power consumption.     

用于无采保流水线ADC的高速低功耗低失调动态比较器

A novel fully differential high speed high resolution low offset CMOS dynamic comparator has been implemented in the SMIC 0.18 μm process used for a sample-and-hold amplifier （SHA）-less pipelined analog-to-digital converters （ADC）. Based on the analysis and optimization between delay time and offset, an enhanced reset architecture with transmission gate was introduced to speed up the comparison and reset procedure. Four inputs with two cross coupled differential pairs, reconstituted bias circuit for tail current transistor and common centroid layouts make the comparator more robust against mismatch and process variations. The simulation results demonstrate that the proposed design achieves 1 mV sensitivity at 2.2 GHz sampling rate with a power consumption of 510 μW, while the mean offset voltage is equal to 10.244 mV.