用于IEEE802．11b／g WLAN直接下变频接收机的射频前端设计

介绍了一种应用于IEEE802．11b／g无线局域网接收机射频前端的设计。基于直接下变频的系统架构。接收机集成了低噪声放大器、I／Q下变频器、去直流偏移滤波器、基带放大器和信道选择滤波器。电路采用TSMC0．18μm CMOS工艺设计,工作在2．4GHz ISM（工业、科学和医疗）频段,实现的低噪声放大器噪声系数为0．84dB,增益为16dB,S11低于-15dB,功耗为13mW;I／Q下变频器电压增益为2dB,输入1dB压缩点为-1 dBm,噪声系数为13dB,功耗低于10mw。整个接收机射频前端仿真得到的噪声系数为3．5dB,IIP3为-8dBm,IP2大于30dBm,电压增益为31dB,功耗为32mW。     

A WiMedia/MBOA-Compliant CMOS RF Transceiver for UWB

A WiMedia/MBOA compliant RF transceiver for ultra-wideband data communication in the 3-5-GHz band is presented. The transceiver includes receiver, transmitter and synthesizer is completely integrated in 0.13-mum standard CMOS technology. The receiver uses a feedback-based low-noise amplifier (LNA) to obtain an RF gain of 4 to 37 dB and an overall measured noise figure of 3.6 to 4.1 dB over the 3-5-GHz band of interest. The transmitter supports an error vector magnitude (EVM) of -28 dB up to -4 dBm output power and meets the FCC and WiMedia mask specifications. The power consumption from a single supply voltage of 1.5 V is 237 mW for the receiver and 284 mW for the transmitter, both including the synthesizer     

A fully integrated 900-MHz CMOS wireless receiver with on-chip RF and IF filters and 79-dB image rejection

A monolithic 900-MHz CMOS wireless receiver with on-chip RF and IF filters and a fully integrated fractional-N synthesizer is presented. Implemented in a standard 0.5-/spl mu/m CMOS process and without any off-chip component, the complete receiver has a measured image rejection of 79 dB, a sensitivity of -90 dBm, an IIP3 of -24 dBm, and a noise figure of 22 dB with a power of 227 mW and a chip area of 5.7 mm/sup 2/. The synthesizer achieves a phase noise of -118 dBc/Hz at 600 kHz offset and a settling time of less than 150 /spl mu/s.     

Monolithic InGaP-GaAs HBT receiver front-end with 6 mW DC power consumption for 5 GHz band WLAN applications

A very low power consumption (6 mW) 5 GHz band receiver front-end using InGaP-GaAs HBT technology is reported. The receiver front-end is composed of a cascode low noise amplifier followed by a double-balanced mixer with the RF transconductor stage placed above the Gilbert quad for direct-coupled connection. The RF band of this receiver front-end is set to be 5.2 GHz, being downconverted to 1 GHz IF frequency. Input-return-loss (S/sub 11/) in RF port smaller than -12 dB and excellent power-conversion-gain of 35.4 dB are achieved. Input 1 dB compression point (P/sub 1dB/) and input third-order intercept point (IIP3) of -24 and -3 dBm, respectively, are also achieved.     

A fully integrated UHF RFID reader SoC for handheld applications in the 0.18 μm CMOS process

A low cost fully integrated single-chip UHF radio frequency identification(RFID) reader SoC for short distance handheld applications is presented.The SoC integrates all building blocks—including an RF transceiver,a PLL frequency synthesizer,a digital baseband and an MCU—in a 0.18μm CMOS process.A high-linearity RX frontend is designed to handle the large self-interferer.A class-E power amplifier with high power efficiency is also integrated to fulfill the function of a UHF passive RFID reader.The measure...     

A 2.4-GHz ISM-Band Sliding-IF Receiver With a 0.5-V Supply

We report an ultra-low-voltage RF receiver for applications in the 2.4 GHz band, designed in a 90 nm CMOS technology. The sliding-IF receiver prototype includes an LNA, an image-reject LC filter with single-ended to differential conversion, an RF mixer, an LC IF filter, a quadrature IF mixer, RF and IF LO buffers, and an I/Q baseband section with a VGA and a low-pass channel-select filter in each path, all integrated on-chip. It has a programmable overall gain of 30 dB, noise figure of 18 dB, out-of-channel IIP3 of -22 dBm. The 3.4 mm² chip consumes 8.5 mW from a 0.5 V supply.     

A 60-GHz Phased Array Receiver Front-End in 0.13-$mu {hbox{m}}$ CMOS Technology

This paper presents a fully integrated dual-antenna phased-array RF front-end receiver architecture for 60-GHz broadband wireless applications. It contains two differential receiver chains, each receiver path consists of an on-chip balun, ag_m-boosted current-reuse low-noise amplifier (LNA), a sub-harmonic dual-gate down-conversion mixer, an IF mixer, and a baseband gain stage. An active all-pass filter is employed to adjust the phase shift of each LO signal. Associated with the proposed dual conversion topology, the phase shift of the LO signal can be scaled to one-third. Differential circuitry is adopted to achieve good common-mode rejection. The g_m-boosted current-reuse differential LNA mitigates the noise, gain, robustness, stability, and integration challenges. The sub-harmonic dual-gate down-conversion mixer prevents the third harmonic issue in LO as well. Realized in a 0.13-mum 1P8M RF CMOS technology, the chip occupies an active area of 1.1 times 1.2 mm². The measured conversion gain and input P1 dB of the single receiver path are 30 dB and -27 dBm , respectively. The measured noise figure at 100 MHz baseband output is around 10 dB. The measured phased array in the receiver achieves a total gain of 34.5 dB and theoretically improves the receiver SNR by 4.5 dB. The proposed 60 GHz receiver dissipates 44 mW from a 1.2 V supply voltage. The whole two-channel receiver, including the vector modulator circuits for built-in testing, consumes 93 mW from a 1.2 V supply voltage.     

A 0.6-V 1.6-mW transformer-based 2.5-GHz downconversion mixer with +5.4-dB gain and -2.8-dBm IIP3 in 0.13-/spl mu/m CMOS

On-chip transformers are best suited to lower the supply voltage in RF integrated circuits. A design method to achieve a high current gain with an on-chip transformer operating in resonance is presented. The proposed method will be proven analytically and has been applied to a downconversion mixer. Thereby part of the overall gain of the mixer has been shifted from the RF input stage to the transformer. Thus, the power consumption has been reduced and, in spite of the low supply voltage, moderate linearity has been achieved. Although the transformer has a bandpass behavior, a 3-dB bandwidth of 900 MHz at a center frequency of 2.5 GHz has been achieved. The downconversion mixer has been realized in 0.13-mum CMOS. It consumes 1.6 mW from a 0.6-V supply. A gain of +5.4 dB, a third-order intercept point of -2.8 dBm, an input 1-dB compression point of -9.2 dBm, and a single-sideband noise figure of 14.8 dB have been achieved     

T形栅In0.52Al0.48As/In0.6Ga0.4As MHEMTs功率器件

利用电子束光刻技术制备了200nm栅长GaAs基T型栅InAlAs/lnGaAs MHEMT器件.该GaAs基MHEMT器件具有优越的直流、高频和功率性能,跨导、饱和漏电流密度、阈值电压、电流增益截止频率和最大振荡频率分别达到510mS/mm,605mA/mm,-1.8V,138GHz和78GHz.在8GHz下,输人功率为-0.88(2.11)dBm时,输出功率、增益、PAE、输出功率密度分别为14.05(13.79)dBm,14.9(11.68)dB,67.74(75.1)%,254(239)mW/mm,为进一步研究高性能GaAs基MHEMT功率器件奠定了基础.     

A low-voltage 5.1-5.8-GHz image-reject downconverter RF IC

This paper describes a single-chip implementation of a low-voltage image-reject downconverter for a 5.1-5.8-GHz radio receiver. It consists of a low-noise preamplifier (LNA) that is simultaneously noise and power matched to the RF source, and dual doubly balanced mixers coupled to the LNA by a monolithic trifilar transformer. The image-reject architecture eliminates an RF filter, thereby simplifying packaging requirements. The downconverter realizes over 36 dB of image rejection while dissipating 24 mW from a 0.9 V supply, or 18.5 mW at 1.8 V. Conversion gain is 14 dB, IIP3=-5.5 dBm, and noise figure is 6.8 dB (single sideband 50 Ω) when operating from a 0.9 V supply     

A high sensitivity and wide dynamic range zero-IF RF receiver for cognitive radio application

This paper presents an RF receiver of zero-Intermediate Frequency (IF) architecture for Cognitive Radio (CR) communication systems. Zero-IF architecture reduce the image reject filter and IF filter, so it is excellent in low cost, compact volume, and low power dissipation. The receiver employs three digital attenuator and a high gain, high linearity low noise amplifier to achieve wide dynamic range of 70 dB and high receiving sensitivity of −81 dBm. A fully balanced I/Q demodulator and a differential Local Oscillator (LO) chips are used to minimize the negative effects caused by second-order distortion and LO leakage. In order to select an 8 MHz-channel from 14 continuous ones located in UHF band (694–806 MHz) accurately, approach of channel selectivity circuits is proposed. The RF receiver has been designed, fabricated, and test. The measured result shows that the noise figure is 3.4 dB, and the error vector magnitude is 7.5% when the input power is −81 dBm.     

Low phase noise IP VCO for multistandard communication using a 0.35-/spl mu/m BiCMOS SiGe technology

In this letter, we report that a commonly used 0.35-/spl mu/m, 60-GHz-F/sub MAX/ BiCMOS SiGe monolithic microwave integrated circuit (MMIC) technology is able to provide very low phase noise signal generation in the X-band frequency range. This statement has been demonstrated using a differential LC voltage-controlled oscillator (VCO) in which varactors are realized with metal-oxide semiconductor (MOS) transistors and inductors with a patterned ground shield technology. This VCO features an output power signal in the range of -5 dBm and exhibits a phase noise of -96 dBc/Hz at a frequency offset of 100kHz from carrier and -120 dBc/Hz at a frequency offset of 1 MHz. The VCO features a tuning range of 430 MHz or 4.3% of its operating frequency. Its power consumption is in the range of 70 mW (200 mW with buffers circuits) for a chip size of 800/spl times/1000 /spl mu/m/sup 2/ (including RF probe pads).     

A 40 GHz single-ended down-conversion mixer in 0.13 /spl mu/m SiGeC BiCMOS HBT

This work presents a single-ended active mixer realized with a 0.13 /spl mu/m BiCMOS SiGeC heterojunction bipolar transistor (HBT) technology. This mixer is designed to be integrated in a superheterodyne receiver for 40 GHz wireless communication systems. Local oscillator (LO) and RF signals are directly applied to the base of the HBT through two coupled lines. The mixer provides a down-conversion from 42 GHz to 2 GHz. The mixer exhibits a power conversion gain better than 2.4 dB and a measured double-sideband noise figure less than 8.3 dB for P/sub LO/=3 dBm (power of the local oscillator) under a global power consumption lower than 9.5 mW. This architecture exhibits good linearity performance with a measured IP/sub 1dB/ of about -7 dBm and an IIP3 of +4 dBm. The linear dynamic range for a 2 GHz system bandwidth is approximately 65 dB for P/sub LO/=+2 dBm and T/sub 0/=290 K. The third order spurious free dynamic range is calculated to be better than 52 dB.     

Low-power/low-voltage RF microsystems for wireless sensors networks

This paper presents radio-frequency (RF) microsystems (MSTs) composed by low-power devices for use in wireless sensors networks (WSNs). The RF CMOS transceiver is the main electronic system and its power consumption is a critical issue. Two RF CMOS transceivers with low-power and low-voltage supply were fabricated to operate in the 2.4 and 5.7 GHz ISM bands. The measurements made in the RF CMOS transceiver at 2.4 GHz, which showed a sensitivity of −60 dBm with a power consumption of 6.3 mW from 1.8 V supply. The measurements also showed that the transmitter delivers an output power of 0 dBm with a power consumption of 11.2 mW. The RF CMOS transceiver at 5.7 GHz has a total power consumption of 23 mW. The target application of these RF CMOS transceivers is for MSTs integration and for use as low-power nodes in WSNs to work during large periods of time without human operation, management and maintenance. These RF CMOS transceivers are also suitable for integration in thermoelectric energy scavenging MSTs.     

低功耗人体通信射频收发器的设计

Human body communication is proposed as a promising body proximal communication technology for body sensor networks. To achieve low power and small volume in the sensor nodes, a Radio Frequency (RF) application-specific integrated circuit transceiver for Human Body Communication (HBC) is presented and the characteristics of HBC are investigated. A high data rate On-Off Keying (OOK)/Frequency-Shift Keying (FSK) modulation protocol and an OOK/FSK demodulator circuit are introduced in this paper, with a data-rate-to-carrier-frequency ratio up to 70% . A low noise amplifier is proposed to handle the dynamic range problem and improve the sensitivity of the receiver path. In addition, a low power automatic-gain-control system is realized using a novel architecture, thereby rendering the peak detector circuit and loop filter unnecessary. Finally, the complete chip is fabricated. Simulation results suggest receiver sensitivity to be -75 dBm. The transceiver shows an overall power consumption of 3.2 mW when data rate is 5 Mbps, delivering a P1 dBoutput power of -30 dBm.     

3 V, 28 mW Si-bipolar front-end IC for 900 MHz homodyne wirelessreceivers

A 900 MHz homodyne receiver front-end bipolar chip is presented. The circuit consists of a low-noise amplifier and two double-balanced mixers for in-phase and quadrature channels. The power supply voltage is 3 V and power dissipation is 28 mW. The measured performance includes 33.5 dB voltage gain, a 3.1 dB noise figure, -13 dBm input referred IP3, -95 dB LO leakage into the RF port on wafer probing, and less than 0.1 dB I/Q magnitude imbalance     

A complete single-chip GPS receiver with 1.6-V 24-mW radio in 0.18-/spl mu/m CMOS

We have developed a complete single-chip GPS receiver using 0.18-/spl mu/m CMOS to meet several important requirements, such as small size, low power, low cost, and high sensitivity for mobile GPS applications. This is the first case in which a radio has been successfully combined with a baseband processor, such as SoC, in a GPS receiver. The GPS chip, with a total size of 6.3 mm /spl times/ 6.3 mm, contains a 2.3 mm /spl times/ 2.0 mm radio part, including RF front end, phase-locked loops, IF functions, and 500 K gates of baseband logic, including mask ROM, SRAM, and dual port SRAM . It is fabricated using 0.18-/spl mu/m CMOS technology with a MIM capacitor and operates from a 1.6-2.0-V power supply. Experimental results show a very low power consumption of, typically, 57 mW for a fully functional chip including baseband, and a high sensitivity of -152dBm. Through countermeasures against substrate coupling noise from the digital part, the high sensitivity was successfully achieved without any external low-noise amplifier.     

A low power 3-5 GHz CMOS UWB receiver front-end

A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below-8.5 dB across the 3.1-4.7 GHz frequency range, max-imum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of-11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm2.     

A high-IP3 RF receiver chip set for mobile radio base stations upto 2 GHz

We present a monolithically integrated high third-order intercept point (IP3) radio frequency (RF) receiver chip set for mobile radio base stations up to 2 GHz, in a 25-GHz f_T Si bipolar production technology. The chip set consists of a RF preamplifier, active mixer circuits, and an intermediate frequency (IF) limiter. The preamplifier gain is 12 dB, the noise figure is 5.5 dB at 900 MHz, and the output (OIP3) is up to +24 dBm depending on supply voltage. The two different mixers provide a conversion gain of 1.5 dB up to 3 dB, an OIP3 in the range of +21 dBm up to +29 dBm, and a minimal single sideband (SSB) noise figure of 13 dB. The IF limiter shows an excellent limiting characteristic at 10 dBm output power and has a high bandwidth of more than 1 GHz     

An interference-robust receiver for ultra-wideband radio in SiGe BiCMOS technology

A 3.1-4.8 GHz ultra-wideband (UWB) receiver front-end for high data rate, short-range communication is presented. The receiver, based on the Multi Band OFDM Alliance (MBOA) standard proposal, consists of a zero-IF receive chain and an ultra-fast frequency-hopping synthesizer. The combination of high-linearity RF circuits, aggressive baseband filtering and low local oscillator spurs from the synthesizer results in an interference-robust receiver, having the ability to co-exist with systems operating in the 2.4-GHz and 5-GHz ISM bands. The packaged device shows an overall noise figure of 4.5 dB and has a measured input IP3 of -6 dBm and input IP2 of +25 dBm. Spurious tones generated by the synthesizer are below -45 dBc and -50 dBc in the 2.4-GHz and 5-GHz ISM bands, respectively. The hopping speed is well below the required 9.5 ns. The complete receive chain has been realized in a 0.25 /spl mu/m BiCMOS technology and draws 78mA from a 2.5-V supply.