A novel model of the gate current in heterojunction FETs

The authors present a model of the gate current in heterojunction FETs that takes into account two-dimensional electron gas effects at the heterojunction interface. The gate current results from tunnel and thermionic contributions. This model takes into account a number of technological parameters such as heterojunction barrier height, threshold voltage, gate length, and temperature. It has been tested against experimental measurements of gate current in AlGaAs/GaAs MISFETs at various temperatures. The agreement has been found quite satisfactory in a large range of temperatures     

Explicit model for the gate tunneling current in double-gate MOSFETs

In this paper, we present an explicit compact quantum model for the gate tunneling current in double-gate metal–oxide–semiconductor field-effect transistors (DG-MOSFETs). Specifically, an explicit closed-form expression is proposed, useful for the fast evaluation of the gate leakage in the context of electrical circuit simulators. A benchmarking test against 1D self-consistent numerical solution of Schrödinger–Poisson (SP) equations has been performed to demonstrate the accuracy of the model.     

A physical model for hole direct tunneling current in p+poly-gate pMOSFETs with ultrathin gate oxides

A model of the hole direct tunneling gate current accounting for heavy and light hole's subbands in the quantized inversion layer is built explicitly. This model comprises four key physical parameters: inversion layer charge density, hole impact frequency on SiO₂-Si interface, WKB transmission probability, and reflection correction factor. With the effective hole mass m_oxh =0.51 M_o for the parabolic dispersion relationship in the oxide, experimental reproduction without any parameter adjustment is consistently achieved in p⁺ poly-gate pMOSFETs with 1.23, 1.85, and 2.16 nm gate oxide thicknesses. The proposed model can thereby serve as a promising characterization means of direct tunnel oxides. In particular, it is calculated that the secondary subbands and beyond, although occupying few holes, indeed contribute substantially to the direct tunneling conduction due to effective lower barrier heights, and are prevailing over the first subbands for reducing the oxide field down below 1 MV/cm     

A model of the stress induced leakage current in gate oxides

A new quantitative model of the stress induced leakage current (SILC) in MOS capacitors with thin oxide layers has been developed by assuming the inelastic trap-assisted tunneling as the conduction mechanism. The oxide band structure has been simplified by replacing the trapezoidal barrier with two rectangular barriers. An excellent agreement between simulations and experiments has been found by adopting a trap distribution Gaussian in space and in energy. Only minor variations of the trap distribution parameters were observed by increasing the injected charge during electrical stress, indicating that oxide neutral defects with similar characteristics are generated at any stage of the stress     

An analytical gate tunneling current model for MOSFETs

Gate tunneling current of MOSFETs is an important factor in modeling ultra small devices. In this paper, gate tunneling in present-generation MOSFETs is studied. In the proposed model, we calculate the electron wave function at the semiconductor-oxide interface and inversion charge by treating the inversion layer as a potential well, including some simplifying assumptions. Then we compute the gate tunneling current using the calculated wave function. The proposed model results have an excellent agreement with experimental results in the literature.     

A surface potential based drain current model for asymmetric double gate MOSFETs

In this paper, we present a generic surface potential based current voltage (I-V) model for doped or undoped asymmetric double gate (DG) MOSFET. The model is derived from the 1-D Poisson’s equation with all the charge terms included and the channel potential is solved for the asymmetric operation of DG MOSFET based on the Newton-Raphson iterative method. A noncharge sheet based drain current model based on the Pao-Sah’s double integral method is formulated in terms of front and back gate surface potentials at the source and drain end. The model is able to clearly show the dependence of the front and back surface potential and the drain current on the terminal voltages, gate oxide thicknesses, channel doping concentrations and the Silicon body thickness and a good agreement is observed with the 2-D numerical simulation results.     

Analytical gate current model for n-channel heterostructure fieldeffect transistors

A simple analytical gate current model for n-channel heterostructure field effect transistors (HFETs) has been developed. Our model is based on the self-consistent approximation to the solution of Schrodinger and Poisson's equations, and the theory of thermionic-field emission. Good agreement between the experimental data and the model results is obtained over the entire range of gate voltages, from below to above threshold, and over a wide range of temperature from 198 to 450 K. Only four parameters are used to fit the experimental data with two of these parameters obtained from the experimental results. This model is suitable for implementation in sophisticated CAD tools such as SPICE     

On gate leakage current partition for MOSFET compact model

Aggressive scaling of the gate-oxide thickness has made gate-tunneling current an essential aspect of MOSFET modeling and this leakage current density continues to increase for every process generation. Accurate compact models for gate-tunneling current and its source/drain partition are extremely critical to valid circuit performance in the 90 nm technology or beyond. Gate current partition has been studied by several authors [Cao K, et al. “BSIM4 gate leakage model including source–drain partition,” in IEDM Tech. Dig., San Francisco, CA, Dec. 2000. p. 815–8; R. van Langevelde et al., Gate current: modeling, ΔL extraction and impact on RF performance, in IEDM Tech. Dig., Washington, DC, Dec. 2001. p. 289–92; Shih W-K, et al., “A general partition scheme for gate leakage current suitable for MOSFET compact models,” in IEDM Tech. Dig., Washington DC., Dec. 2001. p. 293–6]. In this paper, an insight on the common/difference of these different gate leakage current partition schemes into source/drain has been provided and the accuracy of BSIM4 [Cao K, et al. “BSIM4 gate leakage model including source–drain partition,” in IEDM Tech. Dig., San Francisco, CA, Dec. 2000. p. 815–8] partition scheme is confirmed with comparing to the new derived equation, which incorporates the gate current into the inhomogeneous term calculation.     

基于表面势的多晶硅晶体管漏电流物理模型

提出了一种基于薄层电荷模型、陷阱态密度和表面势的多晶硅薄膜晶体管漏电流物理模型。模型采用非迭代的运算方法, 简单且适用于所有大于平带电压的工作区域。 考虑了包括高斯分布的深能态和指数分布的带尾态在内的陷阱分布形式, 陷阱分布参数的提取通过光电子调制谱方法实现。通过模型与现有实验结果的比较, 得到一致的符合结果。     

Enhanced CAD model for gate leakage current in heterostructurefield effect transistors

A simple and accurate circuit model for Heterostructure Field Effect Transistors (HFETs) is proposed to simulate both the gate and the drain current characteristics accounting for hot-electron effects on gate current and the effect of the gate current on the channel current. An analytical equation that describes the effective electron temperature is developed in a simple form. This equation is suitable for implementation in circuit simulators. The model describes both the drain and gate currents at high gate bias voltages. It has been implemented in our circuit simulator AIM-Spice, and good agreement between simulated and measured results is achieved for enhancement-mode HFETs fabricated in different laboratories. The proposed equivalent circuit and model equations are applicable to other compound semiconductor FETs, i.e., GaAs MESFETs     

Drain current model for short-channel triple gate junctionless nanowire transistors

This work proposes a numerical charge-based new model to describe the drain current for triple gate junctionless nanowire transistors (3G JNT). The drain current is obtained through a numerical integration of a single expression that physically describes the junctionless charge density in both accumulation and depletion regimes of operation, leading to a continuous model in all operational regions. The triple gate structure is modeled from an evolution of a previous model designed for double gate junctionless nanowire transistors (2G JNT). Improvements concerning the capacitance coupling, the internal potential changing while reducing the fin height in nanowire transistors and higher immunity to short-channel effects (SCE) are considered. The model validation is performed through both tridimensional numerical simulation and experimental measurements for long and short-channel devices. Through simulated results, it is verified the agreement of the modeled curves for junctionless transistors with different values of fin height. Comparison between the proposed model and experimental data is performed for 3G JNT advanced structures with channel length down to 15 nm and fin height of 8 nm. Results for 3G JNTs with different values of doping concentration and channel width are also displayed showing a good agreement as well. Moreover, 3G JNT performance is also analyzed and compared in the studied structures by extracting the threshold voltage (V_TH), subthreshold slope (S), DIBL and model parameters.     

A quantitative physical model for the band-to-bandtunneling-induced substrate hot electron injection in MOS devices

A quantitative physical model for band-to-band tunneling-induced substrate hot electron (BBISHE) injection in heavily doped n-channel MOSFETs is presented. In BBISHE injection, the injected substrate hot electrons across the gate oxide are generated by impact ionization by the energetic holes which are left behind by the tunneling electrons and become energetic when traveling across the surface high-field region in silicon. The finite available distance for the holes to gain energy for impact ionization is taken into account. A previously published theory of substrate hot electron injection is generalized to account for the spatially distributed nature of the injected electrons. This model is shown to be able to reproduce the I-V characteristics of the BBISHE injection for devices with different oxide thicknesses and substrate dopant concentration biased in inversion or deep depletion. Moreover, it is shown that the effective SiO₂ barrier height for over-the-barrier substrate hot electron injection is more accurately modeled     

Thermionic emission model of electron gate current in submicronNMOSFETs

A thermionic emission model based on a non-Maxwellian electron energy distribution function for the electron gate current in NMOSFET's is described. The model uses hydrodynamic equations to describe more correctly the electron transport and gate injection phenomena in submicron devices. A generalized analytical function is used to describe the high-energy tail of the electron energy distribution function. Coefficients of this generalized function are determined by comparing simulated gate currents with the experimental data. This model also includes the self-consistent calculation of the tunneling component of the gate current by using the WKB approximation, and by using a more accurate representation of the oxide barrier by including the image potential. Good agreement with gate currents over a wide range of bias conditions for three different technological sets of devices are demonstrated by using a single set of coefficients     

A physical model on electron mobility in InGaAs nMOSFETs with stacked gate dielectric

An inversion-channel electron mobility model for InGaAs n-channel metal–oxide-semiconductor field-effect transistors (nMOSFETs) with stacked gate dielectric is established by considering scattering mechanisms of bulk scattering, Coulomb scattering of interface charges, interface-roughness scattering, especially remote Coulomb scattering and remote interface-roughness scattering. The simulation results are in good agreement with the experimental data. The effects of device parameters on degradation of electron mobility, e.g. interface roughness, dielectric constant and thickness of high-k layer/interlayer, and the doping concentration in the channel, are discussed. It is revealed that a tradeoff among the device parameters has to be performed to get high electron mobility with keeping good other electrical properties of devices.     

An analytical programming model for the drain-coupling source-side injection split gate flash EEPROM

This paper presents a compact and accurate analytical model for evaluating the programming behaviors of the drain-coupling source-side injection (SSI) split-gate Flash memory. Starting with the bias-dependent and time-varying drain coupling ratio, a programming model is developed on the basis of the constant barrier height approximation and Lucky-electron model to express the full transient injection current, peak lateral electric field, and storage charge as functions of technological, physical, and electrical parameters. The extracted re-direction mean-free path of the SSI device is smaller than that of the channel hot-electron counterpart by one order of magnitude, which provides the physical intuition for the derived high injection efficiency of around 2/1000. The intrinsic coupling ratio depends only on technological parameters and is presented as the design index of the device. The usefulness of this model is its ability of constructing the complete operation plot of the time-to-program versus the programming voltage for various reliability windows and tunable technological parameters. Besides, the variance of the read current distribution of a memory array is also analytically predicted.     

A physical model for the correlation between holding voltage andholding current in epitaxial CMOS latch-up

A new physical model concerning the holding points for latch-up in epitaxial CMOS structures is established by combining the lateral p-i-n high level injection and the vertical BJT base push-out formula. The model matches adequately the correlation between holding voltage and holding current extensively measured from different combinations of temperatures, epitaxial layer thicknesses, and anode-to-cathode spacings. This is also the case for the two-dimensional device simulations. A quantitative analysis based on the model consistently judges the crucial role of the vertical BJT base push-out width in producing the observed correlation. The potential merits of the model in extended applications are outlined     

一种氮化镓高迁移率晶体管的栅电流噪声模型

This work presents a theoretical and experimental study on the gate current 1/f noise in Al Ga N/Ga N HEMTs. Based on the carrier number fluctuation in the two-dimensional electron gas channel of Al Ga N/Ga N HEMTs, a gate current 1/f noise model containing a trap-assisted tunneling current and a space charge limited current is built. The simulation results are in good agreement with the experiment. Experiments show that, if Vg Vx, gate current 1/f noise comes from not only the trap-assisted tunneling RTS, but also the space charge limited current RTS. This indicates that the gate current 1/f noise of the Ga N-based HEMTs device is sensitive to the interaction of defects and the piezoelectric relaxation. It provides a useful characterization tool for deeper information about the defects and their evolution in Al Ga N/Ga N HEMTs.     

A BiCMOS low-power current mode gate

A controllable BiCMOS low-power current mode logic (LPCML) gate is proposed. The LPCML can be controlled to operate in a high-power mode when its inputs and outputs are in transition. When the gate is idle, it is in a low-power mode and the circuit maintains its output levels with very little tail current. A circuit implementation of the LPCML is also reported with a discussion on its design considerations. A circuit implementation of the LPCML with conventional CML indicates that its delay is greater than that of CML by about 60%. The power consumption of LPCML is proportional to the time it spends in the high-power mode, and, hence, may be significantly lower than that of CML     

A new electron-trapping model for the gate insulator of insulated gate field-effect transistors

In the present paper, a new model for electron trapping kinetics in the gate insulator of an insulated gate field-effect transistor (IGFET) is proposed. This model includes a continuous variation of the trapping cross section, σ_o, as a function of the number of filled traps,N _D . The dependency of σ_o is believed to be related physically to the annihilation, or buildup of coulombic charge, which effect has heretofore been neglected in first-order trapping kinetics that describe the entire defect concentration range. The result is that in order to model the experimental data fewer classes of trap cross sections are needed. AsN _D traps fill, the trapping cross section, σ_o, is assumed to be reduced by a factor (1 -N _D /N _T ) whereN _T is the total number of available traps per unit area. This decrease in δ_o is consistent, physically, with a concept of increasing repulsion of carriers as traps fill. This new model also indicates that the number of injected electrons needed to populate 99% of the total traps is about 20 times greater than that predicted by the existing first-order trapping kinetics model. Comparisons between the results of the new model and the first-order trapping kinetics model applied to experimental defect data are also given.     

A model for the drain voltage and gate voltage dependence of the current fluctuation spectrum of unsaturated JFET's

From the standpoint of the number fluctuation model of the generation-recombination noise and 1/fnoise, a model for the drain and gate voltage dependences of the current fluctuation spectrum of an unsaturated JFET ot MESFET can be established. The derived formula can explain the various experimental results, especially the square-law dependence of the drain voltage throughout almost all of the unsaturated region, and the increasing characteristic of the current fluctuation spectrum with increasing reverse gate voltage. It can also explain the dependence of drain current fluctuation on the device geometric parameters, and finally, it points out that Hooge's expression for the spectral intensity of the current fluctuation can be valid only in the linear region of the device.