CCGA packages for space applications

Commercial-off-the-shelf (COTS) area array packaging technologies in high reliability versions are now being considered for applications, including use in a number of NASA electronic systems being utilized for both the Space Shuttle and Mars Rover missions. Indeed, recently a ceramic package version specifically tailored for high reliability applications was used to provide the processing power required for the Spirit and Opportunity Mars Rovers built by NASA-JPL. Both Rovers successfully completed their 3-months mission requirements and continued exploring the Martian surface for many more moths, providing amazing new information on previous environmental conditions of Mars and strong evidence that water exists on Mars.Understanding process, reliability, and quality assurance (QA) indicators for reliability are important for low risk insertion of these newly available packages in high reliability applications. In a previous investigation, thermal cycle test results for a non-functional daisy-chained peripheral ceramic column grid array (CCGA) and its plastic ball grid array (PBGA) version, both having 560 I/Os, were gathered and are presented here. Test results included environmental data for three different thermal cycle regimes (−55/125 °C, −55/100 °C, and −50/75 °C). Detailed information on these—especially failure type for assemblies with high and low solder volumes—are presented. The thermal cycle test procedure followed those recommended by IPC-9701 for tin–lead solder joint assemblies. Its revision A covers guideline thermal cycle requirements for Pb-free solder joints. Key points on this specification are also discussed.In a recent investigation a fully populated CCGA with 717 I/Os was considered for assembly reliability evaluation. The functional package is a field-programmable gate array that has much higher processing power than its previous version. This new package is smaller in dimension, has no interposer, and has a thinner column wrapped with copper for reliability improvement. This paper will also present thermal cycle test results for assemblies of this and its plastic package version with 728 I/Os, both of which were exposed to four different cycle regimes. Two of these cycle profiles are specified by IPC-9701A for tin–lead, namely, −55 to 100 °C and −55 to 125 °C. One is a cycle profile specified by Mil-Std-883, namely, −65/150 °C, generally used for ceramic hybrid packages screening and qualification. The last cycle is in the range of −120 to 85 °C, a representative of electronic systems directly exposed to the Martian environment without use in a thermal control enclosure. Per IPC-9701A, test vehicles were built using daisy chain packages and were continuously monitored and/or manually checked for opens at intervals. The effects of many process and assembly variables—including corner staking commonly used for improving resistance to mechanical loading such as drop and vibration loads—were also considered as part of the test matrix. Optical photomicrographs were taken at various thermal cycle intervals to document damage progress and behavior. Representative samples of these are presented along with cross-sectional photomicrographs at higher magnification taken by scanning electron microscopy (SEM) to determine crack propagation and failure analyses for packages.     

Ball grid array reliability assessment for aerospace applications

Reliability of ball grid arrays (BGAs) was evaluated with special emphasis on space applications. This work was performed as part of a consortium led by the Jet Propulsion Laboratory (JPL) to help build the infrastructure necessary for implementing this technology. Nearly 200 test vehicles, each with four package types, were assembled and tested using an experiment design. The most critical variables incorporated in this experiment were package type, board material, surface finish, solder volume, and environmental condition. The packages used for this experiment were commercially available packages with over 250 I/Os including both plastic and ceramic BGA packages.The test vehicles were subjected to thermal and dynamic environments representative of aerospace applications. Two different thermal cycling conditions were used, the JPL cycle ranged from −30°C to 100°C and the Boeing cycle ranged from −55°C to 125°C. The test vehicles were monitored continuously to detect electrical failure and their failure mechanisms were characterized. They were removed periodically for optical inspection, scanning electron microscopy (SEM) evaluation, and cross-sectioning for crack propagation mapping. Data collected from both facilities were analyzed and fitted to distributions using the Weibull distribution and Coffin–Manson relationships for failure projection. This paper will describe experiment results as well as those analyses.     

Reliability and RF performance of BGA solder joints with plastic-core solder balls in LTCC/PWB assemblies

In this paper board-level reliability of low-temperature co-fired ceramic (LTCC) modules with thermo-mechanically enhanced ball-grid-array (BGA) solder joint structure mounted on a printed wiring board (PWB) was experimentally investigated by thermal cycling tests in the 0–100 °C and −40 to 125 °C temperature ranges. The enhanced joint structure comprised solder mask defined (SMD) AgPt pad metallization, eutectic solder and plastic-core solder balls (PCSB). Similar daisy-chained LTCC modules with non-collapsible 90Pb10Sn solder spheres were used for a reference test set. The reliability of the joint structures was analyzed by resistance measurements, X-ray microscopy, scanning acoustic microscopy (SAM) and SEM/EDS investigation. In addition, a full-wave electromagnetic analysis was performed to study effects of the plastic-core material on the RF performance of the LTCC/BGA package transition up to millimeter-wave frequencies. Thermal cycling results of the modules with PCSBs demonstrated excellent fatigue performance over that of the reference. In the harsher cycling test, Weibull’s shape factor β values of 7.9 and 4.8, and characteristic lifetime θ values of 1378 and 783 were attained for the modules with PCSBs and 90Pb10Sn solder spheres, respectively. The primary failure mode in all test assemblies was fatigue cracking in eutectic solder on the ceramic side.     

Study of package warp behavior for high-performance flip-chip BGA

To meet the future needs of high pin count and high performance, the LSI die and package size of flip-chip BGA (FC-BGA) devices have become larger. As a result, package warpage due to mismatch of the coefficients of thermal expansion among the construction materials has become a more serious problem for package reliability. In this paper, package warpage is successfully measured by a 3-D surface profile method in the temperature range from −55 to 230 °C. Furthermore, the package warpage of FC-BGA was investigated to clarify the effect of the thermomechanical properties of the underfill resin. Based on the results, we constructed a model of the mechanism of package warpage. This paper proposes an optimized underfill resin that can achieve low package warpage and a long fatigue life of the solder bump. The future trends in underfill resin will be to have properties of extremely low elastic modulus and non-linear properties such as creep.     

BGA封装的焊接技术

随着电子通信产品的迅速发展,作为大规模集成电路封装领域的BGA封装技术受到业界的密切关注,解决了高密度、高性能、多功能及高I/O数的难题,已大量应用于数字通信领域.文中介绍了BGA封装器件的结构特点,从印制电路板设计、印制电路板制作要求、元器件焊接前处理、组装工艺过程控制等几个方面阐述了影响BGA芯片焊接技术的各种因素,借以提高电子通信产品可靠性及稳定性.     

High Cycle Cyclic Torsion Fatigue of PBGA Pb-Free Solder Joints

In this study, a comprehensive experimental and numerical approach was used to investigate high cycle cyclic torsion fatigue behavior of lead-free solder joints in a plastic ball grid array (PBGA) package. The test vehicle was a commercial laptop motherboard. The motherboard was subjected to torsional loading and life tests were conducted. Using finite element analysis (FEA), the test assembly was simulated as a global model and the BGA component was simulated as a local model. Strains measured on the motherboard surface near by the BGA were used to calibrate the FEA models. By combining the life test results and FEA simulations, a high cycle fatigue model for the lead-free solder joints was generated based on the Coffin-Manson strain-range fatigue damage model. This model can now be used to predict the cycles to failure of BGA interconnects for new electronic product design under cyclic torsion loading.     

A visualization-based approach for bump-pad/IO-ball placement and routing in flip-chip/BGA technology

The routing problem in area array integrated circuit (IC) packaging has become an extremely complex problem in the realm of high I/O count IC packages. With the advent of flip-chip and ball grid array (BGA) technology to meet the current demands of smaller size and high wiring densities, the routing problem lies in the core of electronic design automation process. In this paper, we describe an intuitive computer visualization-based approach for placement and routing of bonding pads that would result in low manufacturing costs and smaller component size compared to conventional approaches. This novel approach is an extension of "balls shifted as needed" method for I/O ball placement in BGA package enabling single-layer board-level routing for any I/O count. The I/O ball/pad layout and routing designs along with results are presented for two routing layers with the inclusion of vias in the design. This routing scheme is shown to be easily extensible to accommodate more practical multilayer routing and can be incorporated in current electronic design automation (EDA) computer-aided design (CAD) tools to offer an integrated routing solution for area array chip-package-board codesign. The results show that different trace routing patterns lead to different area requirements for same number of I/Os. This has led to the formulation of new design paradigms which are presented in the paper for smaller component size.     

New dummy design and stiffener on warpage reduction in Ball Grid Array Printed Circuit Board

Printed Circuit Board (PCB) warpage increases as thickness decreases and ultimately is attributed to CTE mismatch and thickness geometry of the components. Recently, a thin Ball Grid Array (BGA) PCB has been developed due to the advantages like high electrical translation speed with low signal noise. Large warpage severely limited by BGA PCB performance leads to reliability issues modes such as crack and delamination between interconnection components. This is why a dummy design on a BGA PCB and metal stiffener on a Flip Chip (FC) BGA PCB warpage are analyzed experimentally.At the first step, new dummy design in BGA PCB (BoC type) is proposed to reduce warpage. The new dummy design is shaped as a bar. Results of the statistical experimental analysis show PCB warpage using the new dummy design is significantly reduced compared to the use of a PCB with a conventional dummy design. Furthermore, the new dummy design decreases PCB warpage by about 67%. These results signify that the stiffness of the BoC PCB is improved by the new dummy design because the bar-shaped Cu pattern in the dummy acts as a rigid bar stiffener.At the second step, metal stiffener effect is studied to reduce coreless FCBGA PCB warpage. Coreless FCBGA PCB, coreless FCBGA package, and specimens with non-symmetric structure are considered to determine metal stiffener effect on warpage. The experimental results show that metal stiffener has high stiffness, and it seems very effective on reducing average and standard deviation of coreless PCB warpage.     

Lead-free plastic area array BGAs and polymer stud grid arrays package reliability

Many packaging and original equipment manufacturers (OEMs) have initiated a program of introducing lead-free electronics. Although lead usage in the packaging industry is relatively small, major efforts are ensuring to eliminate lead usage. In this context, we manufactured and qualified two “green” package solutions: lead-free low-profile fine pitch ball grid array (LFBGA) and polymer stud grid arrays (PSGA^TM) area array packages.The primary source of lead in BGA is in the solder balls. Lead-free solder alloys are readily available, although there is no universal drop-in replacement identified so far for plastic BGAs. One of the most promising alloys for this purpose appears to be the eutectic Sn95.5Ag4Cu0.5, although it involves higher processing temperature. Based on a design of experiment (DOE), the best reflow profile has been determined and used. A lead-free 8×8 mm² LFBGA has been manufactured without other process or equipment changes, and has been qualified for JEDEC moisture level 3, with 245°C reflow simulations, and standard 1st level package reliability tests.An alternative to lead-free plastic BGA is the PSGA^TM. The PSGA^TM package consists of a polymer injection-molded 3D body with a location for chip mounting and polymer studs. The metallized studs, which are by nature lead-free, replace the solder balls within the BGA package. Moisture conditioning and reliability analysis was performed on 8×8 mm² PSGA^TM. The package passed JEDEC moisture conditioning level 3 as well as standard reliability tests.     

高可靠先进微系统封装技术综述

在人工智能、航空航天、国防武器装备电子系统小型化、模块化、智能化需求驱动下,系统级封装设计及关键工艺技术取得了革命性突破。新型的系统封装方法可把不同功能器件集成在一起,并实现了相互间高速通讯功能。封装工艺与晶圆制造工艺的全面融合,使封装可靠性、封装效率得到极大的提升,封装寄生效应得到有效抑制。文章概述了微系统封装结构及类型,阐述了高可靠晶圆级芯片封装(WLP)、倒装焊封装(BGA)、系统级封装(SIP)、三维叠层封装、TSV通孔结构的实现原理、关键工艺技术及发展趋势。     

Board level reliability assessment of chip scale packages

A large program had been initiated to study the board level reliability of various types of chip scale package (CSP). The results on six different packages are reported here, which cover flex interposer CSP, rigid interposer CSP, wafer level assembly CSP, and lead frame CSP. The packages were assembled on FR4 PCBs of two different thicknesses. Temperature cycling tests from −40°C to +125°C with 15 min dwell time at the extremes were conducted to failure for all the package types. The failure criteria were established based on the pattern of electrical resistance change. The cycles to failure were analyzed using Weibull distribution function for each type of package. Selected packages were tested in the temperature/humidity chamber under 85°C/85%RH for 1000 h. Some assembled packages were tested in vibration condition as well. In all these tests, the electrical resistance of each package under testing was monitored continuously. Test samples were also cross-sectioned and analyzed under a Scanning Electronic Microscope (SEM). Different failure mechanisms were identified for various packages. It was noted that some packages failed at the solder joints while others failed inside the package, which was packaging design and process related.     

Temperature profile effects in accelerated thermal cycling of SnPb and Pb-free solder joints

Accelerated thermal cycling (ATC) has been widely used in the microelectronics industry for reliability assessment. ATC testing decreases life cycle test time by one or more of the following means: increasing the heating and cooling rate, decreasing the hold time, or increasing the range of the applied temperature. The relative effect of each of these cycle parameters and the failure mechanisms they induce has been the subject of many studies; however uncertainty remains, particularly regarding the role of the heating and cooling rate. In this research, three conditions with two ramp rates (14 °C/min and 95 °C/min) and two temperature ranges (ΔT = 0–100 °C and −40 to 125 °C) were applied to resistor 2512 and PBGA 256 test vehicles assembled with SnPb and Pb-free solders. The test results showed that the higher ramp rate reduced the testing time while retaining the same failure modes, and that the damage per cycle increased with the temperature difference. For the resistors, the Pb-free solder joints lasted longer than the SnPb joints at the smaller ΔT, but were inferior at the larger ΔT. In contrast, the Pb-free solder joints in the PBGA test vehicles lasted longer than the SnPb solder under both conditions.     

面积阵列封装--BGA和Flip Chip

随着表面安装技术的迅速发展,新的封装技术不断出现,面积阵列封装技术成了现代封装的热门话题,ＢＧＡ和ＦｌｉｐＣｈｉｐ是面积阵列封装的两大类型,它们作为当今大规模集成电路的封装形式,引起电子组装界的关注,而且逐渐在不同领域得到应用。ＢＧＡ和ＦｌｉｐＣｈｉｐ的出现,适应了表面安装技术的需要,解决了高密度、高性能、多功能及高Ｉ／Ｏ数应用的封装难题,预计随着进一步的发展,ＢＧＡ和ＦｌｉｐＣｈｉｐ技术将成为     

BGA和CCGA形位尺寸测试方法研究

BGA和CCGA电路焊球、焊柱的平面位置度、线性度以及PBGA翘曲度是封装检测的必检项目,其测量方法也较多。文章提出用激光测量显微镜来获取电路焊球球心、焊柱轴线的X-Y平面投影坐标,并结合AutoCAD软件,准确给出焊球/焊柱的平面位置度、线性度等,具有直观、快速、简便、精度高等特点,适合BGA和CCGA形位尺寸的在线检测、离线检验。     

Stability of the warpage in a PBGA package subjected to hygro-thermal loading

The CTE and CHE mismatch between materials in a thin PBGA package is primarily attributed to the warpage which occurs when the package is being mounted on to a PCB, especially when the moisture content reaches a specified value. In this paper, the stability equations for the warpage in a PBGA package without the solder balls being subjected to hygro-thermal loading, by modeling it as an initially perfect/imperfect composite plate, have been developed. The analytical closed-form solutions are found and used to compute not only the critical moisture content but also the warpage occurring before the critical loads are reached. The buckling of the PBGA package, at the solder reflow peak temperature, occurs when the theoretical moisture content reaches 0.259–0.283 wt.%. This theoretical critical moisture content accurately predicts the experimental critical moisture content (0.25–0.30 wt.%) derived from our previous work. The results, from comparison between theoretical and experimental critical moisture content, indirectly indicate that the PBGA package has little imperfection. However, the large initial imperfect structure of the package does not easily reach the buckling stage because of moisture absorption. In addition to this, the structure of the PBGA package before buckling become stress-free at the moisture level of 0.077 wt.% and at room temperature during moisture conditioning.     

Underfill selection methodology for fine pitch Cu/low-k FCBGA packages

A systematic underfill selection approach has been presented to characterize and identify suitable underfill encapsulants for large size flip chip ball grid array (FCBGA) packages. In the selection scheme, a total of six evaluation factors such as fracture toughness, coefficient of moisture expansion, flowability, delamination performance and filler settlement were considered. Driving stresses for package failure were also included as a factor of consideration, which clearly depends on the package size and geometry. Based on the approach adopted, underfill material that is suitable for 35 × 35 mm² packages with 15 mm die size and 45 × 45 mm² packages with 21 mm die size was selected. Target value for underfill properties has also been revised.     

High-performance FCBGA based on multi-layer thin-substrate packaging technology

We developed a new concept flip-chip ball grid array (FCBGA) based on multi-layer thin-substrate (MLTS) packaging technology in order to meet the strong demand for high-density, high-performance, and low-cost LSI packages. The most important feature of MLTS packaging is that, only a high-density and high-performance MLTS remains by removing the metal plate after mounting an LSI chip. The MLTS packaging offers the advantages of (1) good registration accuracy, which makes higher-density and finer-pitch pattering possible; (2) an ideal multi-layer structure that is highly suitable for high-speed and high-frequency applications; (3) excellent flip-chip mounting reliability, which makes higher-pin-count and finer-pitch area array flip-chip interconnection possible; (4) excellent reliability, supported by use of high T_g (glass transition temperature) resin; and (5) a cost-effective design achieved as a result of fewer layers fabricated with fine-pitch patterning.We successfully produced a high-performance FCBGA prototype based on our MLTS packaging technology. The prototype comprises an LSI chip connected to approximately 2500 bonding pads arranged in 240 μm pitch area array, and 1296 I/O pads for BGA. The prototype FCBGA’s excellent long-term reliability was demonstrated through a series of tests conducted on it.     

Ribbed package geometry for reducing thermal warpage and wire sweepduring PBGA encapsulation

The effects of changing package shape to a ribbed geometry on thermal warpage and wire sweep of a plastic BGA (PBGA) are investigated in this paper. Three rib geometries (border, diagonal, and cross) with a variation of rib widths and thicknesses are compared with the original plane geometry. Finite element analyses of thermal warpage during the reflow process of PBGA molding with and without ribbed geometry are carried out. Numerical modeling shows that the border rib has the least thermal warpage at the reflow condition. Flow visualization was performed to study the effect of rib geometry on wire sweep, and demonstrates that the wire sweep in ribbed packages is significantly less than that in the original nonribbed package     

Plasma cleaning of plastic ball grid array package

An investigation of O₂, Ar and Ar/H₂ plasma cleaning was carried out on plastic ball grid array (PBGA) substrates to study its effects on surface cleanliness, wire bondability and molding compound/solder mask adhesion. Optimization of the plasma cleaning process parameters was achieved using the contact angle method and verified by auger electron spectroscopy (AES), X-ray photoelectron spectroscopy (XPS) and wedge pull tests. It was found that both the wedge bond quality and moisture sensitivity of a 225 I/O PBGA package were improved after plasma cleaning. Furthermore, atomic force microscopy (AFM) characterization and XPS analysis revealed that the solder mask has undergone plasma-induced surface modification. Cross-contamination of Au and F traces on the solder mask that has occurred during plasma cleaning was identified by XPS. This study has demonstrated the benefits and consequences of plasma cleaning for a PBGA package.     

弯曲应力状况下微型BGA封装可靠性比较研究

微型球栅阵列（μBGA）是芯片规模封装（CSP）的一种形式,已发展成为最先进的表面贴装器件之一。在最新的IxBGA类型中使用低共晶锡．铅焊料球,而不是电镀镍金凸点。采用传统的表面贴装技术进行焊接,研讨μBGA的PCB装配及可靠性。弯曲循环试验（1000～1000με）,用不同的热因数（Qη）回流,研究μBGA、PBGA和CBGA封装的焊点疲劳失效问题。确定液相线上时间,测定温度,μBGA封装的疲劳寿命首先增大,接着随加热因数的增加而下降。当Q。接近500S·℃时,出现寿命最大值。最佳Qη范围在300-750s·℃之间,此范围如果装配是在氮气氛中回流,μBGA封装的寿命大于4500个循环。采用扫描电子显微镜（SEM）,来检查μBGA和PBGA封装在所有加热N数状况下焊点的失效。每个断裂接近并平行于PCB焊盘,在μBGA封装中裂纹总是出现在焊接点与PCB焊盘连接的尖角点,接着在Ni3Sn4金属间化合物（IMC）层和焊料之间延伸。CBGA封装可靠性试验中,失效为剥离现象,发生于陶瓷基体和金属化焊盘之间的界面处。