Novel architecture for a digital switching network

A method for the design of economic PCM switching networks composed of uniform time-space elements is proposed. This method makes it possible to design switching networks having in many cases fewer stages and fewer elements than known networks.     

New structure for digital switching network

Methods for the design of cost-effective one-stage PCM switching networks composed of digital switching matrices are proposed. These one-stage networks have, in many cases, a more regular structure and contain fewer elements than networks currently known. The proposed one-stage networks can also be used as submodules for multistage networks.<>     

Cost-effective digital switching network

A method for the design of cost-effective one-stage PCM switching networks composed of uniform time-space elements is proposed. These one-stage networks can be used as submodules for multistage networks, having, in many cases, fewer elements than currently known networks.     

Practical Multistage Space-Time Switching Networks

This paper discusses PCM switching networks using combined space-time (ST) nonblocking switches in multistage arrays. The interplay between switch, network, and path-search characteristics is considered and the networks chosen for the Swiss system IFS-1 are described.     

Time-Division Switching Networks With Partial-Access Pulse Shifters Performing Serial-Parallel Conversion

Some means of time-slot interchanging is required in a pulse-code-modulation (PCM) transit switching system to satisfy the blocking requirements due to the fact that average trunk loading is high and that the time slots of incoming calls are preassigned at the remote office. This paper presents the use of serial-to-parallel conversion and parallel-to-serial conversion pulse shifters, both having limited time-slot interchange capability at the input and the output of the switching networks, respectively. The features of the system are that the required memory capacity is much smaller than the conventional systems and that serial transmission and parallel switching are possible. The results of optimization through blocking probability evaluation and network cost estimation are also described for networks with one, two, and three gate stages, and with an additional parallel pulse-shifter stage.     

Design of Economic PCM Arrays with a Prescribed Grade of Service

This paper deals with the design of economically structured PCM switching arrays for traffic distribution. The presented switching arrays are symmetrically structured, and have one up to six stages and use different combinations of time stagesTand space stagesS, respectively. It is shown how such arrays can be designed for a required grade of service having a prescribed number of terminations and a prescribed carried traffic per time slot. Their relative costs per termination equal to that per time slot are calculated. These are costs for the gates and costs for memory bits, i.e., speech memories and all control memories. All presented PCM switching arrays are mapped into the corresponding space division multiplex (SDM) arrays. This allows a simple comparison with SDM link systems and an easy calculation of the point-to-point loss. The paper concludes comparing the traffic behavior and costs of the various PCM switching arrays. Finally, new "PCM charts" are developed as useful means for the design of economic PCM switching arrays. A second paper of this congress [14] compares traffic equivalent PCM and SDM switching arrays, respectively, with regard to their economic design, their traffic behavior, and their costs per termination.     

TDM Versus SDM Switching Arrays--Comparison

In the first paper at the 9th ITC [8], PCM (TDM) switching arrays having up to six stages and up to about 100 000 terminations were investigated with regard to their standardized costs per termination as a function of the cost ratio "gate to memory-bit." In this context, the following were considered: the influence of the number and sequence of stages (T-stages,S-stages), the number of terminations, the degree of multiplexing (30, 120 time slots per multiplex line). Furthermore, new PCM charts for the quick design of economic PCM switching arrays were developed. The second paper completes these studies by comparisons between PCM switching arrays and their equivalent SDM switching arrays. Handy formulas for the best possible economic design of PCM and SDM arrays, respectively, are presented and derived. The loss versus the carried traffic of PCM arrays havingS = 3up to six stages and withM = 30and 120 time slots per highway are compared with each other and with equivalent SDM link systems. Furthermore, the relative costs per termination are calculated for these PCM and SDM array structures and drawn versus the size of these arrays.     

Fault-Tolerance In a Multiprocessor, Digital Switching System

Since the introduction of computer-controlled telephone switching systems, fault-tolerance requirements have been described in terms such as ``no more than two hours downtime in 40 years', and ``no more than 2 calls in 10 000 lost by the system.' As microprocessors, pulse code modulation (PCM) and multiprocessing have been added to switching systems, system architects have had to rethink system implementations in striving to meet these goals. This paper describes how the challenge is being met in a family of field-proven, multiprocessor-controlled PCM switching systems.     

A review of compact modeling for phase change memory

Phase change memory(PCM)attracts wide attention for the memory-centric computing and neuromorphic comput-ing.For circuit and system designs,PCM compact models are mandatory and their status are reviewed in this work.Macro mod-els and physics-based models have been proposed in different stages of the PCM technology developments.Compact model-ing of PCM is indeed more complex than the transistor modeling due to their multi-physics nature including electrical,thermal and phase transition dynamics as well as their interactions.Realizations of the PCM operations including threshold switching,set and reset programming in these models are diverse,which also differs from the perspective of circuit simulations.For the purpose of efficient and reliable designs of the PCM technology,open issues and challenges of the compact modeling are also discussed.     

TDMA Site Diversity Switching Experiments with Japanese CS

A site diversity switching experiment system for satellite earth links adopting PCM/PSK/TDMA is introduced. Results of downlink switching experiments using CS (30/20 GHz) are presented. Investigations of measuring time of signal quality for minimizing the diversity. switching error are made in point of Allan variance of bit error rate (BER) and of the defined switching error rate.     

Development of a TDM/FDM Transmultiplexer

Recently, digital systems such as digital telephone switching systems and digital transmission paths are being introduced more and more into communications networks in which signals are handled with Time Division Multiplex (TDM). There still exists, on the other hand, a number of analog transmission paths in which signals are multiplexed with Frequency Division Multiplex (FDM). Therefore, it is important to develop a scheme to interconnect efficiently TDM and FDM systems. Transmultiplexer, which is an equipment directly converting PCM.TDM signals and SSB.FDM signals with each other, is expected to provide an efficient interconneetion between TDM and FDM systems. Authors have developed an experimental transmultiplexer which can provide mutual conversion between a 24-channel PCM primary group (1.544 Mbits/s) and two 12-channel FDM basic groups (60-108 kHz). The developed equipment is designed so as to achieve reduction of the computation rate and simplicity of the hardware by the following techniques: (1) The FFT (Fast Fourier Transform) technique is used to optimize the filtering and multiplexing processes. (2) The spectrum reversion of odd-numbered channel signals is achieved by inverting the sign bits of the PCM signals every other frame. (3) The bandpass sampling technique is applied to obtain SSB.FDM signals directly without frequency shifts at analog FDM stages. In order to evaluate the characteristics of the developed transmultiplexer, experiments have been conducted by connecting it with FDM terminal equipments. The experimental results showed that the transmultiplexer can offer better performance than the tandem connection of standard PCM multiplex equipments and standard FDM terminal equipments with reasonable hardware.     

VoIP与二线电话的PCM时隙交换设计

针对不同网络间的话音通信设计需求,论述了利用内嵌语音网关模块在网络电话(Voice over Internet Protocol,VoIP)与二线模拟电话之间进行话音脉冲编码调制(PCM)时隙交换的设计方案,给出了硬件实现原理和软件设计流程,对话音通信中内VoIP模块性能、PCM信号接口电平的稳定性以及模块间串口包通信的可靠性进行了详细分析。     

Multiplexing and Switching of Data in Synchronous Networks and the Realization in the EDS System

Data networks using PCM transmission links include synchronous data multiplexers and data exchanges. The function of these multiplexers and exchanges is described, taking the system units for synchronous networks of the EDS system as an example.     

An Idea Turns Into Reality--CCITT Activities on the way to ISDN

This paper traces, in broad terms, how the idea of integration of telecommunication services into one network has evolved in the CCITT. A brief overview of existing telecommunication networks is followed by a review of CCITT activities from 1968 to 1980. It had become evident by 1968 that digital technology would not be restricted to transmission only, but would also intrude into switching, signaling, and the terminal field. The CCITT acknowledged this tendency by setting up a Special Study Group entrusted with the study of all questions related to PCM and the coordination of work going on in other Study Groups in the digital field. By 1980 the first ISDN Recommendation (G. 705) was agreed upon, and activities during 1980-1984, when the ISDN took shape, are related in some detail. The structure of the I-Series Recommendations, all relevant to ISDN matters, is described.     

Line Circuit Interfaces for a Digital Switching System

Crucial to the design of digital switching systems for local switching applications is the line circuit interface. It forms the boundary between the analog, 2-wire, subscriber loop, with its attendant environment hostile to low-voltage electronics, and the digital logic environment. ITT North's DSS uses a Quad Line Circuit (QLC) that provides the line circuit interface between four subscriber loops and two PCM multiplexed highways. The QLC contains per-line elements consisting of an electronic 2W/4W hybrid, transmit and receive PCM filters, a codec, two card-mounted relays, and distributed logic for various gating and clocking functions. In addition, there is digital logic common to all four lines for interfacing with redundant microprocessors common to 320 lines. Design of the QLC in a dynamic technology evolution is discussed, and several evolutions of the initial design are presented.     

Dynamic switching characteristic dependence on sidewall angle for phase change memory

In this paper, the volume-minimized model of phase change memory (PCM) cell with Ge₂Sb₂Te₅ (GST) material has been established to study the dynamic switching (set-to-reset) characteristic dependence on the sidewall angle. Joule heating volume, threshold current, dynamic resistance and phase transition rate of PCM cells by current pulse are all calculated. The results show that the threshold current increases with decreasing the sidewall angle and is significantly impacted by the feature size and aspect ratio. The PCM cell of 90° sidewall angle exhibits the smallest Joule heating volume, the highest RESET resistance and the fastest phase transition property.     

Planning of a Digital Hierarchy

The choice of the fundamental parameters of a pulsecode modulation (PCM) system hierarchy depends on many factors, such as transmission media characteristics, time division switching and multiplexing plant requirements, traffic demand and network topology, etc. This paper deals with the problem of clarifying these interdependences and gives the general design criteria for planning a digital hierarchy. In accordance with these criteria, the main characteristics of a digital hierarchy, starting from the 2.048-Mbit/s primary PCM system, are derived and proposed. At present, systems in accordance with this proposal are being developed in Italy.     

A Microprocessor Log PCM/ADPCM Code Converter

A microprocessor has been used to translate between Log PCM and ADPCM (Adaptive Differential PCM) code forms. This system, in bridging the gap between simulation and prototyping, provides realtime speech processing with user interaction. Continuously coded speech can he subjectively evaluated while switching the values of code word length, step size, or predictor coefficients. Translations of additional code forms such as Δ-Mod, NIC, or Tree Codes could easily be implemented with the micro-codable system. The processor is configured as a stand-alone device competitive with special purpose hardware in size, speed, and cost.     

Ingénierie des systèmes de commutation optique et des réseaux locaux à large bande sur fibres optiques : analyses et perspectives

This paper first reviews how switching evolves in the ISDN environment with emphasize placed on changes in conventionnal time-division switches, then assesses techniques and technologies usable in optical switching and broadband networks : optical space-division switching systems (architecture, technologies based on dielectrics, semiconductors, photorepactive material) and optical time-division switching (optical memories based on delay lines and on bistable components multiplexing); multiple access networks (tdma, multiple access by code) ; switching using spread spectrum (bit switching); wavelength switching (multiplexer-demultiplexer, tunable laser and filters) ; packet switching in multi-wavelength networks (broadband networks standardization, local area networks with bus, passive star or multi-star configuration).     

Efficiency of packet voice with deterministic delay

Packet switching is appealing for carrying real-time traffic because it can benefit from (possibly variable bit rate) compression schemes and statistical multiplexing to more efficiently exploit network resources. This work explores the efficiency of IP telephony in terms of the volume of voice traffic carried with deterministically guaranteed quality related to the amount of network resources used. An IP network carrying compressed voice is compared to circuit switching carrying PCM (64 kb/s) encoded voice, and some design choices affecting IP telephony efficiency are discussed