A 3.3-mW /spl Sigma//spl Delta/ modulator for UMTS in 0.18-/spl mu/m CMOS with 70-dB dynamic range in 2-MHz bandwidth

A quadrature fourth-order, continuous-time, /spl Sigma//spl Delta/ modulator with 1.5-b quantizer and feedback digital-to-analog converter (DAC) for a universal mobile telecommunication system (UMTS) receiver chain is presented. It achieves a dynamic range of 70 dB in a 2-MHz bandwidth and the total harmonic distortion is -74 dB at full-scale input. When used in an integrated receiver for UMTS, the dynamic range of the modulator substantially reduces the need for analog automatic gain control and its tolerance of large out-of-band interference also permits the use of only first-order prefiltering. An IC including an I and Q /spl Sigma//spl Delta/ modulator, phase-locked loop, oscillator, and bandgap dissipates 11.5 mW at 1.8 V. The active area is 0.41 mm/sup 2/ in a 0.18-/spl mu/m 1-poly 5-metal CMOS technology.     

A 25-MS/s 14-b 200-mW /spl Sigma//spl Delta/ Modulator in 0.18-/spl mu/m CMOS

The design of a fifth-order 4-b quantizer single-loop /spl Sigma//spl Delta/ modulator is presented that achieves 25-MS/s conversion rate with 84 dB of dynamic range and 82 dB of signal-to-noise ratio. Implemented in a 0.18-/spl mu/m CMOS technology, the 0.95-mm/sup 2/ chip has a power consumption of 200 mW from a 1.8-V supply.     

A 14-bit high-temperature /spl Sigma//spl Delta/ modulator in standard CMOS

Experimental verification is given for the use of /spl Sigma//spl Delta/ modulation for high-temperature applications (/spl ges/approximately 150/spl deg/C) in a standard CMOS process. Switched-capacitor circuits are used to implement a second-order single-stage and a third-order 2-1 MASH /spl Sigma//spl Delta/ modulator with single-bit quantization. The two modulators have an oversampling ratio of 256 with an input signal bandwidth of 500 Hz. The modulators were fabricated in a 1.5-/spl mu/m standard CMOS technology. A fully differential signal path and near minimum sized switches are used to mitigate the effect of large junction-to-substrate leakage current present at high temperatures. Experimental results show both modulators are capable of over 14 bits of resolution at 225/spl deg/C and over 13 bits of resolution at 255/spl deg/C. Results show that the single-stage modulator is more resistant to high-temperature circuit impairment than is the MASH cascaded structure.     

A 1.5-V 12-bit power-efficient continuous-time third-order /spl Sigma//spl Delta/ modulator

This paper presents the design strategy, implementation, and experimental results of a power-efficient third-order low-pass /spl Sigma//spl Delta/ analog-to-digital converter (ADC) using a continuous-time (CT) loop filter. The loop filter has been implemented by using active RC integrators. Several power optimizations, design requirements, and performance limitations relating to circuit nonidealities in the CT modulator are presented. The influence of the low supply voltage on the various building blocks such as the amplifier as well as on the overall /spl Sigma//spl Delta/ modulator is discussed. The ADC was implemented in a 3.3-V 0.5-/spl mu/m CMOS technology with standard threshold voltages. Measurements of the low-power 1.5-V CT /spl Sigma//spl Delta/ ADC show a dynamic range and peak signal-to-noise-plus-distortion ratio of 80 and 70 dB, respectively, in a bandwidth of 25 kHz. The measured power consumption is only 135 /spl mu/W from a single 1.5-V power supply.     

A Bluetooth radio in 0.18-/spl mu/m CMOS

This paper describes the results of an implementation of a Bluetooth radio in a 0.18-/spl mu/m CMOS process. A low-IF image-reject conversion architecture is used for the receiver. The transmitter uses direct IQ-upconversion. The VCO runs at 4.8-5.0 GHz, thus facilitating the generation of 0/spl deg/ and 90/spl deg/ signals for both the receiver and transmitter. By using an inductor-less LNA and the extensive use of mismatch simulations, the smallest silicon area for a Bluetooth radio implementation so far can be reached: 5.5 mm/sup 2/. The transceiver consumes 30 mA in receive mode and 35 mA in transmit mode from a 2.5 to 3.0-V power supply. As the radio operates on the same die as baseband and SW, the crosstalk-on-silicon is an important issue. This crosstalk problem was taken into consideration from the start of the project. Sensitivity was measured at -82 dBm.     

Sturdy MASH /spl Delta//spl Sigma/ modulator

A new Delta-Sigma modulator is proposed. Its operation is similar to that of a multi-stage noise-shaping structure but requires no digital noise cancellation filters. Thus, the need for matching required between analogue and digital filters is eliminated. Simulation results and mathematical analysis demonstrate the effectiveness of this structure     

A 0.18-/spl mu/m CMOS bioluminescence detection lab-on-chip

The paper describes a bioluminescence detection lab-on-chip consisting of a fiber-optic faceplate with immobilized luminescent reporters/probes that is directly coupled to an optical detection and processing CMOS system-on-chip (SoC) fabricated in a 0.18-/spl mu/m process. The lab-on-chip is customized for such applications as determining gene expression using reporter gene assays, determining intracellular ATP, and sequencing DNA. The CMOS detection SoC integrates an 8 /spl times/ 16 pixel array having the same pitch as the assay site array, a 128-channel 13-bit ADC, and column-level DSP, and is fabricated in a 0.18-/spl mu/m image sensor process. The chip is capable of detecting emission rates below 10/sup -6/ lux over 30 s of integration time at room temperature. In addition to directly coupling and matching the assay site array to the photodetector array, this low light detection is achieved by a number of techniques, including the use of very low dark current photodetectors, low-noise differential circuits, high-resolution analog-to-digital conversion, background subtraction, correlated multiple sampling, and multiple digitizations and averaging to reduce read noise. Electrical and optical characterization results as well as preliminary biological testing results are reported.     

A high-frequency double-sampling second-order /spl Delta//spl Sigma/ modulator

As the minimum feature size of VLSI technologies scales down, more of the signal processing tasks are performed in the digital domain. This results in increased speed, resolution, and dynamic range requirements for the analog-to-digital converter (ADC). High-speed and high-accuracy designs can be achieved by using oversampling ADC structures, which demand amplifiers with a high gain and a high unity-gain frequency. Due to the difficulty to meet both of these specifications, the ADC resolution at a frequency in the megahertz range appears to be limited by amplifier settling requirements. Design techniques to improve the ADC performance are presented. The proposed modulator structure uses the double-sampled technique, which increases by a factor of two the maximum speed of operation and correctly operates even with low dc gain amplifiers. Furthermore, the signal-to-noise ratio is significantly improved by a calibration stage, which dynamically estimates the offset errors to be removed by a simple subtraction from the output signal.     

A low-voltage folded-switching mixer in 0.18-/spl mu/m CMOS

Scaling of CMOS technologies has a great impact on analog design. The most severe consequence is the reduction of the voltage supply. In this paper, a low voltage, low power, AC-coupled folded-switching mixer with current-reuse is presented. The main advantages of the introduced mixer topology are: high voltage gain, moderate noise figure, moderate linearity, and operation at low supply voltages. Insight into the mixer operation is given by analyzing voltage gain, noise figure (NF), linearity (IIP3), and DC stability. The mixer is designed and implemented in 0.18-/spl mu/m CMOS technology with metal-insulator-metal (MIM) capacitors as an option. The active chip area is 160 /spl mu/m/spl times/200 /spl mu/m. At 2.4 GHz a single side band (SSB) noise figure of 13.9 dB, a voltage gain of 11.9 dB and an IIP3 of -3 dBm are measured at a supply voltage of 1 V and with a power consumption of only 3.2 mW. At a supply voltage of 1.8 V, an SSB noise figure of 12.9 dB, a voltage gain of 16 dB and an IIP3 of 1 dBm are measured at a power consumption of 8.1 mW.     

A matrix amplifier in 0.18-/spl mu/m SOI CMOS

A fully integrated matrix amplifier with two rows and four columns (2-by-4) fabricated in a three-layer metal 0.18-/spl mu/m silicon-on-insulator (SOI) CMOS process is presented. It exhibits an average pass-band gain of 15 dB and a unity-gain bandwidth of 12.5 GHz. The input and output ports are matched to 50 /spl Omega/ using m-derived half sections; the measured S/sub 11/ and S/sub 22/ values exceed -7 and -12 dB, respectively. Integrated in 2.0/spl times/2.9mm/sup 2/, it dissipates 233.4 mW total from 2.4- and 1.8-V power supplies.     

A low-power multi-bit /spl Sigma//spl Delta/ modulator in 90-nm digital CMOS without DEM

Multi-bit sigma-delta modulators are widely used in analog-to-digital conversion especially in the modern deep-submicron CMOS process. As the quantizer resolution of /spl Sigma//spl Delta/ modulators increases, the SNR performance improves. However, the feedback DAC has to maintain high linearity. The general practice to achieve that is to use dynamic element matching (DEM). The methodology proposed in this paper will greatly reduce the complexity or even avoid usage of DEM for multi-bit /spl Sigma//spl Delta/ modulators. The proposed methodology-truncation error shaping and cancellation-reduces the feedback DAC levels for multi-bit quantizers. A prototype was designed in a standard CMOS 90-nm process to demonstrate the proposed methodologies. It achieved targeted performance without DEM at low power consumption with small silicon area.     

A 0.7-V MOSFET-only switched-opamp /spl Sigma//spl Delta/ modulator in standard digital CMOS technology

A 0.7-V MOSFET-only /spl Sigma//spl Delta/ modulator for voice band applications is presented. The second-order modulator is realized using a switched-opamp technique. All capacitors are realized using compensated MOS devices operated in the depletion region. A combination of parallel and series compensated depletion-mode MOSCAPs is used to obtain high area efficiency. The circuit is fabricated in a 0.18-/spl mu/m CMOS process. The only components used are standard n-MOS and p-MOS transistors with threshold voltages of approximately 400 mV. All transistors are operated within the supply voltage window of 0.7 V; voltage boosting techniques are not used. The active area is 0.082 mm/sup 2/. The modulator achieves 67-dB signal-to-noise-and-distortion ratio, 70-dB signal-to-noise ratio, and 75-dB dynamic range at 8-kHz signal bandwidth and consumes 80 /spl mu/W of power.     

Highly linear 2.5-V CMOS /spl Sigma//spl Delta/ modulator for ADSL+

We present a 90-dB spurious-free dynamic range sigma-delta modulator (/spl Sigma//spl Delta/M) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25-/spl mu/m CMOS process with metal-insulator-metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band (ADSL+) and 85-dB DR in the 30-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within /spl plusmn/0.85 and /spl plusmn/0.80 LSB/sub 14 b/, respectively. The /spl Sigma//spl Delta/ modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the /spl Sigma//spl Delta/ modulator.     

A low-power oscillator mixer in 0.18-/spl mu/m CMOS technology

A downconversion double-balanced oscillator mixer using 0.18-/spl mu/m CMOS technology is proposed in this paper. This oscillator mixer consists of an individual mixer stacked on a voltage-controlled oscillator (VCO). The stacked structure allows entire mixer current to be reused by the VCO cross-coupled pair to reduce the total current consumption of the individual VCO and mixer. Using individual supply voltages and eliminating the tail current source, the stacked topology requires 1.0-V low supply voltage. The oscillator mixer achieves a voltage conversion gain of 10.9 dB at 4.2-GHz RF frequency. The oscillator mixer exhibits a tuning range of 11.5% and a single-sideband noise figure of 14.5 dB. The dc power consumption is 0.2 mW for the mixer and 2.94 mW for the VCO. This oscillator mixer requires a lower supply voltage and achieves a higher operating frequency among recently reported Si-based self-oscillating mixers and mixer oscillators. The mixer in this oscillator mixer also achieves a low power consumption compared with recently reported low-power mixers.     

A 5.9-GHz voltage-controlled ring oscillator in 0.18-/spl mu/m CMOS

This paper presents the design of three- and nine-stage voltage-controlled ring oscillators that were fabricated in TSMC 0.18-/spl mu/m CMOS technology with oscillation frequencies up to 5.9 GHz. The circuits use a multiple-pass loop architecture and delay stages with cross-coupled FETs to aid in the switching speed and to improve the noise parameters. Measurements show that the oscillators have linear frequency-voltage characteristics over a wide tuning range, with the three- and nine-stage rings resulting in frequency ranges of 5.16-5.93 GHz and 1.1-1.86 GHz, respectively. The measured phase noise of the nine-stage ring oscillator was -105.5 dBc/Hz at a 1-MHz offset from a 1.81-GHz center frequency, whereas the value for the three-stage ring oscillator was simulated to be -99.5 dBc/Hz at a 1-MHz offset from a 5.79-GHz center frequency.     

11 GHz CMOS /spl Sigma//spl Delta/ frequency synthesiser

A fully integrated 11 GHz fractional-N PLL with a three-stage MASH SigmaDelta modulator with DC dither in all stages is implemented in a standard 0.13 mum CMOS technology. The synthesiser generates no fractional spurs at frequency offsets outside the loop bandwidth and a small number of fractional spurs with the power not exceeding -44 dBc within the loop bandwidth at the carrier frequency of 11 GHz     

A time-delay jitter-insensitive continuous-time bandpass /spl Delta//spl Sigma/ modulator architecture

In this paper, we present a new continuous-time bandpass delta-sigma (/spl Delta//spl Sigma/) modulator architecture with mixer inside the feedback loop. The proposed bandpass /spl Delta//spl Sigma/ modulator is insensitive to time-delay jitter in the digital-to-analog conversion feedback pulse, unlike conventional continuous-time bandpass /spl Delta//spl Sigma/ modulators. The sampling frequency of the proposed /spl Delta//spl Sigma/ modulator can be less than the center frequency of the input narrow-band signal.     

A 40-GHz frequency divider in 0.18-/spl mu/m CMOS technology

An analysis of regenerative dividers predicts the required phase shift or selectivity for proper operation. A divider topology is introduced that employs resonance techniques by means of on-chip spiral inductors to tune out the device capacitances. Configured as two cascaded /spl divide/2 stages, the circuit achieves a frequency range of 2.3 GHz at 40 GHz while consuming 31 mW from a 2.5-V supply.     

A 285-MHz pipelined MAP decoder in 0.18-/spl mu/m CMOS

Presented in this paper is a pipelined 285-MHz maximum a posteriori probability (MAP) decoder IC. The 8.7-mm/sup 2/ IC is implemented in a 1.8-V 0.18-/spl mu/m CMOS technology and consumes 330 mW at maximum frequency. The MAP decoder chip features a block-interleaved pipelined architecture, which enables the pipelining of the add-compare-select kernels. Measured results indicate that a turbo decoder based on the presented MAP decoder core can achieve: 1) a decoding throughput of 27.6 Mb/s with an energy-efficiency of 2.36 nJ/b/iter; 2) the highest clock frequency compared to existing 0.18-/spl mu/m designs with the smallest area; and 3) comparable throughput with an area reduction of 3-4.3/spl times/ with reference to a look-ahead based high-speed design (Radix-4 design), and a parallel architecture.     

Robust sound localization in 0.18 /spl mu/m CMOS

This paper presents a hardware implementation of a sound localization algorithm that localizes a single sound source by using the information gathered by two separated microphones. This is achieved through estimating the time delay of arrival (TDOA) of sound at the two microphones. We have used a TDOA algorithm known as the "phase transform" to minimize the effects of reverberations and noise from the environment. Simplifications to the chosen TDOA algorithm were made in order to replace complex operations, such as the cosine function, with less expensive ones, such as iterative additions. The custom digital signal processor implementing this algorithm was designed in a 0.18-/spl mu/m CMOS process and tested successfully. The test chip is capable of localizing the direction of a sound source within 2.2/spl deg/ of accuracy, utilizing approximately 30 mW of power and 6.25 mm/sup 2/ of silicon area.