共查询到20条相似文献,搜索用时 46 毫秒
1.
Ismail Y.I. Friedman E.G. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2000,8(2):195-206
A closed-form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range of RLC loads. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treated as a distributed RC line can be over 35% for current on-chip interconnect. It is also shown that the traditional quadratic dependence of the propagation delay on the length of the interconnect for RC lines approaches a linear dependence as inductance effects increase. On-chip inductance is therefore expected to have a profound effect on traditional high-performance integrated circuit (IC) design methodologies. The closed-form delay model is applied to the problem of repeater insertion in RLC interconnect. Closed-form solutions are presented for inserting repeaters into RLC lines that are highly accurate with respect to numerical solutions. RC models can create errors of up to 30% in the total propagation delay of a repeater system as compared to the optimal delay if inductance is considered. The error between the RC and RLC models increases as the gate parasitic impedances decrease with technology scaling. Thus, the importance of inductance in high-performance very large scale integration (VLSI) design methodologies will increase as technologies scale 相似文献
2.
To analyze at which rise/fall times the inductance effect appears in DSM interconnects, the author develops a methodology versus the input line transition time to be technology-independent. These lines are modeled as RC and RLC distributed lines, and the two models are compared to define the effects caused by neglecting inductance. The goal of this study is, based upon the discrepancy between RC and RLC models, to define when inductance must be included in the modeling of interconnects. A simple rule permits the choice of the simplest model (RC or RLC) for a given accuracy. The length range concerned by the inductive effect is calculated from the complex propagation factor value. The theoretical limits are illustrated on several interconnection configurations, on a 0.18-/spl mu/m technology. 相似文献
3.
Azadpour M.A. Kalkur T.S. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2003,11(6):1143-1146
Due to decreasing device sizes and increasing clock speed, interconnect inductance is becoming an important factor in the on-chip delay analysis of deep submicrometer technologies. This delay has been represented as an RC model in the available electric design automation tools. In this paper, we model the on-chip interconnect as a RLC for systems running at multigigahertz frequencies. A static-extraction analysis method optimized for ASICs is detailed. It considers all the lines within the vicinity of the target signal line as return paths. 相似文献
4.
Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints 总被引:1,自引:0,他引:1
Guoqing Chen Friedman E.G. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2006,14(2):161-172
Interconnect plays an increasingly important role in deep-submicrometer very large scale integrated technologies. Multiple design criteria are considered in interconnect design, such as delay, power, and bandwidth. In this paper, a repeater insertion methodology is presented for achieving the minimum power in an RC interconnect while satisfying delay and bandwidth constraints. These constraints determine a design space for the number and size of the repeaters. The minimum power is shown to occur at the edge of the design space. With delay constraints, closed form solutions for the minimum power are developed, where the average error is 7% as compared with SPICE. With bandwidth constraints, the minimum power can be achieved with minimum-sized repeaters. The effects of inductance on the delay, bandwidth, and power of an RLC interconnect with repeaters are also analyzed. By including inductance, the minimum interconnect power under a delay or bandwidth constraint decreases as compared with an RC interconnect. 相似文献
5.
Sang-Pil Sim Krishnan S. Petranovic D.M. Arora N.D. Kwyro Lee Yang C.Y. 《Electron Devices, IEEE Transactions on》2003,50(6):1501-1510
In this paper, we propose a compact on-chip interconnect model for full-chip simulation. The model consists of two components, a quasi-three-dimensional (3-D) capacitance model and an effective loop inductance model. In the capacitance model, we propose a novel concept of effective width (W/sub eff/) for a 3-D wire, which is derived from an analytical two-dimensional (2-D) model combined with a new analytical "wall-to-wall" model. The effective width provides a physics-based approach to decompose any 3-D structure into a series of 2-D segments, resulting in an efficient and accurate capacitance extraction. In the inductance model, we use an effective loop inductance approach for an analytic and hierarchical model construction. In particular, we show empirically that high-frequency signals (above multi-GHz) propagating through random signal lines can be approximated by a quasi-TEM mode relationship, leading to a simple way to extract the high-frequency inductance from the capacitance of the wire. Finally, the capacitance and inductance models are combined into a unified frequency-dependent RLC model, describing successfully the wide-band characteristics of on-chip interconnects up to 100 GHz. Non-orthogonal wire architecture is also investigated and included in the proposed model. 相似文献
6.
So Young Kim Wong S.S. 《IEEE transactions on circuits and systems. I, Regular papers》2007,54(9):2001-2010
The Elmore delay model is the most popular and efficient delay model used for analytical delay estimation. Closed-form delay formulas are useful for circuit design, timing-driven physical design, synthesis, and optimization. As signal rise time becomes faster and the line resistance becomes smaller from copper technology, the significance of inductance increases. Both RC and RLC delays are a strong function of signal rise time. We propose a novel and efficient delay modeling method based on nondimensionalization to consider finite input rise time as an improvement over the Elmore's approach. To further improve the accuracy of the delay model, a new correction method, effective distance correction factor (EDCF), is proposed to consider resistive shielding of downstream capacitance. EDCF can be used to correct the delays for both RC and RLC tree structures. The proposed delay modeling method was applied to a number of nets selected from an integrated circuit (IC) design, and the delay estimation results were compared with HSPICE simulations. The new delay model retains the efficiency and simplicity of the Elmore delay model with significantly improved accuracy. 相似文献
7.
Xiaoning Qi Gyure A. Yansheng Luo Lo S.C. Shahram M. Singhal K. 《Electron Device Letters, IEEE》2006,27(8):696-698
The on-chip inductive impact on signal integrity has been a problem for designs in deep-submicrometer technologies. The inductive impact increases the clock skew, max timing, and noise of bus signals. In this letter, circuit simulations using silicon-validated macromodels show that there is a significant inductive impact on the signal max timing (/spl sim/ 10% pushout versus RC delay) and noise (/spl sim/2/spl times/RC noise). In nanometer technologies, process variations have become a concern. Results show that device and interconnect process variations add /spl sim/ 3% to the RLC max-timing impact. However, their impact on the RLC signal noise is not appreciable. Finally, inductive impact in 65- and 45-nm technologies is investigated, which indicates that the inductance impact will not diminish as technology scales. 相似文献
8.
Ismail Y.I. Friedman E.G. Neves J.L. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》1999,7(4):442-449
A closed-form solution for the output signal of a CMOS inverter driving an RLC transmission line is presented. This solution is based on the alpha power law for deep submicrometer technologies. Two figures of merit are presented that are useful for determining if a section of interconnect should be modeled as either an RLC or an RC impedance. The damping factor of a lumped RLC circuit is shown to be a useful criterion. The second useful figure of merit considered in this paper is the ratio of the rise time of the input signal at the driver of an interconnect line to the time of flight of the signals across the line. AS/X circuit simulations of an RLC transmission line and a five section RC II circuit based on a 0.25-μm IBM CMOS technology are used to quantify and determine the relative accuracy of an RC model. One primary result of this paper is evidence demonstrating that a range for the length of the interconnect exists for which inductance effects are prominent. Furthermore, it is shown that under certain conditions, inductance effects are negligible despite the length of the section of interconnect 相似文献
9.
El-Moursy M.A. Friedman E.G. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2005,13(3):396-400
Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effective capacitance of an RLC load driven by a CMOS inverter is presented. The interconnect inductance decreases the gate delay and increases the time required for the signal to propagate across an interconnect, reducing the overall delay to drive an RLC load. Ignoring the line inductance overestimates the circuit delay, inefficiently oversizing the circuit driver. Considering line inductance in the design process saves gate area, reducing dynamic power dissipation. Average reductions in power of 17% and area of 29% are achieved for example circuits. An accurate model for a CMOS inverter and an RLC load is used to characterize the propagation delay. The accuracy of the delay model is within an average error of less than 9% as compared to SPICE. 相似文献
10.
The effect of random signal lines on the on-chip inductance is quantitatively investigated, using an S-parameter-based methodology and a full wave solver, leading to an empirical model for high-frequency inductance. The results clearly indicate that the random signal lines as well as designated ground lines provide return paths for gigahertz-frequency signals. In particular, quasi TEM-wave-like propagation mode is observed above 10 GHz, revealing a unique relationship between capacitance and inductance of the signal line. Incorporating the random capacitive coupling effect, our frequency-dependent RLC model is confirmed to be valid up to 100 GHz. 相似文献
11.
《Microwave Theory and Techniques》2009,57(6):1572-1580
12.
13.
An efficient timing modelling scheme for coupled inductance dominant resistance inductance capacitance (RLC) interconnects is presented. The transfer function in the Laplace domain is expanded in a series of rational, polynomial and exponential products, the time-domain responses of which can be computed analytically. The resulting time-domain response has fast convergence yet maintains high fidelity of non-monotonic characteristics of RLC transmission line circuits. By using an analytical decoupling technique, an efficient analytical timing model for coupled inductance dominant RLC interconnects is constructed. 相似文献
14.
互连线RC模型应用条件的仿真研究 总被引:3,自引:0,他引:3
研究结果表明,在L与RC比值较小时,阶跃响应的上升时间基本上由RC的乘积决定,电感对电路的影响可以忽略,互连线采用RC模型与RLC模型结果应无多大差别。在L与RC比值较大时,阶跃响应曲线出现振荡,此时使用RC模型需满足工作频率低于RC模型的“上限使用频率;当工作频率超过RC模型的“上限使用频率”时,互连线的模型就必须采用RLC模型。RC模型的“上限使用频率”仅与互连线长度有关:fmax106(Hz·m)。 相似文献
15.
快速估计互连线网的信号传输特性是VLSI设计中的重要问题,矩匹配是目前的主要方法.本文给出了获得RLC传输线精确矩模型的一个简单方法,避免了以往方法复杂的推导.文中还提出了互连线时延估计的一个新方法,这一方法不仅可用于目前通常的二阶模型,还可对高阶模型进行估计. 相似文献
16.
Awwad F.R. Nekili M. Ramachandran V. Sawan M. 《IEEE transactions on circuits and systems. I, Regular papers》2008,55(1):322-335
17.
18.
19.
Yu Cao Xiaodong Yang Xuejue Huang Sylvester D. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2005,13(9):1072-1078
Timing uncertainty caused by inductive and capacitive coupling is one of the major bottlenecks in timing analysis. In this paper, we propose an effective loop RLC modeling technique to efficiently decouple lines with both inductive and capacitive coupling. We generalize the RLC decoupling problem based on the theory of distributed RLC lines and a switch-factor, which is the voltage ratio between two nets. This switch-factor is also known as the Miller factor, and is widely used to model capacitive coupling. The proposed modeling technique can be directly applied to partial RLC netlists extracted using existing parasitic extraction tools without advance knowledge of the return path. The new model captures the impact of neighboring switching activity as it significantly affects the current return path. As demonstrated in our experiments, the new model accurately predicts both upper and lower delay bounds as a function of neighboring switching patterns. Therefore, this approach can be easily implemented into existing timing analysis flows such as max-timing and min-timing analysis. Finally, we apply the new modeling approach to a range of activities across the design process including timing optimization, static timing analysis, high frequency clock design, and data-bus wire planning. 相似文献
20.
Compact physical models are presented for on-chip double-sided shielded transmission lines, which are mainly used for long global interconnects where inductance effects should not be ignored. The models are then used to optimize the width and spacing of long global interconnects with repeater insertion. The impacts of increasing line width and spacing on various performance parameters such as delay, data-flux density, power dissipation and total repeater area are analysed. The product of data-flux density and reciprocal delay per unit length are defined as a figure of merit (FOM). By maximizing the FOM, the optimal width and spacing of shielded RLC global interconnects are obtained for various international technology roadmap for semiconductors (ITRS) technology nodes. 相似文献