Crosstalk modeling for coupled RLC interconnects with application to shield insertion

On-chip interconnect delay and crosstalk noise have become significant bottlenecks in the performance and signal integrity of deep submicrometer VLSI circuits. A crosstalk noise model for both identical and nonidentical coupled resistance-inductance-capacitance (RLC) interconnects is developed based on a decoupling technique exhibiting an average error of 6.8% as compared to SPICE. The crosstalk noise model, together with a proposed concept of effective mutual inductance, is applied to evaluate the effectiveness of the shielding technique.     

On the impact of on-chip inductance on signal nets under the influence of power grid noise

It has been well recognized that the impact of on-chip inductance on some critical nets, such as clock nets, is significant and cannot be ignored in delay modeling for these nets. However, the impact of on-chip inductance on signal nets in general is still not well understood. We present results of analyzing inductive effects on signal nets for ultradeep submicron technologies under the influence of power grid noise. The analysis is based on an Al-based 0.18-/spl mu/m CMOS process and a Cu-based 0.13-/spl mu/m CMOS process. The impact of on-chip inductance is shown to be insignificant if we assume a perfect power supply network around the interconnect routes. Otherwise, the impact of on-chip inductance can be significant. Furthermore, the results presented in this paper illustrate the impact of on-chip inductance one would expect from transitioning from an Al-based interconnect technology to a Cu-based interconnect technology. A heuristic method is proposed in the paper to account for the inductive coupling due to power grid noise in signal delay modeling and simulations.     

Modulation techniques for multiple access to a hard-limiting satellite repeater

This paper considers the problem of devising modulation techniques that allow a large number of earth stations to use, simultaneously, a satellite repeater with the transfer characteristics of a wide-band hard-limiting amplifier. Four distinct classes of modulation techniques and their singular properties are described. Three important design considerations are discussed: repeater bandwidth and power sharing, network timing, and operational considerations. The paper provides a framework for further study of the multiple access problem. The hard-limiting repeater is shown to accommodate a wide variety of signal designs. No single class of multiple-access modulation techniques is found to be uniformly best in satisfying all needs of the diverse networks which can use communication satellites.     

Gigahertz analog repeater for fiber optic delay lines

A gigahertz analog fiber optic repeater is used to extend the achievable delay time for radar delay line applications. The repeater consists of a silicon avalanche photodiode (APD), a wide-band amplifier, and a GaAlAs laser diode transmitter. This repeater has an optical gain of 14.5 dB, a 42 dB electrical dynamic range, and a noise figure of approximately 6.5 dB. The frequency response is flat within ±2 dB over the frequency range from 10 MHz to 1.3 GHz. The nanosecond pulse fidelity is such that the subtraction between input and output pulses is 20 dB below the pulse amplitude.     

CMOS on-chip clock for digital signal processors

An on-chip clock for frequencies up to 190 MHz is presented. This clock generator can be used for application specific digital signal processors which are clocked faster than the off-chip system clock. It is useful for both processors with a few cycles per sample or for high frequency bit-serial processors which need a large number of cycles.<>     

直放站的原理与应用

直放站是随着移动通信的发展而出现的一种无线通信设备。直放站的应用在第一代模拟移动通信网建立时就已经开始，当时的设备体积大、价格高、指标较差，使用中经常对网络造成干扰。目前使用的直放站设备外观和指标已经大大改善，但调试不好也会影响系统的性能。直放站的大量应用是近两年的事情，尤其随着CDMA网开通和GSM网的深度覆盖，制造厂家明显增多。     

Compact model generation for on-chip transmission lines

An approach for the fast and accurate generation of compact distributed circuit models for on-chip transmission lines on lossy silicon substrates is presented. Using a novel ABCD matrix partitioning procedure, accurate distributed circuit models are extracted from scattering parameters obtained from measurements and calibrated full-wave electromagnetic simulations for a small set of transmission-line geometries spanning ranges of design parameter values. A feedforward artificial neural network is trained using the extracted results, and applied to generate accurate compact models for arbitrary values within the bounds of the training ranges. Consequently, the model generation time is greatly reduced compared to conventional approaches by exploiting the interpolation capabilities of the neural network. The compact model generator is fully compatible with HSPICE and SPECTRE-RF and is easily incorporated into parasitic-aware RF circuit design and optimization tools.     

直放站天线的分类与应用

移动通信直放站是为消除移动通信网的局部范围信号盲区或弱信号区而设计的通信设备。它与基站相比有结构简单、价格低廉、安装方便等优点，通过架设直放站不但能改善覆盖效果，同时能大大减少投资成本。直放站被广泛应用于商场、停车场、机场、地铁、高速公路、体育馆等基站信号所无法到达的信号盲区，     

A power-optimal repeater insertion methodology for global interconnects in nanometer designs

This paper addresses the problem of power dissipation during the buffer insertion phase of interconnect performance optimization. It is shown that the interconnect delay is actually very shallow with respect to both the repeater size and separation close to the minimum point. A methodology is developed to calculate the repeater size and interconnect length which minimizes the total interconnect power dissipation for any given delay penalty. This methodology is used to calculate the power-optimal buffering schemes for various ITRS technology nodes for 5% delay penalty. Furthermore, this methodology is also used to quantify the relative importance of the various components of the power dissipation for power-optimal solutions for various technology nodes.     

Wafer-level packaging technology for high-Q on-chip inductors and transmission lines

In the current trend toward portable applications, high-Q integrated inductors have gained considerable importance. Hence, much effort has been spent to increase the performance of on-chip Si inductors. In this paper, wafer-level packaging (WLP) techniques have been used to integrate state-of-the-art high-Q on-chip inductors on top of a five-levels-of-metal Cu damascene back-end of line (BEOL) silicon process using 20-/spl Omega//spl middot/cm Si wafers. The inductors are realized above passivation using thick post-processed low-K dielectric benzocyclobutene (BCB) and Cu layers. For a BCB-Cu thickness of 16 /spl mu/m/10 /spl mu/m, a peak single-ended Q factor of 38 at 4.7 GHz has been measured for a 1-nH inductor with a resonance frequency of 28 GHz. Removing substrate contacts slightly increases the performance, though a more significant improvement has been obtained by combining post-processed passives with patterned ground shields: for a 2.3-nH above integrated-circuit (above-IC) inductor, a 115% increase in Q/sub BW//sup max/ (37.5 versus 17.5) and a 192% increase in resonance frequency (F/sub res/: 12 GHz versus 5 GHz) have been obtained as compared to the equivalent BEOL realization with a patterned ground shield. Next to inductors, high-quality on-chip transmission lines may be realized in the WLP layers. Losses below -0.2 dB/mm at 25 GHz have been measured for 50-/spl Omega/ post-processed coplanar-waveguide lines, above-IC thin-film microstrip lines have measured losses below -0.12 dB/mm at 25 GHz.     

Characterization and modeling of left-handed microstrip lines with application to loop antennas

This study investigates in detail the left-handed (LH) properties of the two-layer microstrip line, periodically loaded with broadside-coupled split ring resonators (BC-SRRs) and vias. The mechanism of the left-handed microstrip line (LHML), which includes the diamagnetic response, the backward-wave propagation and the proportionality of the guided wavelength on frequency, is discussed in terms of the field and current distributions and the dispersion diagram. To examine the resonance of the BC-SRR, both the full-wave eigenmode analysis and the closed-form formula based on the quasistatic approach are developed. The effects of the BC-SRR shape on the resonant frequency are evaluated. To facilitate the computer-aided-design (CAD) applications of the LHML, the equivalent-circuit model, which comprises the three-conductor coupled microstrip line for the coupling section, the series LC for the BC-SRR, and the shunt inductance for the via, is established. Good agreement among the results of the full-wave simulation, equivalent-circuit model, published data, and measurement supports the usefulness of the proposed modeling methodology and also validates the analytical expressions. The application of the LHML in the microstrip rectangular loop antenna fed by the conductor-backed coplanar waveguide-to-conductor-backed coplanar stripline (CBCPW-to-CBCPS) transition is presented to highlight the unique features of the LHML. Compared with the conventional loop antenna, the LHML-loaded loop antenna achieves a 50% area reduction and the 52% of main beam steering.     

Characterization and modeling of on-chip spiral inductors for Si RFICs

The paper presents a complete characterization of on-chip inductors fabricated in BiCMOS technology. First, a study of the scaling effect of inductance on geometry and structure parameters is presented to provide a clear guideline on inductor scaling with suitable quality factors. The substrate noise analysis and noise reduction techniques are then investigated. It is shown that floating well can improve both quality factor and noise elimination by itself under 3 GHz and together with a guard ring above 3 GHz. Finally, for accurate circuit simulations, a new inductor model is developed for predicting the skin effect and eddy effect and associated quality factor and inductance.     

A design-oriented methodology for accurate modeling of on-chip interconnects

An accurate modeling methodology for typical on-chip interconnects used in the design of high frequency digital, analog, and mixed signal systems is presented. The methodology includes the parameter extraction procedure, the equivalent circuit model selection, and mainly the determination of the minimum number of sections required in the equivalent circuit for accurate representing interconnects of certain lengths within specific frequency ranges while considering the frequency-dependent nature of the associated parameters. The modeling procedure is applied to interconnection lines up to 35 GHz obtaining good simulation-experiment correlations. In order to verify the accuracy of the obtained models in the design of integrated circuits (IC), several ring oscillators using interconnection lines with different lengths are designed and fabricated in Austriamicrosystems 0.35 μm CMOS process. The average error between the experimental and simulated operating frequency of the ring oscillators is reduced up to 2% when the interconnections are represented by the equivalent circuit model obtained by applying the proposed methodology.     

High-accuracy and low signal distortion on-chip auto-calibrating architecture for continuous-time filters

A high-accuracy on-chip auto-calibrating architecture is presented to compensate the process and temperature parameter variations in high-linearity continuous-time filter. The on-chip auto-calibrating architecture consists of a clock generating circuit, a voltage comparator, a digital tuning engine, and an analog integrator with similar time-constants as the tuned filter. Discrete capacitor arrays are utilized to tune filter automatically for preserving a high linearity. A fourth-order RC filter for GNSS receivers is fabricated in 0.18 µm CMOS process to verify the performance of proposed tuning architecture. With adjustment, this filter achieves less than 5 % frequency uncertainty. The whole circuit consumes 5.2 mA under a 1.8 V supply and occupies a die area of 0.55 mm². Both the post-layout simulation and measured results indicate that the auto-calibrating architecture is a useful and adequate solution to compensate the errors caused by factors such as fabrication tolerances, changes in operating conditions, parasitic effects and aging.     

Atto-farad measurement and modeling of on-chip coupling capacitance

A first reported method of measuring coupling capacitance (both inter- and intralevel) between any two lines in the presence of any other lines in a very large scale integration (VLSI) chip, to an accuracy of atto-farad range, is discussed. The setup simply requires dc current measurement and the method has been tested for 180 nm and 130 nm technologies. Furthermore, the method can be easily implemented for on-wafer e-test measurement in a fab, to study die-to-die and wafer-to-wafer coupling capacitance variation due to manufacturing process variation. In one process, it has been observed that the coupling capacitance between parallel lines could vary as much as 17%.     

An area model for on-chip memories and its application

An area model suitable for comparing data buffers of different organizations (e.g. caches versus register files) and arbitrary sizes is described. The area model considers the supplied bandwidth of a memory cell and includes such buffer overhead as control logic, driver logic and tag storage. The model gave less than 10% error when verified against real caches and register files. It is shown that, comparing caches and register files in terms of area for the same storage capacity, caches generally occupy more area per bit than register files for small caches because the overhead dominates the cache area at these sizes. For larger caches, the smaller storage cells in the cache provide a smaller total cache area per bit than the register set. Studying cache performance (traffic ratio) as a function of area, it is shown that, for small caches (less than the area occupied by 256 registers bits-r.b.e.-or 32 b), direct-mapped caches perform significantly better than four-way set-associative caches and, for caches of medium areas (between 256 r.b.e. and 4096 r.b.e.), both direct-mapped and set-associative caches perform better than fully associative caches     

Capacitance and inductance matrices of coupled lines from modalpowers

The capacitance and inductance matrices of a system of coupled lines are calculated from the modal powers. Knowledge of the propagation constants of the different modes, the eigencurrent matrix [M _I], and the modal powers uniquely specify the two matrices. The present approach is tested both analytically and numerically     

Statistical extraction and modeling of inductance considering spatial correlation

In this paper, we present a novel method for statistical inductance extraction and modeling for interconnects considering process variations. The new method, called statHenry, is based on the collocation-based spectral stochastic method where orthogonal polynomials are used to represent the statistical processes. The coefficients of the partial inductance orthogonal polynomial are computed via the collocation method where a fast multi-dimensional Gaussian quadrature method is applied with sparse grids. To further improve the efficiency of the proposed method, a random variable reduction scheme is used. Given the interconnect wire variation parameters, the resulting method can derive the parameterized closed form of the inductance value. We show that both partial and loop inductance variations can be significant given the width and height variations. This new approach can work with any existing inductance extraction tool to extract the variational partial and loop inductance or impedance. Experimental results show that our method is orders of magnitude faster than the Monte Carlo method for several practical interconnect structures.