Board level solder joint reliability analysis of stacked die mixed flip-chip and wirebond BGA

Stacked die BGA has recently gained popularity in telecommunication applications. However, its board level solder joint reliability during the thermal cycling test is not as well-studied as common single die BGA. In this paper, solder joint fatigue of lead-free stacked die BGA with mixed flip-chip (FC) and wirebond (WB) interconnect is analyzed in detail. 3D fatigue model is established for stacked die BGA with considerations of detailed pad design, realistic shape of solder ball, and non-linear material properties. The fatigue model applied is based on a modified Darveaux’s approach with non-linear viscoplastic analysis of solder joints. Based on the FC–WB stack die configuration, the critical solder ball is observed located between the top and bottom dice corner, and failure interface is along the top solder/pad interface. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house lead-free TFBGA46 (thin-profile fine-pitch BGA) thermal cycling test data. Subsequently, design analyzes are performed to study the effects of 20 key design variations in package dimensions, material properties, and thermal cycling test conditions. In general, thinner PCB and mold compound, thicker substrate, larger top or bottom dice sizes, thicker top die, higher solder ball standoff, larger solder mask opening, smaller PCB pad size, smaller thermal cycling temperature range, longer ramp time, and shorter dwell time contribute to longer fatigue life. SnAgCu is a common lead-free solder, and it has much better board level reliability performance than eutectic solder based on modeling results, especially low stress packages.     

Effects of Phase Change of Pb-Free Flip-Chip Solders During Board-Level Interconnect Reflow

The impact of phase change (from solid to liquid) on the reliability of Pb-free flip-chip solders during board-level interconnect reflow is investigated. Most of the current candidates for Pb-free solder are tin-based with similar melting temperatures near 230 degC. Thus, Pb-free flip-chip solders melt again during the subsequent board-level interconnect reflow cycle. Solder volume expands more than 4% during the phase change from solid to liquid. The volumetric expansion of solder in a volume constrained by chip, substrate, and underfill creates serious reliability issues. The issues include underfill fracture and delamination from chip or substrate. Besides decreasing flip-chip interconnect reliability in fatigue, bridging through underfill cracks or delamination between neighboring flip-chip interconnects by the interjected solder leads to failures. In this paper, the volume expansion ratio of tin is experimentally measured, and a Pb-free flip-chip chip-scale package (FC-CSP) is used to observe delamination and solder bridging after solder reflow. It is demonstrated that the presence of molten solder and the interfacial failure of underfill can occur during solder reflow. Accordingly, Pb-free flip-chip packages have an additional reliability issue that has not been a concern for Pb solder packages. To quantify the effect of phase change, a flip-chip chip-scale plastic ball grid array package is modeled for nonlinear finite-element analysis. A unit-cell model is used to quantify the elongation strain of underfill and stresses at the interfaces between underfill and chip or underfill and substrate generated by volume expansion of solder. In addition, the strain energy release rate of interfacial crack between chip and underfill is also calculated     

热循环条件下空洞对PBGA焊点热疲劳寿命的影响

球栅阵列(ball grid array, BGA)封装器件的广泛应用使空洞对焊点可靠性的影响成为业界关注的焦点之一.采用非线性有限元分析方法和统一型粘塑性本构方程,以PBGA组装焊点为对象,建立了互连焊点热应变损伤的三维有限元模型,并基于修正的Coffin-Manson方程,分析了在热循环加裁条件下不同位置和大小的空洞对焊点疲劳寿命的影响.研究结果显示,位于原应力集中区的空洞将降低焊点疲劳寿命,基于应变失效机理,焊点裂纹易在该类空洞周围萌生和扩展;位于焊球中心和远离原应力集中区的空洞,在一定程度上可提高焊点的疲劳寿命.     

Reliability issues for flip-chip packages

In this article, we review the reliability issues for plastic flip-chip packages, which have become an enabling technology for future packaging development. The evolution of area-array interconnects with high I/O counts and power dissipation has made thermal deformation an important reliability concern for flip-chip packages. Significant advances have been made in understanding the thermo-mechanical behavior of flip-chip packages based on recent studies using moiré interferometry. Results from moiré studies are reviewed by focusing on the role of the underfill to show how it reduces the shear strains of the solder balls but shifts the reliability concern to delamination of the underfill interfaces. The development of the high-resolution moiré interferometry based on the phase-shift technique provided a powerful method for quantitative analysis of thermal deformation and strain distribution for high-density flip-chip packages. This method has been applied to study plastic flip-chip packages and the results and impacts on delamination at the die/underfill interface and in the underfill region above the plated through-hole via are discussed. Here a related reliability problem of die cracking during packaging assembly and test is also discussed. Finally, we discuss briefly two emerging reliability issues for advanced flip-chip packages, one on the packaging effect on Cu/low k interconnect reliability and the other on electromigration of solder balls in flip-chip packages.     

Effects of Glue on the Bend Performance of Flip Chip Packages

To combat reliability margin loss in ball grid array (BGA) packages specifically in mechanical shock and vibration testing, companies are exploring the possibility of using glue and complete underfill to mitigate risk to second-level interconnects (SLI). Though glue has been demonstrated to have a positive influence on SLI reliability margin, it can have adverse affects on the rest of the package such as substrate or first-level interconnects (FLI). This paper explains details on how glue modulates the overall reliability of the package. Finite-element modeling (FEM) along with low strain rate bend tests was done to prove the effect of glue on solder joint reliability. Further, shock testing was done to demonstrate how the glue modulates the shock performance. The improvement in SLI reliability was highly dependent on the choice of glue.      

Drop impact reliability analysis of CSP packages at board and product levels through modeling approaches

Chip scale package (CSP) and fine pitch ball grid array (BGA) packages have been increasingly used in portable electronic products such as mobile cell phones and PDA, etc. Drop impact which is inevitable during its usage could cause not only housing crack but also package to board interconnect failure, such as BGA solder breaks. Various drop tests have been used to ensure high reliability performance of packaging to withstand such impact and shock load. Due to extreme difficulty in directly measuring responses in solder joint during drop shock event, computer simulation based modeling approach has been increasingly played an important role in evaluating product reliability performance during product development. An advanced modeling technique with a comprehensive failure criterion including high strain rate effect needs to be developed to quantitatively evaluate package reliability performance especially in cross comparisons between different board and system level designs. In this paper, three drop tests have been modeled, namely, bare board drop, board with fixture drop or shock, and system level phone drop. Submodeling and explicit-implicit sequential modeling techniques are used to characterize the dynamic responses of CSP/BGA packages in different board designs. Failure criteria and effects of strain rate and edge support on BGA in multicomponent boards are also investigated. A validation test with data acquisition is used to correlate the test results with numerical results.     

Effect of Size of Lid-Substrate Adhesive on Reliability of Solder Balls in Thermally Enhanced Flip Chip PBGA Packages

Six design cases of lid-substrate adhesive with various combinations of widths and heights were analyzed to investigate how the size of the adhesive affects the reliability of the solder balls of thermally enhanced flip chip plastic ball grid array (FC-PBGA) packages in thermal cycling tests. Analysis results were compared with data on the reliability of conventional FC-PBGA packages. Thermal-mechanical behavior was simulated by the finite element (FE) method and the eutectic solder was assumed to exhibit elastic-viscoplastic behavior. The temperature-dependent nonlinear stress/strain relationship of the adhesive was experimentally determined and used in the FE analysis. Darveaux's model was employed to obtain the predicted fatigue life of the solder ball. Simulation results reveal that the fatigue life of the solder balls in thermally enhanced FC-PBGA packages is much shorter than that in conventional FC-PBGA packages, and the life of solder balls increases with both the width and the height of the adhesive. However, the effect of the width of the adhesive on the reliability of the solder ball is stronger than that of the height. Moreover, increasing either the width or the height reduces the plastic strain in the adhesive at critical locations, indicating that the reliability of the adhesive can be improved by its size. The predicted results of the life of solder balls for some selected studied packages are also compared with experimental data from thermal cycling tests in the paper     

Board level solder joint reliability modeling and testing of TFBGA packages for telecommunication applications

For thin-profile fine-pitch BGA (TFBGA) packages, board level solder joint reliability during the thermal cycling test is a critical issue. In this paper, both global and local parametric 3D FEA fatigue models are established for TFBGA on board with considerations of detailed pad design, realistic shape of solder joint, and nonlinear material properties. They have the capability to predict the fatigue life of solder joint during the thermal cycling test within ±13% error. The fatigue model applied is based on a modified Darveaux’s approach with nonlinear viscoplastic analysis of solder joints. A solder joint damage model is used to establish a connection between the strain energy density (SED) per cycle obtained from the FEA model and the actual characteristic life during the thermal cycling test. For the test vehicles studied, the maximum SED is observed at the top corner of outermost diagonal solder ball. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house BGA thermal cycling test data. Subsequently, design analysis is performed to study the effects of 14 key package dimensions, material properties, and thermal cycling test condition. In general, smaller die size, higher solder ball standoff, smaller maximum solder ball diameter, bigger solder mask opening, thinner board, higher mold compound CTE, smaller thermal cycling temperature range, and depopulated array type of ball layout pattern contribute to longer fatigue life.     

Effect of the drop impact on BGA/CSP package reliability

In this study, ball grid arrays (BGAs) and chip size packages (CSPs) were evaluated with respect to their solder joint reliabilities under drop impacts. The correlation between solder joint stresses and motherboard strains was confirmed by numerical analysis, and the motherboard strains caused by the drop impacts were measured to evaluate the BGA/CSP reliability. The authors found that the stress at a solder joint differs depending on the package structure, even if the motherboard strain is the same, and that underfilling eases the motherboard strain and disperses the stress concentrated on a solder joint.     

Board level solder joint reliability analysis and optimization of pyramidal stacked die BGA packages

Due to requirements of cost-saving and miniaturization, stacked die BGA has recently gained popularity in many applications. However, its board level solder joint reliability during the thermal cycling test is not as well-studied as common single die BGA. In this paper, solder joint fatigue of wirebond stacked die BGA is analyzed in detail. 3D fatigue model is established for stacked die BGA with considerations of detailed pad design, realistic shape of solder ball, and non-linear material properties. The fatigue model applied is based on a modified Darveaux's approach with non-linear viscoplastic analysis of solder joints. The critical solder ball is observed located between the top and bottom dice corner, and failure interface is along the top solder/pad interface. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house TFBGA (thin-profile fine-pitch BGA) thermal cycling test data. Subsequently, design analyses are performed to study the effects of 16 key design variations in package dimensions, material properties, and thermal cycling test conditions. In general, smaller top and bottom dice sizes, thicker top or bottom die, thinner PCB, thicker substrate, higher solder ball standoff, larger solder mask opening size, smaller maximum ball diameter, smaller PCB pad size, smaller thermal cycling temperature range, longer ramp time, and shorter dwell time contribute to longer fatigue life. The effect of number of layers of stacked-die is also investigated. Finally, design optimization is performed based on selected critical design variables.     

Experimental and numerical analysis of BGA lead-free solder joint reliability under board-level drop impact

Board-level solder joint reliability is very critical for handheld electronic products during drop impact. In this study, board-level drop test and finite element method (FEM) are adopted to investigate failure modes and failure mechanisms of lead-free solder joint under drop impact. In order to make all ball grid array (BGA) packages on the same test board subject to the uniform stress and strain level during drop impact, a test board in round shape is designed to conduct drop tests. During these drop tests, the round printed circuit board assembly (PCBA) is suffered from a specified half-sine acceleration pulse. The dynamic responses of the PCBA under drop impact loading are measured by strain gauges and accelerometers. Locations of the failed solder joints and failure modes are examined by the dye penetration test and cross section test. While in simulation, FEM in ABAQUS software is used to study transient dynamic responses. The peeling stress which is considered as the dominant factor affecting the solder joint reliability is used to identify location of the failed solder joints. Simulation results show very good correlation with experiment measurement in terms of acceleration response and strain histories in actual drop test. Solder joint failure mechanisms are analyzed based on observation of cross section of packages and dye and pry as well. Crack occurred at intermetallic composite (IMC) interface on the package side with some brittle features. The position of maximum peeling stress in finite element analysis (FEA) coincides with the crack position in the cross section of a failed package, which validated our FEA. The analysis approach combining experiment with simulation is helpful to understand and improve solder joint reliability.     

Dependence of Flip Chip Solder Reliability on Filler Settling

Thermomechanical reliability of solder joints in flip-chip packages is usually analyzed by assuming a homogeneous underfill ignoring the settling of filler particles. However, filler settling does impact flip chip reliability. This paper reports a numerical study of the influence of filler settling on the fatigue estimation of flip-chip solder joints. In total, nine underfill materials ( 35 vol% silica filler in three epoxies with three filler settling profiles for each epoxy) are individually introduced in a 2-D finite element (FE) model to compare the thermal response of flip chip solder joints that are surrounded by the underfill. The results show that the fatigue indicators for the solder joints (inelastic shear strain increments and inelastic shear strain energy density) corresponding to a gradual, nonuniform filler profile studied in this paper can be smaller than those associated with the uniform filler profile, suggesting that certain gradual filler settling profiles in conjunction with certain resin grades may favor a longer solder fatigue lifetime. The origin of this intriguing observation is in the fact that the solder fatigue indicators are a function of the thermal mismatch among the die, substrate, solder, and underfill materials. The thermal mechanics interplayed among these materials along with a gradual filler profile may allow for minimizing thermal mismatch; and thus lead to lower fatigue indicators.      

无铅倒装焊点的热应力与湿热应力分析

板上倒装芯片（FCOB）作为一种微电子封装结构形式得到了广泛的应用。微电子塑封器件中常用的聚合物因易于吸收周围环境中的湿气而对封装本身的可靠性带来很大影响。文章采用有限元软件分析了潮湿环境下板上倒装芯片下填充料在湿敏感元件实验标准MSL-1条件下（85℃／85％RH、168h）的潮湿扩散分布,进而分别模拟计算出无铅焊点的热应力与湿热应力,并加以分析比较。论文的研究成果不仅对于塑封电子元器件在潮湿环境中的使用具有一定的指导意义,而且对于FCOB器件在实际应用中的焊点可靠性问题具有一定的参考价值。     

倒装焊SnPb焊点热循环失效和底充胶的影响

采用实验方法,确定了倒装焊SnPb焊点的热循环寿命．采用粘塑性和粘弹性材料模式描述了SnPb焊料和底充胶的力学行为,用有限元方法模拟了SnPb焊点在热循环条件下的应力应变过程．基于计算的塑性应变范围和实验的热循环寿命,确定了倒装焊SnPb焊点热循环失效Coffin-Manson经验方程的材料参数．研究表明,有底充胶倒装焊SnPb焊点的塑性应变范围比无底充胶时明显减小,热循环寿命可提高约20倍,充胶后的焊点高度对可靠性的影响变得不明显．     

The effects of underfill and its material models onthermomechanical behaviors of a flip chip package

In this paper, the effects of underfill on thermomechanical behavior of two types of flip chip packages with different bumping size and stand-off height were investigated under thermal cycling both experimentally and two-dimensional (2-D) finite element simulation. The materials inelasticity, i.e., viscoelasticity of underfill U8437-3 and viscoplasticity of 60 Sn40 Pb solder, were considered in the simulations. The results show that the use of underfill encapsulant increases tremendously (~20 times) the thermal fatigue lifetime of SnPb solder joint, weakens the effects of stand-off height on the reliability, and changes the deformation mode of the package. It was found that the thermal fatigue crack occurs in the region with maximum plastic strain range, and the Coffin-Manson type equation could then be used for both packages with and without underfill. Solder joint crack initiation occurred before delamination when using underfill with good adhesion (75 MPa) and the underfill delamination may not be a dominant failure mode in the present study. The interfacial stresses at the underfill/chip interface were calculated to analyze delamination sites, which agree with the results from acoustic image. Moreover, the effects of material models of underfill, i.e., constant elasticity (EC) and temperature dependent elasticity (ET) as well as the viscoelasticity (VE), on the thermomechanical behaviors of flip chip package were also studied in the simulation. The VE model gives comparatively large plastic strain range and large displacements in the shear direction, as well as decreased solders joint lifetime. The ET model gives similar results as the VE model and could be used instead of VE in simulations for the purpose of simplicity     

Impact of Isothermal Aging on Long-Term Reliability of Fine-Pitch Ball Grid Array Packages with Sn-Ag-Cu Solder Interconnects: Surface Finish Effects

The interaction between isothermal aging and the long-term reliability of fine-pitch ball grid array (BGA) packages with Sn-3.0Ag-0.5Cu (wt.%) solder ball interconnects was investigated. In this study, 0.4-mm fine-pitch packages with 300-μm-diameter Sn-Ag-Cu solder balls were used. Two different package substrate surface finishes were selected to compare their effects on the final solder composition, especially the effect of Ni, during thermal cycling. To study the impact on thermal performance and long-term reliability, samples were isothermally aged and thermally cycled from 0°C to 100°C with 10 min dwell time. Based on Weibull plots for each aging condition, package lifetime was reduced by approximately 44% by aging at 150°C. Aging at 100°C showed a smaller impact but similar trend. The microstructure evolution was observed during thermal aging and thermal cycling with different phase microstructure transformations between electrolytic Ni/Au and organic solderability preservative (OSP) surface finishes, focusing on the microstructure evolution near the package-side interface. Different mechanisms after aging at various conditions were observed, and their impacts on the fatigue lifetime of solder joints are discussed.     

倒装焊SnPb焊点热循环失效和底充胶的影响

采用实验方法 ,确定了倒装焊 Sn Pb焊点的热循环寿命 .采用粘塑性和粘弹性材料模式描述了 Sn Pb焊料和底充胶的力学行为 ,用有限元方法模拟了 Sn Pb焊点在热循环条件下的应力应变过程 .基于计算的塑性应变范围和实验的热循环寿命 ,确定了倒装焊 Sn Pb焊点热循环失效 Coffin- Manson经验方程的材料参数 .研究表明 ,有底充胶倒装焊 Sn Pb焊点的塑性应变范围比无底充胶时明显减小 ,热循环寿命可提高约 2 0倍 ,充胶后的焊点高度对可靠性的影响变得不明显     

Stacked solder bumping technology for improved solder joint reliability

Solder joint failure is a serious reliability concern in flip-chip and ball grid array packages of integrated-circuit chips. In current industrial practice, the solder joints take on the shape of a spherical segment. Mathematical calculations and finite element modeling have shown that hourglass-shaped solder joints would have the lowest plastic strain and stress during a temperature cycle, thus the longest lifetime. In an effort to improve solder joint reliability, we have developed a stacked solder bumping technique for fabricating triple-stacked hourglass-shaped solder joints. This solder bumping technology can easily control the solder joint shape and height. The structure of triple-stacked solder joints consists of an inner cap, middle ball and outer cap. The triple-stacked solder joints are expected to have greater compliance than conventional solder joints and are able to relax the stresses caused by the coefficient of thermal expansion mismatching between the silicon chips and substrates since it has a greater height. Furthermore, the hourglass-shaped solder joints are to have a much lower stress/strain concentration at the interface between the solder joint and the silicon die as well as at the interface between the solder joint and substrate than barrel-shaped solder joints, especially around the corners of the interfaces. In this paper, the solder bumping process is designed and joint reliability is evaluated. Mechanical tests have been carried out to characterize the adhesion strength of the solder joints. The interfaces of the solder joints are investigated by scanning electron microscopy and energy dispersive X-ray analysis. Temperature cycling results show that the triple-stacked hourglass-shaped solder joints are more reliable than the traditional spherical-shaped solder joints.     

Underfilling fine pitch BGAs

Fine pitch BGAs and chip scale packages have been developed as an alternative to direct flip chip attachment for high-density electronics. The larger solder sphere diameter and higher standoff of CSPs and fine pitch BGAs improve thermal cycle reliability while the larger pitch relaxes wiring congestion on the printed wiring board. Fine pitch BGAs and CSPs also allow rework to replace defective devices. Thermal cycle reliability has been shown to meet many consumer application requirements. However, fine pitch BGAs and CSPs have difficulty passing mechanical shock and substrate flexing tests for portable electronics applications. The fine pitch BGA used in the study was a 10 mm package with the die wire bonded. The package substrate was bismaleimide-triazine (BT) and the solder sphere diameter was 0.56 mm. Two types of underfill were examined. The first was a fast flow, snap cure underfill. This material rapidly flows under the package and can be cured in five minutes at 165°C using an in-line convection oven. The second underfill was a thermally reworkable underfill for those applications requiring device removal and replacement. The paper discusses the assembly and rework process. In addition, liquid-to-liquid thermal shock data is presented along with mechanical shock and flexing test results     

Impact of Isothermal Aging on Long-Term Reliability of Fine-Pitch Ball Grid Array Packages with Sn-Ag-Cu Solder Interconnects: Die Size Effects

The interaction between isothermal aging and long-term reliability of fine-pitch ball grid array (BGA) packages with two different die sizes was investigated. Both 5 mm × 5 mm and 10.05 mm × 10.05 mm die-attached packages with Sn-3.0Ag-0.5Cu (wt.%) solder balls were used to compare the correlation between the internal strain difference and isothermal aging on microstructural evolution during thermal cycling. To determine their long-term reliability, the samples were isothermally aged and thermally cycled from 0°C to 100°C with 10-min dwell time. Based on Weibull plots for each aging condition, the packages with large dies attached showed shorter characteristic lifetimes, because of the relatively higher stress, but showed less lifetime degradation with isothermal aging compared with the smaller die-attached samples. Microstructure analysis using orientation imaging microscopy (OIM) revealed the evolution of the microstructure during thermal cycling, showing a higher degree of recrystallization inside the bulk solder for joints that were isothermally aged and experienced higher stress. The possible mechanisms giving rise to these observations are discussed.