Transconductance degradation in VLSI devices

Experimental results from small geometry VLSI devices show that as devices are scaled, transconductance degradation occurs. This results from scaling either the length or width. A model using a mobility expression developed by Wang is used to predict transconductance in small MOS devices. Comparison between theory and experiments is excellent.     

Characterization of CMOS devices for VLSI

CMOS bulk and SOS technologies are discussed for VLSI with emphasis on static and dynamic characteristics of two-input NAND gates. Optimum performance (minimum figure of merit FM = tpdPd) is obtained for a CMOS/SOS two-input NAND gate (FO = 2, CL= 22 fF) with an electrical channel length L = 0.75 µm, channel width W = 5.0 µm, and oxide thickness Xo= 450 Å with VDD= 3.0 V, to yield tpd= 400 ps and Pd= 250 µW (tpdPd= 100 fJ) at room temperature. Bulk technology performs within a factor of 2 of SOS for tpdand Pd. CMOS technologies offer subnanosecond propagation delays, similar to ECL bipolar, at the low submilliwatt power levels of CMOS. An analytical expression for tpddescribes the performance of two-input NAND gates in terms of device modeling and fabrication parameters. Such an expression provides a hierarchial modeling approach to characterize minicells for VLSI.     

Near-field antenna measurements using nonideal measurementlocations

We introduce a near-field to far-field transformation algorithm that relaxes the usual restriction that data points be located on a plane rectangular grid. Computational complexity is O(Nlog N) where N is the number of data points. This algorithm allows efficient processing of near-field data with known probe position errors. Also, the algorithm is applicable to other measurement approaches such as plane-polar scanning, where data are collected intentionally on a nonrectangular grid     

Simulation of three-dimensional effects in VLSI devices

Two dimensional (2D) modelling of electron devices is already established as an indispensable tool for VLSI design, and a number of very sophisticated 2D device simulators have been developed. The increasing miniaturization and packing density of VLSI circuits is now boosting research activity towards three-dimensional (3D) device simulation. In this paper we present some results obtained with our prototype 3D simulator. HFIELDS-3D, and discuss some topics related to the underlying philosophy and to the implementation of a vector code, which we are now exploiting on a CRAY XMP48 machine.     

Near-field scattering measurements for determining complex targetRCS

The application of near-field scattering measurements for determining the near-zone and far-zone radar cross section (RCS) of complex targets that are both physically and electrically large is reviewed and examined in the light of recent advances in near-field measurement technology and data processing capabilities     

Near-field measurements in monomode fibres: determination of chromatic dispersion

A new dispersion measurement for monomode fibres is proposed. It is based on an elaboration of the near-field intensities at different wavelengths. The measurement is considerably simplified and the results are highly accurate.     

Closed-form physical model for VLSI bipolar devices consideringenergy transport

A closed-form physical model is reported for VLSI bipolar devices considering energy transport. Based on the model, for a base width of 810 Å, the bipolar device, biased at V_cb=2 V, has a peak electron temperature of over 700 K, which results in a 5% reduction in the collector current     

Near-field probe measurements of microwave scattering from discontinuities in planar surfaces

In microwave scattering, nonradiating fields may contribute to radiating fields by local perturbations such as geometric discontinuities or variations in impedance or electromagnetic properties. Near-field measurements of scattering bodies provide insight into these scattering mechanisms by measuring both radiated and nonradiated fields. In this research, an H-field probe measured scattering from simple discontinuities in planar bodies at frequencies between 2 and 10 GHz. Illumination of the test-body was furnished by a focused lens system with a Gaussian-like tapered beam that locally illuminated inhomogeneities on the body. Measured data and model calculations are presented for scattered H-fields near canonical discontinuities (e.g. gaps and edges in conducting planes). Calculations of the plane wave spectrum of the measured and modeled data were used to distinguish specular reflected components from surface modes. A focused beam was simulated in a finite-difference time-domain (FDTD) model with a weighted sum of plane waves. FDTD results agreed with the measured near-field data.     

Noise measurements in charge-coupled devices

Measurements of the noise levels at the output of surface and bulk channel charge-coupled devices with three-phase overlapping polysilicon electrodes are presented. Pulser noise, correlated transfer noise, shot noise, dark current noise, and electrical insertion noise at the input have been measured and studied. The dependences of the electrical insertion noise and the transfer noise on charge packet size and clock frequency are discussed in detail and the latter related to interface state densities. New schemes and input circuits for low-noise electrical insertion of the signal charge are discussed. Our measurements indicate that the noise levels due to the intrinsic noise sources (transfer and storage noise) agree with our physical understanding of the device operation. The noise levels due to the extrinsic noise sources (pulser noise and electrical insertion noise) are above the expected theoretical values.     

Robust frame synchronisation using standard VLSI synchronousinput/output devices

A robust frame synchronisation technique is proposed for serial data links which are to be implemented using standard VLSI synchronous input/output (SIO) hardware devices with a built-in 8-bit frame sync collector. This new technique uses a multiple byte marker and additional software for frame sync, and yields up to 4.6 dB improvement on noisy channels where forward error correction is used and only the SIO hardware is available     

Considerations for the development of radiation resistant devices and VLSI circuits

The impact of radiation on Very Large Scale Integration (VLSI) silicon technology is discussed with a focus on Complimentary Metal-Oxide Semiconductor (CMOS). Effects of total dose, transient radiation, single event phenomena, and neutron fluence on devices and circuits are presented. General approaches to mitigating radiation effects are put forth. With proper considerations, VLSI CMOS can be enhanced to achieve several orders-of-magnitude increase in radiation tolerance.     

Near-field analysis of a thick lens and horn combination: theoryand measurements

At millimeter-waves quasi-optical systems are commonly designed based on the Gaussian beam and thin lens approximation. The accuracy of the Gaussian beam and thin lens approximation was studied in the case of a corrugated horn and a thick Teflon lens (focal length to lens diameter ratio f/D=1.2) combination at 87 GHz. A special near-field measurement system was constructed. A large disagreement between the measured and theoretical values with the approximative method was obtained. The measurements showed that the thin lens approximation breaks down when the distance from the input beam waist to the lens is less than 1.5 D. Theoretical values obtained with a thick lens model based on ray tracing and use of exact Huygens' aperture integration principle agree well with the measurements     

Low-temperature mobility measurements on CMOS devices

The surface channel mobility of carriers in n- and p-MOS transistors fabricated in a CMOS process was accurately determined at low temperatures down to 5 K. The mobility was obtained by an accurate measurement of the inversion charge density using a split C-V technique and the conductance at low drain voltages. The split C-V technique was validated at all temperatures using a one-dimensional Poisson solver (MOSCAP) which was modified for low-temperature application. The mobility dependence on the perpendicular electric field for different substrate bias values appeared to have different temperature dependences for n- and p-channel devices. The electron mobility increased with a decrease in temperature at all gate voltages. On the other hand, the hole mobility exhibited a different temperature behavior depending upon whether the gate voltage corresponded to strong inversion or was near threshold     

Oxide charge measurements in EEPROM devices

A method to measure “on site” programmed charges in EEPROM devices is presented. Electrical AFM based techniques (Electric Force Microscopy (EFM) and Scanning Kelvin Probe Microscopy (SKPM)) are used to probe directly floating gate potentials. Both preparation and probing methods are discussed. Sample preparation to access floating gate/oxide interfaces at a few nanometers distance without discharging the data reveals to be the key point, more than the probing technique itself.     

Use of solid-state devices in noise measurements

For accurate noise measurements the use of valves in preamplifiers has its advantages and disadvantages. Analysis in this paper shows that a combination of the bipolar and unipolar transistors offers a very satisfactory substitute for the valve in low noise preamplifiers for operation over a wide range of source resistances (10ω—1 Mω).     

VLSI?are smaller devices and more complex chips mutually exclusive?

It is suggested that the exploitation of complex silicon chips incorporating submicrometre devices will require the use of highly structured architecture, such as systolic arrays, with maximum exphasis on `nearest-neighbour? interconnections.     

Surface conduction in short-channel MOS devices as a limitation to VLSI scaling

In MOS VLSI device scaling, two major limiting mechanisms are the punchthrough and source-drain breakdown. The punchthrough mechanism is generally considered a bulk-dominated effect. Drain-source avalanche breakdown is generally attributed to bipolar transistor action between drain and source, dominated by injection through the neutral substrate region. The present work includes an experimental verification and a qualitative model demonstrating that both punchthrough and drain-source avalanche breakdown limitations are surface and surface-depletion-region dominated mechanisms, respectively. The two mechanisms are treated simultaneously since both involve enhanced injection from the source due to drain-induced source-potential barrier lowering. The experimental verification is done over a wide range of relevant device parameters, channel implant concentration between 5 × 10¹⁴-1 × 10¹⁶cm^-3for punchthrough and 2 × 10¹⁵-5 × 10¹⁶cm^-3for drain-source avalanche breakdown, effective channel length of 1.0-30.0 µm for both mechanisms.     

Motion-sensor fusion-based gesture recognition and its VLSI architecture design for mobile devices

With the rapid proliferation of smartphones and tablets, various embedded sensors are incorporated into these platforms to enable multimodal human–computer interfaces. Gesture recognition, as an intuitive interaction approach, has been extensively explored in the mobile computing community. However, most gesture recognition implementations by now are all user-dependent and only rely on accelerometer. In order to achieve competitive accuracy, users are required to hold the devices in predefined manner during the operation. In this paper, a high-accuracy human gesture recognition system is proposed based on multiple motion sensor fusion. Furthermore, to reduce the energy overhead resulted from frequent sensor sampling and data processing, a high energy-efficient VLSI architecture implemented on a Xilinx Virtex-5 FPGA board is also proposed. Compared with the pure software implementation, approximately 45 times speed-up is achieved while operating at 20 MHz. The experiments show that the average accuracy for 10 gestures achieves 93.98% for user-independent case and 96.14% for user-dependent case when subjects hold the device randomly during completing the specified gestures. Although a few percent lower than the conventional best result, it still provides competitive accuracy acceptable for practical usage. Most importantly, the proposed system allows users to hold the device randomly during operating the predefined gestures, which substantially enhances the user experience.     

Defect size variations and their effect on the critical area of VLSI devices

The effect on VLSI device yield of variations in the size of defects has not been widely recognized until recently, when the theory of critical areas and fault probabilities was developed. It is shown that assumptions regarding the defect size distribution can substantially affect the computed critical area.