集成电路版图的电路提取

集成电路版图提取为精确估计电路性能提供了可靠的手段。主要介绍了版图电路提取的各种方法及其优缺点。最后,着重介绍了一种新的层次式版图电路提取方法。     

集成电路μpc1366C工作原理

μPC 1366C为黑白电视机图象中放集成电路,内部包含95个三极管、120个电阻,一个电容和20个二极管,它具有增益高,抗干扰性能好,外围元件少等优点.该集成电路由四级中放、同步检波、预视放、消噪电路、IFAGC和RFAGC等组成,如图1所示.     

GaAs单片微波集成电路的制作工艺

GaAs单片微波集成电路工艺属于分立GaAs MESFET工艺的进一步发展。描述了GaAs制作工艺,它为微波电路设计师提供了制作所有元件的能力,其中包括MESFET、电阻、电容、电感和完整的背面接地连接。以2～12GHz单片放大器为例说明了这些元件的集成。     

辐照诱发闭锁现象的分布模型

我们用集总模型方法确定了复杂集成电路中的三维效应,电路的闭锁行为往往是受三维效应支配的。我们采用了一种预处理程序,该程序能根据对电路局部结构布局和物理的基本描述,自动地生成与SPICE程序相容的、元件数多达数千个的文件。模型的结果表明,对于非对称布局的器件来说,衬底和隔离阱中的内部电位降比由金属化层电阻引起的电位降要大得多。模型分析还表明,改变背面接触(例如部分地除去电路中间部分的背面接触,以进行激光背面模拟)可使衬底中的横向电压降提高一个数量级以上,从而显著地改变闭锁特性。我们的模型可用来计算对闭锁现象和闭锁窗口效应都具有重要影响的分布电位;在采用激光模拟的情况下,还可用术确定金属遮挡或非均匀载流子产生所造成的影响。     

电视机场扫描块μPC1031H2常见故障的快速判断检修法

μPC 1031 H2的外围电路有多种,图1所示的μPC 1031 H2外围电路是最常见的一种。本文介绍的维修程序,列举的各项参数均以此图为例。对于其它类型的外围电路也可作为参考。图中给出了μPC1031H2集成电路的名脚功能。附表提供了该集成电路各脚的电压、电流及电阻的参数。表中数据是用500型     

一种开关电阻调制方法及其应用

本文提出了一种基于开关与电阻串联的调制方法,通过适当的电路连接方式并以一定的方式控制开关的通断,可以产生所需要的等效电阻.从能量等效的角度给出了开关电阻支路等效电阻的计算方法.以反相放大器和跟踪滤波器为例,给出了开关电阻调制方法在电路中的应用.本文的讨论可供从事电路教学的教师参考.     

超声楔键合过程界面接合部演化规律研究

超声引线楔键合是集成电路芯片内部电路与外部电路实现功率与信号联通的重要互连工艺.键合参数对键合点连接质量有重要影响.运用化学腐蚀方法,全面考察键合点外观及接合部特征与键合参数之间的关系.实验结果表明:随着超声功率的增加,接头接合部形貌由椭圆形变为圆形,有效连接部位由键合点周边向中心扩展以致达到整个界面.从变形能的角度解释了接头界面形成特点的本质.     

CMOS与非门振荡器原理及应用（一）

CMOS与非门是数字集成电路中最基本的电路之一,由CMOS与非门集成电路配以适当电阻、电容组成的各种振荡器,有着十分广泛的用途。本文着重介绍几种常见振荡器的原理及其应用。     

负电阻及其串并联电路连接

负电阻不是实际存在的电路器件,但它可以通过运放和其它电路元件来实现。本文给出了负电阻的实现方法,讨论了负电阻和负电阻的串并联连接以及负电阻和正电阻的串并联连接,给出了运算放大器工作于线性区的条件。在存在负电阻的电阻串并联等效变换中,负电阻的处理方法与正电阻一致。     

SPICE-Ⅱ程序在集成电路设计中的应用

在众多的电路模拟程序中,通用电路分析程序SPICE-Ⅱ已经在国际上得到广泛的应用.就国内而言,该程序的权威性更为明显,许多从事集成电路研究和生产,并拥有大型计算机的单位都先后装配了SPICE-ⅡG版本.现在的问题是怎样使这些程序充分发挥其作用.本文主要讨论应用SPICE-Ⅱ程序进行集成电路各项性能的模拟分析和最佳设计的方法.     

A time-domain full-wave extraction method of frequency-dependentequivalent circuit parameters of multiconductor interconnection lines

A time-domain full-wave method for the extraction of frequency-dependent equivalent circuit parameters of multiconductor interconnection lines is presented in this paper. The circuit parameters extracted by this method can be inserted into circuit simulation software to investigate time-domain responses of a high-speed IC system with multiconductor interconnects. Because the definitions of the voltage and the current are not unique in full-wave analysis, transformation among circuit parameters according to different definitions of the voltage and current is also presented. The method is based on the finite-difference time-domain (FDTD) method, and the reliability of this method is illustrated by its application to representative problems     

An efficient crosstalk parameter extraction method for high-speedinterconnection lines

A proposal is presented for an effective extraction method for crosstalk model parameters of high-speed interconnection lines. In the extraction procedure, mutual capacitance and mutual inductance of the coupled interconnection lines are extracted based on S-parameter measurement, time-domain-reflectometry (TDR) measurement and subsequent microwave network analysis. The extraction method is useful for characterizing homogeneous guiding structures, where the propagation of coupled transverse electromagnetic (TEM) modes is supported. In contrast to previous extraction methods, the suggested procedure requires fewer on-wafer probing steps and does not need matched terminations in the test device for high-frequency probing. The extracted models can be readily used with simulation program with integrated circuit emphasis (SPICE) circuit simulation. The procedure can also be used for modeling the crosstalk in packaging structures and multichip modules (MCMs). The proposed procedure has been successfully applied to the crosstalk model extraction of on-chip interconnection lines. Crosstalk model parameters were obtained for different line structures, spaces, and widths. Finally, the validity and reliability of the extracted models were examined by comparing a SPICE circuit simulation using the extracted crosstalk model parameters with high-speed time-domain crosstalk measurement. A close agreement was observed in the amplitude and pulse shape between the simulation and the measurement, showing the accuracy and usefulness of the proposed extraction method     

Driver IC and COG Package Design

This paper investigates the interconnection between the driver integrated circuit (IC) and glass substrate via anisotropic conductive adhesive (ACF) of chip on glass package. The conductive particle deformation is evaluated using a novel method, optical microscope (OM) inspection. The proposed method is more convenient than the traditional approach using scanning electron microscopy applied in the manufacturing process. Interconnection performance is easily judged using OM, allowing poor interconnection between the driver IC and glass substrate to be screened out. Several types of driver ICs with different bump area ratios (total input bump area/total output bump area, input/output ratio) and length/width (L/W) ratios are designed in this experiment. The conductive particle deformations are investigated in this study. Driver ICs with L/W ratios larger than 15 have better conductive particle deformation uniformity at each position. The average deformation degree at the driver IC center position is larger than that at the side and edge positions. The deformation degree at the input position with a smaller bump area is better than that at the output position. The conductive resistance increases with the reliability testing time because of the thermal stress effect and softening of the ACF polymer material. The deformation degree is related to the conductive resistance of the interconnection. The conductive resistance is lower at the center and input positions with larger deformation degree.     

A design-oriented methodology for accurate modeling of on-chip interconnects

An accurate modeling methodology for typical on-chip interconnects used in the design of high frequency digital, analog, and mixed signal systems is presented. The methodology includes the parameter extraction procedure, the equivalent circuit model selection, and mainly the determination of the minimum number of sections required in the equivalent circuit for accurate representing interconnects of certain lengths within specific frequency ranges while considering the frequency-dependent nature of the associated parameters. The modeling procedure is applied to interconnection lines up to 35 GHz obtaining good simulation-experiment correlations. In order to verify the accuracy of the obtained models in the design of integrated circuits (IC), several ring oscillators using interconnection lines with different lengths are designed and fabricated in Austriamicrosystems 0.35 μm CMOS process. The average error between the experimental and simulated operating frequency of the ring oscillators is reduced up to 2% when the interconnections are represented by the equivalent circuit model obtained by applying the proposed methodology.     

印制电路板设计与工艺对信号完整性的影响

信号完整性问题是高速数字系统的研究重点,其主要形式有反射、串扰与电磁干扰等。影响信号完整性的物理互连层包括集成电路、芯片封装、印制电路板和系统级连接四个部分,芯片和印制电路板是当前信号完整性研究的主要对象。本文主要阐述了印制电路板设计和工艺对信号完整性的影响。     

A simplified synthesis of transmission lines with a tree structure

The limiting factor for high-performance systems is being set by interconnection delay rather than transistor switching speed. The advances in circuits speed and density are placing increasing demands on the performance of interconnections, for example chip-to-chip interconnection on multichip modules. To address this extremely important and timely research area, we analyze in this paper the circuit property of a generic distributedRLC tree which models interconnections in high-speed IC chips. The presented result can be used to calculate the waveform and delay in anRLC tree. The result on theRLC tree is then extended to the case of a tree consisting of transmission lines. Based on an analytical approach a two-pole circuit approximation is presented to provide a closed form solution. The approximation reveals the relationship between circuit performance and the design parameters which is essential to IC layout designs. A simplified formula is derived to evaluate the performance of VLSI layout.     

A new parameter extraction technique for small-signal equivalentcircuit of polysilicon emitter bipolar transistors

We propose a new parameter extraction method for advanced polysilicon emitter bipolar transistors. This method is based on the predetermination of equivalent circuit parameters using the analytical expressions of de-embedded Z-parameters of these devices. These parameter values are used as initial values for the parameter extraction process using optimization. The entire device equivalent circuit, containing RF probe pad and interconnection circuit parameters extracted by test structures, is optimized to fit measured S-parameters for eliminating de-embedding errors due to the imperfection of pad and interconnection test structures. The equivalent circuit determined by this method shows excellent agreement with the measured S-parameters from 0.1 to 26.5 GHz     

An overview of electrical characterization techniques and theory for IC packages and interconnects

This paper reviews current approaches to the electrical characterization and modeling of IC packages and interconnects. An overview of both frequency and time-domain measurement methods and summaries of equivalent circuit model selection and extraction methodologies are included. Additionally, an overview of numerical methods for electromagnetic modeling is included for completeness. Finally, relevant case studies from the literature are summarized to further supplement the discussed techniques. The focus is primarily on high-frequency signal related characterization and power integrity issues are not directly considered in this paper. This paper is presented in the context of the growing requirement for package and interconnection electrical models for high-speed and miniaturized systems.     

A technology-independent approach to custom analog cell generation

STAT (schematic to artwork transistor), a set of software tools designed to generate full-custom layouts of analog cells from arbitrary schematic topologies in any IC technology, is described. The system enables the circuit designer to annotate the schematic with component matching and symmetry relationships. Software subroutines are then used to generate device artwork. The placement program implements algorithms in which groups of related components are placed first so that annotated layout constraints are preserved. A novel placement method is offered which recognizes that analog schematic topologies often reflect desirable layout configurations. A flexible multilayer cell-level router has been developed to complete the device interconnection. The STAT system functions in either a polygon or symbolic layout environment. The symbolic layout allows design-rule and technology changes to be made easily and is designed to interface with a commercial compaction program to produce the final layout     

IC封装中互连线信号完整性的研究

随着电子芯片向着高密度、高频率和小体积化方向发展,IC封装的结构尺寸及其互连线系统在信号完整性、损耗等多方面影响着整个电路系统的可靠性。因此,对IC封装及其互连线电特性的分析显得尤为重要。文章以四列直插芯片封装外壳模型为设计实例,利用AnsoftQ3D软件提取了该封装模型的寄生电阻、电容和电感（RCL）,并结合Mult...