Short-term frequency stability of clock generators for multigigahertz rapid-single-flux quantum digital circuits

Superconducting digital systems based on Josephson junctions have generally used a synchronous timing strategy. A master clock signal is used to delimit a data window during which the system changes state and data is transferred from one block to the next. The temporal stability of the clock signal has a profound effect on the performance of rapid single flux quantum (RSFQ) digital systems. In particular, short-term clock fluctuations, or clock jitter, can degrade system performance due to the hazard of timing constraint violations. The successful development of large-scale RSFQ digital systems will require highly stable multigigahertz on-chip clock sources. To meet this need, methods for characterizing and measuring the short-term stability of such sources are required. We identify the relevant figure of merit to characterize and compare various clocks: the cycle-to-cycle standard deviation of the clock periods. We present experimental techniques for the measurement of this figure of merit and apply them to the measurement of jitter in a clock generator used often in RSFQ systems, the ring oscillator. High-frequency phase noise measurements found the jitter of a 9.6-GHz clock to be in the range from 0.6% to 0.36% of the clock period. The measured values of clock jitter fell within the 95% confidence interval of our stochastic circuit simulations. This was sufficient evidence to conclude that thermal noise from the resistors in the circuit may be the dominant source of jitter in the ring oscillator.     

Phase Noise and Jitter in CMOS Ring Oscillators

A simple, physically based analysis illustrate the noise processes in CMOS inverter-based and differential ring oscillators. A time-domain jitter calculation method is used to analyze the effects of white noise, while random VCO modulation most straightforwardly accounts for flicker ($1/f$) noise. Analysis shows that in differential ring oscillators, white noise in the differential pairs dominates the jitter and phase noise, whereas the phase noise due to flicker noise arises mainly from the tail current control circuit. This is validated by simulation and measurement. Straightforward expressions for period jitter and phase noise enable manual design of a ring oscillator to specifications, and guide the choice between ring and LC oscillator.     

Energy per logic operation in integrated circuits: definition and determination

A figure of merit for the comparison of different types of logic circuits on the basis of inverters is presented. This figure of merit-the minimum energy per logic operation-is equal to the product of the time period necessary for carrying out a logic operation times the power which is fed into the inverter during this time period. Methods for the determination of these terms by ring oscillator measurements and model calculations are considered. In contrast to the so-called `delay-power' product, these newly defined terms are independent of the kind of measurement, as for example the number of stages of the ring oscillator. Thus the minimum energy per logic operation is an intrinsic figure of merit which allows a qualitative comparison of different types of logic circuits on a physical basis.     

Jitter and phase noise in ring oscillators

A companion analysis of clock jitter and phase noise of single-ended and differential ring oscillators is presented. The impulse sensitivity functions are used to derive expressions for the jitter and phase noise of ring oscillators. The effect of the number of stages, power dissipation, frequency of oscillation, and short-channel effects on the jitter and phase noise of ring oscillators is analyzed. Jitter and phase noise due to substrate and supply noise is discussed, and the effect of symmetry on the upconversion of 1/f noise is demonstrated. Several new design insights are given for low jitter/phase-noise design. Good agreement between theory and measurements is observed     

面向5GHz无线应用的单片InGaP/GaAs HBT压控振荡器

介绍了一种由商用InGaP/GaAs异质结双极晶体管工艺制成、基于负阻原理的单片压控振荡器,此电路定位于5GHz频段下的无线应用.在实际使用中,除了旁路和去耦电容外,无需外接其他外部元件.测试得到的输出频率范围超过300MHz,为4.17～4.56GHz,与仿真结果非常吻合;相位噪声为-112dBc/Hz@1MHz;在3.3V电源电压下,其核心部分的直流功耗为15.5mW,输出功率为0～2dBm.为了与其他振荡器比较,还通过计算得到了相位噪声优值,约为-173.2dBc/Hz.同时,还讨论了负阻振荡器的原理和设计方法.     

面向5GHz无线应用的单片InGaP/GaAs HBT压控振荡器

介绍了一种由商用InGaP/GaAs异质结双极晶体管工艺制成、基于负阻原理的单片压控振荡器,此电路定位于5GHz频段下的无线应用.在实际使用中,除了旁路和去耦电容外,无需外接其他外部元件.测试得到的输出频率范围超过300MHz,为4.17～4.56GHz,与仿真结果非常吻合;相位噪声为-112dBc/Hz@1MHz;在3.3V电源电压下,其核心部分的直流功耗为15.5mW,输出功率为0～2dBm.为了与其他振荡器比较,还通过计算得到了相位噪声优值,约为-173.2dBc/Hz.同时,还讨论了负阻振荡器的原理和设计方法.     

A low jitter, low spur multiphase phase-locked loop for an IR-UWB receiver

A low jitter,low spur multiphase phase-locked loop(PLL) for an impulse radio ultra-wideband(IR-UWB) receiver is presented.The PLL is based on a ring oscillator in order to simultaneously meet the jitter requirement, low power consumption and multiphase clock output.In this design,a noise and matching improved voltage-controlled oscillator(VCO) is devised to enhance the timing accuracy and phase noise performance of multiphase clocks.By good matching achieved in the charge pump and careful choice of the l...     

Jitter characteristics of an on-chip voltage reference-locked time-to-digital converter

The noise and jitter characteristics of an on-chip voltage reference-locked ring oscillator used in the time-to-digital converter (TDC) of the integrated receiver of a pulsed time-of-flight laser rangefinder are presented. The frequency of the ring oscillator, 683 MHz, was locked to the on-chip voltage reference by means of a frequency-to-voltage converter, resulting in better than 90 ppm/°C stability. The noise and jitter transfer characteristics of the loop were derived, and simulations were performed to see the effects of different noise types (white and 1/f noise) on the cumulative jitter of the locked ring oscillator. Finally, these results were verified by jitter measurements performed using an integrated time-to-digital converter (TDC) fabricated on the same die (0.18 μm CMOS process). The cumulative jitter of the on-chip reference-locked ring oscillator was less than 30 ps (sigma value) over a time range of 70 ns, which made it possible to use this oscillator as the heart of a TDC when aiming at centimetre-level precision (1 cm = 67 ps) in laser ranging.     

Novel last passage time based jitter model with application to low slew rate/high noise ring oscillator

In a ring oscillator, the behaviour in which the output voltage ramp (up/down) of its individual delay cell crosses the threshold, which triggers the next stage delay cell, is crucial in determining the timing jitter, and hence phase noise. Specifically, as the slew rate of the ramp decreases and/or the amount of noise contribution from the transistors in the delay cell increases, the voltage ramp (up or down) has a higher probability of crossing the threshold multiple times, before finally passing it at a time denoted as last passage time, which is more accurate than the conventional first passage time model. This multiple crossing results in a higher jitter. In the past, investigation in last passage time jitter model results in jitter expression that can only be calculated numerically and thus no design guidelines/insights are apparent. In this paper, a novel model is presented with a simple closed form formula, which shows the extra jitter, due to multiple crossing, adds a term that increases as a function of the fourth power of the noise strength/slew rate ratio. The formula is applied to a real life practical low slow rate/high noise ring oscillator which finds application, for example, in random number generator implementation. Corresponding transistor level simulation results agree reasonably well with the model. Furthermore, it is shown that, on example designs, the last passage time approach in this paper can lead to time jitter that is 100 % larger than that due to conventional first passage time model.     

Computing Timing Jitter From Phase Noise Spectra for Oscillators and Phase-Locked Loops With White and$1/f$Noise

Phase noise and timing jitter in oscillators and phase-locked loops (PLLs) are of major concern in wireless and optical communications. In this paper, a unified analysis of the relationships between time-domain jitter and various spectral characterizations of phase noise is first presented. Several notions of phase noise spectra are considered, in particular, the power-spectral density (PSD) of the excess phase noise, the PSD of the signal generated by a noisy oscillator/PLL, and the so-called single-sideband (SSB) phase noise spectrum. We investigate the origins of these phase noise spectra and discuss their mathematical soundness. A simple equation relating the variance of timing jitter to the phase noise spectrum is derived and its mathematical validity is analyzed. Then, practical results on computing jitter from spectral phase noise characteristics for oscillators and PLLs with both white (thermal, shot) and$bf 1/f$noise are presented. We are able to obtain analytical timing jitter results for free-running oscillators and first-order PLLs. A numerical procedure is used for higher order PLLs. The phase noise spectrum needed for computing jitter may be obtained from analytical phase noise models, oscillator or PLL noise analysis in a circuit simulator, or from actual measurements.     

4.9-GHz low-phase-noise transformer-based superharmonic-coupled GaInP/GaAs HBT QVCO

The low-phase-noise GaInP/GaAs heterojunction bipolar transistor (HBT) quadrature voltage controlled oscillator (QVCO) using transformer-based superharmonic coupling topology is demonstrated for the first time. The fully integrated QVCO at 4.87GHz has phase noise of -131dBc/Hz at 1-MHz offset frequency, output power of -4dBm and the figure of merit (FOM) -198dBc/Hz. The state-of-the-art phase noise FOM is attributed to the superior GaInP/GaAs HBT low-frequency device noise and the high quality transformer formed on the GaAs semi-insulating substrate.     

A figure of merit for the high-frequency noise behavior of bipolartransistors

In this paper a new figure of merit for high frequency noise behavior for use in the evaluation and development of bipolar silicon process technology is introduced. Basic low noise design rules for optimum transistor biasing and emitter scaling are proposed     

Low Phase-Noise and Low-Power CMOS VCO Constructed in Current-Reused Configuration

A Ku-band CMOS voltage-controlled oscillator (VCO) constructed in a modified current-reused configuration is presented in this letter. Two dc level shifters combined into two metal-insulator-metal capacitors are adopted to solve the transconductance and load mismatch problems of the conventional current-reused VCO for obtaining more symmetrical oscillation signals and lowering the phase noise of oscillator. A prototype was designed and measured to verify the design concept. The measurement results demonstrate the central oscillation signal of 16 GHz to be associated with the 900 MHz tuning range and -111 dBc/Hz phase noise at 1 MHz offset. The power consumption of the VCO core is only 8.1 mW. The measurement result evaluated by means of a figure of merit is about -186.8 dBc/Hz.     

Low Noise Wide Tuning Range Quadrature Ring Oscillator for Multi-Standard Transceiver

This letter presents a low phase noise quadrature ring oscillator with new start-up circuit. The oscillator architecture is a two-stage differential ring with an additional pair of transition-assistance transistors. The circuit was implemented in 0.18 $mu{rm m}$ CMOS technology and the measured tuning range of the prototype device is from 1.7 GHz to 5.5 GHz and figure of merit (FOM) is ${- 162}~{rm dB}$. The proposed area of application is the core of the local oscillator in a multi-standard wireless transceiver.      

A 6 GHz high power and low phase noise VCO using an InGaP/GaAs HBT

A 6 GHz voltage controlled oscillator (VCO) optimized for power and noise performance was designed and characterized. This VCO was designed with the negative-resistance (Neg-R) method, utilizing an InGaP/GaAs hetero-junction bipolar transistor in the negative-resistance block. A proper output matching network and a high Q stripe line resonator were used to enhance output power and depress phase noise. Measured central frequency of the VCO was 6.008 GHz. The tuning range was more than 200 MHz. At the central frequency, an output power of 9.8 dBm and phase noise of -122.33 dBc/Hz at 1 MHz offset were achieved, the calculated RF to DC efficiency was about 14%, and the figure of merit was -179.2 dBc/Hz.     

RF Oscillator Based on a Passive RC Bandpass Filter

A passive RC bandpass filter (BPF) based voltage-controlled-oscillator (VCO) operating at 2.5 GHz is presented. In GHz frequency range, a preferred type of an oscillator is either an LC oscillator or a ring oscillator. An LC oscillator exhibits an excellent phase noise performance while its fabrication cost is expensive due to the inductors. On the other hand, a ring oscillator can be built with standard CMOS devices resulting in a cheap fabrication cost. However, it has a poor phase noise and jitter performance and is sensitive to power supply noise. This paper proposes a RC BPF-based oscillator. Its property is closer to a LC oscillator rather than a ring oscillator and, as a result, improves the jitter performance due to power supply noise. Also, it can be fabricated in a standard CMOS process since there is no inductor. To prove the proposed concept, a RC BPF-based oscillator was designed and fabricated in a standard 0.13-$mu{hbox {m}}$ CMOS technology. An operating frequency of 2.5 GHz and phase noise of $-$ 95.4 dBc/Hz at 1$~$MHz offset was measured. Power consumption was 2.86 mW from a 1.3$~$ V supply voltage.      

一种低噪声CMOS差分环型压控振荡器的设计和分析

设计和分析了一种高稳定性,宽频带范围,低噪声的差分环型压控振荡器.该电路具有较低的压控增益,较好的线性范围,较低的相位噪声.应用复制偏置电路,对差分环型压控振荡器的控制电压进行复制,以提高对环型压控振荡器电源电压噪声和衬底噪声的抑制.采用0.6 tanCMOS工艺进行模拟仿真,当控制电压从1 V到3.2 V变化时,相应的振荡频率为130 MHz到740 MHz;在偏离中心频率100 kHz,1 MHz频率处的相位噪声为-89 dBc,-110 dBc.     

An On-chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators

A technique for reducing the supply voltage sensitivity of a ring oscillator using on-chip calibration is described. A 1-V 0.13-mum CMOS PLL demonstrates robust performance against VCO supply noise over operating frequencies of 0.5 to 2 GHz. In the presence of a 10-mV 1-MHz VCO supply noise, the measured rms jitter of the proposed PLL with on-chip calibration is 3.95 ps at a 1.4-GHz operating frequency, while a conventional design measures 8.22 ps rms jitter. For 10-MHz VCO supply noise, the measured rms jitter is improved from 16.8 ps to 3.97 ps. The total power consumption of the PLL is 9.6 mW at 1.4 GHz, and the combined core die area of the PLL and the calibration circuitry is 0.064 mm²     

Minimizing the Supply Sensitivity of a CMOS Ring Oscillator Through Jointly Biasing the Supply and Control Voltages

A method to minimize the supply sensitivity of a CMOS ring oscillator is proposed through joint biasing of the supply and the control voltage. The technique can supplement a number of common supply rejection techniques and can be exploited to compensate for the noise coupling caused by the parasitic capacitance in the loop filter of a phase-locked loop (PLL). The proposed CMOS ring oscillator is designed and implemented with a charge-pump based PLL in 65-nm technology to demonstrate the robustness against the supply fluctuation. Taking advantage of the negative static supply sensitivity of the ring oscillator with proper combination of the bias voltages, the rms jitter of the 5.12-GHz output clock is reduced from 6.41 ps to 2.38 ps while subject to supply noise at 90 MHz.