Multilevel Inverter For Grid-Connected PV System Employing Digital PI Controller

This paper presents a single-phase five-level photovoltaic (PV) inverter topology for grid-connected PV systems with a novel pulsewidth-modulated (PWM) control scheme. Two reference signals identical to each other with an offset equivalent to the amplitude of the triangular carrier signal were used to generate PWM signals for the switches. A digital proportional-integral current control algorithm is implemented in DSP TMS320F2812 to keep the current injected into the grid sinusoidal and to have high dynamic performance with rapidly changing atmospheric conditions. The inverter offers much less total harmonic distortion and can operate at near-unity power factor. The proposed system is verified through simulation and is implemented in a prototype, and the experimental results are compared with that with the conventional single-phase three-level grid-connected PWM inverter.     

A new single-phase five-level PWM inverter employing a deadbeat control scheme

A single-phase five-level PWM inverter is presented to alleviate harmonic components of the output voltage and the load current. Operational principles with switching functions are analyzed. To keep the output voltage sinusoidal and to have the high dynamic performances even in the cases of load variations and the partial magnetization in filter inductor, the deadbeat controller is designed and implemented on a prototype. The validity of the proposed inverter is verified through simulation and experiments. To assess the proposed inverter, it is compared with the conventional single-phase three-level PWM inverter under the conditions of identical supply DC voltage and switching frequency. In addition, it is compared with the five-level cascaded PWM inverter.     

Advanced Control and Analysis of Cascaded Multilevel Converters Based on P-Q Compensation

This paper introduces new controls for the cascaded multilevel power converter. This converter is also sometimes referred to as a ldquohybrid converterrdquo since it splits high-voltage/low-frequency and low-voltage/pulsewidth-modulation (PWM)-frequency power production between ldquobulkrdquo and ldquoconditioningrdquo converters respectively. Cascaded multilevel converters achieve higher power quality with a given switch count when compared to traditional multilevel converters. This is a particularly favorable option for high power and high performance applications such as naval ship propulsion. This paper first presents a new control method for the topology using three-level bulk and conditioning inverters connected in series through a three-phase load. This control avoids PWM frequency switching in the bulk inverter. The conditioning inverter uses a capacitor source and its control is based on compensating the real and reactive (P-Q) power difference between the bulk inverter and the load. The new control explicitly commands power into the conditioning inverter so that its capacitor voltage remains constant. A unique space vector analysis of hybrid converter modulation is introduced to quantitatively determine operating limitations. The conclusion is then generalized for all types of controls of the hybrid multilevel converters (involving three-level converter cells). The proposed control methods and analytical conclusions are verified by simulation and laboratory measurements.     

基于脉冲阶梯调制的级联型逆变器研究

脉冲阶梯调制(PSM)是将脉宽调制(PWM)与阶梯调制(SM)相结合,起初应用在高压直流电源系统中。将脉冲阶梯调制技术应用到逆变器领域,提出了基于脉冲阶梯调制的级联型逆变器。介绍了级联逆变器的基本拓扑,分析了PSM级联型逆变器的工作原理,研究了PSM的调制算法。该级联型逆变器具有电路结构简单、控制方法简便、开关损耗小、效率高等优点,适合高压大功率场合。建立了6模块的PSM级联型高压逆变器(可获得有效值为4 kV的输出电压)的Matlab仿真模型进行分析,给出仿真结果。仿真结果表明,PSM级联型高压逆变器的输出波形特性好,谐波含量和THD均很小。     

Optimal PWM design for high power three-level inverter throughcomparative studies

Comparative studies between harmonic elimination and optimal PWM strategies are given for high power three-level inverter feeding an induction motor. An effective PWM map construction method based on the valid region on the frequency modulation index plane is suggested. Thereby, an optimal map including asynchronous space vector PWM, harmonic elimination and optimal PWM method is generated covering all of the low, middle and high modulation index regions. The PWM map was designed for 1 MVA rated general purpose GTO inverter and implemented with a digital signal processor. Experimental results are presented for 10 kVA prototype     

Topological and Modulation Design of Three-Level Z-Source Inverters

This paper presents the development of two three- level cascaded Z-source inverters, whose output voltage can be stepped down or up unlike a traditional buck three-level inverter. The proposed inverters are designed using two three-phase voltage-source inverter bridges, supplied by two uniquely designed Z-source impedance networks. These three-phase bridges can either be cascaded at their dc sides to form a dc-link-cascaded Z-source inverter or at their ac outputs using single-phase transformers to form a dual Z-source inverter. The dc-link-cascaded inverter has the advantages of not using any clamping diodes and transformers, but does not have redundant switching states within a phase leg for equalizing switching losses among the power devices. This constraint limits the modulation options for the dc-link-cascaded inverter, and indeed, it can only be controlled using the modified carrier disposition technique with appropriate “Z-source shoot-through” states inserted for achieving balanced voltage boosting and optimal “nearest-three-vectors” switching. On the other hand, the dual Z-source inverter with transformer isolation can be controlled using different modulation approaches due to the presence of redundant switching states within a phase leg. Particularly, using a modified phase-shifted-carrier (PSC) scheme with shoot-through states inserted, it is shown that the dual inverter can be implemented using only a single Z-source network, while still achieving the correct volt-sec average and switching loss equalization. This represents a significant reduction in cost, and can more than compensate for the slightly degraded spectral characteristics of the PSC scheme. To verify the theoretical concepts discussed, experimental testing has been performed with the captured results presented in a later section of the paper.      

New inverter output filter topology for PWM motor drives

This paper presents a new inverter output filter topology for pulse width modulation (PWM) motor drives. It is shown that the proposed filter effectively reduces high frequency harmonics which can cause serious damage to the motor bearings and insulation. The proposed filter is comprised of a conventional resistance, inductance, capacitance (RLC) network cascaded with an LC trap filter. The LC trap, tuned to the inverter switching frequency, is very effective in reducing the switching harmonics. By using this new topology the need for high damping resistance and low RLC cut-off frequency is eliminated. This reduces the phase shift in the current regulation loop and increases the filter efficiency. Experimental verification of the filter topology is provided with a 180 V inverter and a 25 hp permanent magnet synchronous motor. Space-vector predictive current regulation is implemented as an inner-loop current regulator for the outer-loop speed control using a digital signal processor. The effectiveness of the filter at different motor speeds is presented     

PWM驱动电机系统传导干扰等效电路模型

采用脉宽调制技术（PWM）驱动的电机系统通过功率变换器对电能进行变换和控制,使得电机系统的性能指标得到较大提高。但是由于功率变换器中的电力电子器件工作在开关状态,具有较大电压和电流变化率的功率脉冲信号产生很强的电磁干扰,对电机系统自身和周围环境产生很大影响。本文针对PWM变频器产生的电磁兼容问题,首先分析了PWM驱动电...     

带中性点电压调节的级联型高压变频器拓扑研究

目前传统级联型高压变频器广泛应用于交流电机的调速,但是结构上的缺陷使得它无法将电机制动能量回馈至电网。本文提出了一种具有能量回馈功能的级联型高压变频器新型拓扑。在传统级联高压变频器拓扑的基础上,将浮空的中性点断开,串入一个双PWM变换器．并对串入的双PWM变换器建模,最后通过仿真验证,说明这种新型拓扑在电机制动时进行能量回馈的可行性。     

Multicarrier PWM strategies for multilevel inverters

Analytical solutions of pulsewidth-modulation (PWM) strategies for multilevel inverters are used to identify that alternative phase opposition disposition PWM for diode-clamped inverters produces the same harmonic performance as phase-shifted carrier PWM for cascaded inverters, and hybrid PWM for hybrid inverters, when the carrier frequencies are set to achieve the same number of inverter switch transitions over each fundamental cycle. Using this understanding, a PWM method is then developed for cascaded and hybrid inverters to achieve the same harmonic gains as phase disposition PWM achieves for diode-clamped inverters. Theoretical and experimental results are presented in the paper.     

Distributed Control of Hybrid Motor Drives

The hybrid inverter fed motor drive with two cascaded multilevel inverters is an attractive option for high performance high power applications such as naval ship propulsion systems due to a number of unique features. There is a natural split between a higher-voltage lower-frequency “bulk” inverter and a lower-voltage higher-frequency “conditioning” inverter in the cascaded system which matches the availability of semiconductor devices. Furthermore, the bulk inverter may be a commercial-off-the-shelf (COTS) motor drive meaning that only the conditioning inverter needs to be custom made. However, a drive involving a COTS bulk inverter would require a distributed conditioning inverter control which works completely independent of the bulk inverter control. In this paper, a set of distributed control methods are developed for the hybrid inverter drive with cascaded bulk and conditioning inverters, requiring only single dc source. Moreover, a solution to the practical problem of instant synchronization between the two inverters is presented. Laboratory measurements on a 3.7-kW induction motor drive validate the proposed control. Various practical considerations (such as low$m$-index performance and capacitor precharging options) are discussed and their solutions provided.     

PWM Method to Eliminate Power Sources in a Nonredundant 27-Level Inverter for Machine Drive Applications

A nonredundant three-stage 27-level inverter using ldquoHrdquo converters is analyzed for medium- and high-power machine drive applications. The main advantage of this converter is the optimization of levels with a minimum number of semiconductors. However, the system needs six bidirectional and isolated power supplies and three more unidirectional if the machine is not using regenerative braking. In this paper, these nine power supplies are reduced to only four, all of them unidirectional, using three strategies: 1) the utilization of independent and isolated windings for each phase of the motor; 2) the utilization of independent input transformers; and 3) the most important of them, the application of special pulsewidth modulation (PWM) strategies on the 27-level converter, to keep positive average power at the medium power bridges and zero average power at the low-power bridges. The generation of this PWM and control of this multiconverter was implemented using DSP controllers, which give flexibility to the system.     

Switching Characterization of Cascaded Multilevel-Inverter-Controlled Systems

In this paper, the method of triangular carrier switching control of two-level inverters is extended to cascaded multilevel inverters using phase-shifted multicarrier unipolar pulsewidth modulation (PWM). The condition for smooth modulation is obtained using the Bessel's function representation of the PWM output and the switching condition of the multilevel-inverter-controlled system. A method is proposed for the determination of the minimum amplitude of the triangular carrier for smooth modulation at fixed switching frequency. It is shown that the multilevel modulation based on the phase-shifted carriers significantly reduces the ripple magnitude in the switching function and allows the use of a smaller carrier amplitude under closed loop. This increases the forward gain and, hence, improves the tracking characteristics. The proposed cascaded multilevel inverter control is implemented for the operation of a distribution static compensator (DSTATCOM) in the voltage control mode. The experimental verification of the theoretical and simulation results is provided through a field-programmable gate array (FPGA) based control of a laboratory model of a single-phase DSTATCOM.     

A new pulse-width modulation (PWM) scheme for modular structured multilevel voltage source inverter

This work proposes a new switching scheme for a particular multilevel topology, known as the modular structured multilevel inverter (MSMI). The proposed scheme is based on symmetric regular sampled unipolar PWM, with multiple modulating waveforms and a single carrier. Mathematical equations that define the PWM switching instants are derived. These equations are suitable for digital implementation. An experimental five-level MSMI test-rig is built to implement the proposed algorithm. The derived equations are implemented by a low-cost fixed-point microcontroller. Several tests to quantify the performance of the inverter under the proposed modulation scheme are carried out.     

H桥级联多电平逆变器相移SVPWM技术的研究

载波相移SPWM调制法是级联型逆变器的主流控制方法,其等效载波频率高、谐波特性好、功率单元之间输出功率平衡。而空间矢量法谐波特性好、电压利用率高、控制方法简单便于数字实现。文中针对H桥级联型多电平逆变器的结构特点,综合采用载波移相SPWM法和空间矢量法,并用一种新的空间矢量算法取代传统的方法。该算法中无需三角函数和无理数计算,计算过程非常简单,节约了计算时间,结果更为准确。最后通过系统仿真验证该算法的正确性和有效性。     

A line-voltage-sensorless synchronous rectifier

A line-voltage-sensorless control for three-phase pulsewidth-modulated (PWM) synchronous rectifiers is presented. A line synchronization and unity power factor control are described. Indirect synchronization without sensing the line voltage allows a standard vector-controlled inverter to be used as a synchronous rectifier without requiring any additional hardware. Furthermore, the line synchronization can be properly operated under line voltage distortion or notching and line frequency variation. All control functions are implemented with a single-chip microcontroller. It is shown via experimental results that the proposed controller gives good performance for the synchronous rectifier     

Dead-Time Elimination of PWM-Controlled Inverter/Converter Without Separate Power Sources for Current Polarity Detection Circuit

This paper will present a dead-time elimination scheme for a pulsewidth-modulation (PWM)-controlled inverter/converter. The presented dead-time elimination scheme does not require separated power supplies for freewheeling-current detection of high- and low-side power devices. The presented scheme includes the freewheeling-current polarity detection circuit and the PWM control generator without dead time. It will be shown that the presented scheme eliminates the dead time of PWM control for inverter/converter and therefore dramatically improves output voltage loss and current distortion. Experimental results derived from a field-programmable-gate-array-based PWM-controlled inverter are shown to demonstrate the effectiveness.      

Switching frequency optimal PWM control of a three-level inverter

A pulse-width-modulation (PWM) method for the control of a three-level inverter is described. The switching frequency optimal-PWM method (SFO-PWM) works with a constant carrier frequency not synchronized with fundamental stator frequency. SFO-PWM gives an optimal utilization of the mean thyristor switching frequency permitted; therefore, PWM carrier frequency may be chosen to a value of two times the permitted mean thyristor switching frequency. The signal processing structure is simple. Many applications of three-level inverter work with a DC-link neutral point not stabilized from the power input converter. A neutral-point potential control is described, which is capable of stabilizing potential by varying the switching sequences of the three-level inverter itself. Results from computer simulation and practical experience show the good performance of SFO-PWM     

Design and implementation of an FPGA-based control IC forAC-voltage regulation

This paper presents a field-programmable gate army (FPGA)-based control integrated circuit (IC) for controlling the pulsewidth modulation (PWM) inverters used in power conditioning systems for AC-voltage regulation. We also propose a multiple-loop control scheme for this PWM inverter control IC to achieve sinusoidal voltage regulation under large load variations. The control scheme is simple in architecture and thus facilitates realization of the proposed digital controller for the PWM inverter using the FPGA-based circuit design approach. Bit-length effect of the digital PWM inverter controller has also been examined in this paper. The designed PWM inverter control IC has been realized using a single FPGA XC4005 from Xilinx Inc., which can be used as a coprocessor with a general-purpose microprocessor in application of AC-voltage regulation. Owing to the high-speed nature of FPGA, the sampling frequency of the constructed IC can be raised up to the range that cannot be reached using a conventional digital controller based merely on microcontrollers or a digital signal processor (DSP). Experimental results show the designed PWM inverter control IC using the proposed control scheme can achieve good voltage regulation against large load variations