Low-power CMOS wireless MEMS motion sensor for physiological activity monitoring

In this paper, a short distance wireless sensor node "AccuMicroMotion" for physiological activity monitoring is proposed for detecting motions in six degrees of freedom. System architecture, relevant microstructures, and electronic circuits to implement the sensor node are presented. A three-axis microelectromechanical systems (MEMS) accelerometer and a z-axis gyroscope are designed and fabricated using a new deep-reactive ion-etch CMOS-MEMS process. The interface circuits, an analog-to-digital converter, and a wireless transmitter are designed using Taiwan Semiconductor Manufacturing Company 0.35-/spl mu/m CMOS process, wherein the interface circuits adopt chopper stabilization technique and can resolve a signal (dc to 1 kHz) as low as 200 nV from the microsensors; digitized outputs from the microsensors are transmitted by a 900-MHz amplitude-shift-keying radio-frequency transmitter that delivers a 2.2-mW power to a 50-/spl Omega/ antenna. The system draws an average current of 4.8 mA from a 3-V supply when six sensors are in operation simultaneously and provides an overall 60-dB dynamic range.     

Distributed wake-up scheduling for data collection in tree-based wireless sensor networks

In a multi-hop wireless network, a conventional way of defining interference neighbors is to prohibit a node from using the same slot/code as those of its 1-hop and 2-hop neighbors. However, for data collection in a wireless sensor network, since the set of communication nodes is limited and the transmission directions are toward the sink, we show that a less strict set of interference neighbors can be defined. Based on this observation, we develop an efficient distributed wake-up scheduling scheme for data collection in a sensor network that achieves both energy conservation and low reporting latency.     

Low-power fully integrated and tunable CMOS RF wireless receiver for ISM band consumer applications

A 0.25-/spl mu/m single-chip CMOS single-conversion tunable low intermediate frequency (IF) receiver operated in the 902-928-MHz industrial, scientific, and medical band is proposed. A new 10.7-MHz IF section that contains a limiting amplifier and a frequency modulated/frequency-shift-key demodulator is designed. The frequency to voltage conversion gain of the demodulator is 15 mV/kHz and the dynamic range of the limiting amplifier is around 80 dB. The sensitivity of the IF section including the demodulator and limiting amplifier is -72 dBm. With on-chip tunable components in the low-power low-noise amplifier (LNA) and LC-tank voltage-controlled oscillator circuit, the receiver measures an RF gain of 15 dB at 915 MHz, a sensitivity of -80 dBm at 0.1% bit-error rate, an input referred third-order intercept point of -9 dBm, and a noise figure of 5 dB with a current consumption of 33 mA and a 2450 /spl mu/m/spl times/ 2450 /spl mu/m chip area.     

Design techniques for mitigation of intermodulation distortion components in CMOS RF receiver front-end circuits with subthreshold operation

This paper provides an overview of target applications and design aspects for emerging radio frequency front-end circuits with subthreshold biasing to reduce power consumption. Design methods are described to linearize a subthreshold pseudo-differential common-source cascode low-noise amplifier (LNA) and a subthreshold active mixer. The linearization techniques can improve the third-order intermodulation intercept point (IIP3) through the use of passive components, which implies that they do not require auxiliary amplifiers to suppress third-order distortion components, and therefore do not incur any extra power consumption. A 1.95 GHz receiver front-end chip with a narrowband LNA and down-conversion mixer was designed and fabricated in 110 nm CMOS technology. Measurement results show that the linearized low-power front-end has a 20.6 dB voltage gain, a 9.5 dB double sideband noise figure, and a ? 10.8 dBm IIP3 with a power consumption of 0.9 mW.     

High-speed CMOS wavefront sensor with resistive-ring networks of winner-take-all circuits

We present a high-bandwidth Hartmann-Shack sensor for adaptive optics implemented in a standard 0.35 /spl mu/m CMOS process technology. Hartmann-Shack sensors reconstruct an optical wavefront from the displacement of focal points as imaged by a microlens array. This image is usually captured by CCD cameras and then processed by software, limiting the wavefront bandwidth to a few hertz. The presented CMOS-based sensors achieves a frame rate of up to 4 kHz by analog image processing on the focal plane. The implemented position sensitive detectors consist of a resistive-ring network of Winner-Take-All circuits with reduced sensitivity to transistor mismatch and fixed-pattern noise. This CMOS-based wavefront sensor allowed the first high-bandwidth wavefront measurements at the human eye.     

Low-power clock-less hardware implementation of the rijndael S-box for wireless sensor networks

The recent development of microelectronics techniques and advances in wireless communications have made it feasible to design low-cost, low-power, multifunctional and intelligent sensor nodes for wireless sensor networks (WSN). The design challenges for an efficient WSN mainly lie in two issues power and security. The Rijindael algorithm is a candidate algorithm for encrypting data in WSN. The SubByte (S-box) transformation is the main building block of the Rijindael algorithm. It dominates the hardware complexity and power consumption of the Rijindael cryptographic engine. This article proposes a clock-less hardware implementation of the S-box. In this S-box, 1) The composite field arithmetic in GF((24))2 was used to implement the compact datapath circuit; 2) A high-efficiency latch controller was attained by utilizing the four-phase micropipeline. The presented hardware circuit is an application specific integrated circuit (ASIC) on 0.25 μm complementary mental oxide semiconductor (CMOS) process using three metal layers. The layout simulation results show that the proposed S-box offers low-power consumption and high speed with moderate area penalty. This study also proves that the clock-less design methodology can implement high- performance cryptographic intellectual property (IP) core for the wireless sensor node chips.     

Low-power interface circuits between adiabatic and standard CMOS circuits

The clocking schemes and signal waveforms of adiabatic circuits are different from those of standard CMOS circuits. This paper investigates the design approaches of low-power interface circuits in terms of energy dissipation. Several low-power interface circuits that convert signals between adiabatic logic and standard CMOS circuits are presented. All interface circuits and their layouts are implemented using TSMC 0.18 μm CMOS technology. The function verifications and energy loss tests for all interfaces are carried out using the net-list extracted from the layout. Full parasitic extraction is done. An adiabatic 8-bit carry look-ahead adder embedded in a static CMOS circuits is used to verify the proposed interfaces. The proposed interface circuits attain large energy savings over a wide range of frequencies, as compared with the previously reported circuits.     

SMTS: a swarm intelligence-inspired sensor wake-up control method for multi-target sensing in wireless sensor networks

Wireless Networks - The different number of targets in wireless sensor networks (WSNs) leads to different detection effects. Because of the existence of multiple targets in the detection area,...     

A fully integrated CMOS super-regenerative wake-up receiver for EEG applications

A fully integrated super-regenerative wake-up receiver for wireless body area network applications is presented. The super-regeneration receiver is designed to receive OOK-modulated data from the base station. A low power waveform generator is adopted both to provide a quench signal for VCO and to provide a clock signal for the digital module. The receiver is manufactured in 0.18 μm CMOS process and the active area is 0.67 mm². It achieves a sensitivity of -80 dBm for 10^-3 BER with a data rate of 200 kbps. The power consumption of the super-regenerative wake-up receiver is about 2.16 mW.     

一种基于CMOS亚阈值设计的低失调基准电路

基于工作在亚阈值区域的PMOS管,提出一种叠加结构的低失调带隙基准电路。该方法将传统基准电路中倍乘的失调电压转变为均方根的形式,有效降低了基准电路的失调电压。仿真表明该基准电路的输出电压为1.07 V,3σ范围内的失调电压为6.69 mV,温度特性为21.3 ppm/℃,PSRR为-56 dB。该电路在TSMC18工艺下成功流片。     

CMOS phase-shifting circuits for wireless beamforming transmitters

Two phase-shifting techniques for wireless beamforming transmitter applications are presented. The first performs quadrant selection using phase-offset local oscillators and fine-grain phase-shifting using RF phase shifters; a 5.2 GHz narrowband phase shifter is designed and fabricated in the CMOS subset of a 0.25 μm SiGe BiCMOS process. Using a tunable all-pass filter topology, it achieves a wide phase-shift range with low loss, and minimizes the number of on-chip passive elements. Measurement results show an insertion loss of 2 dB, an IIP3 of 1 dBm, and a total phase-shift range of 240°; power consumption of the core circuitry is 36.3 mW from a 2.5 V supply. The second approach, a phase-shifting up-converter based on Cartesian combining, achieves a 360° phase shift range that is independent of the operating frequency. Fabricated in 0.18 μm CMOS, it achieves 8 dB conversion gain, 4 dBm OP1 dB, 28 dB sideband rejection, and a 360° phase-shift range at 5.2 GHz without the explicit use of RF phase shifters. The power consumption of its core circuitry is 46.5 mW.     

nW-MAC: multiple wake-up provisioning in asynchronously scheduled duty cycle MAC protocol for wireless sensor networks

To reduce the energy cost of wireless sensor networks (WSNs), the duty cycle (i.e., periodic wake-up and sleep) concept has been used in several medium access control (MAC) protocols. Although these protocols are energy efficient, they are primarily designed for low-traffic environments and therefore sacrifice delay in order to maximize energy conservation. However, many applications having both low and high traffic demand a duty cycle MAC that is able to achieve better energy utilization with minimum energy loss ensuring delay optimization for timely and effective actions. In this paper, nW-MAC is proposed; this is an asynchronously scheduled and multiple wake-up provisioned duty cycle MAC protocol for WSNs. The nW-MAC employs an asynchronous rendezvous schedule selection technique to provision a maximum of n wake-ups in the operational cycle of a receiver. The proposed MAC is suitable to perform in both low- and high-traffic applications using a reception window-based medium access with a specific RxOp. Furthermore, per cycle multiple wake-up concept ensures optimum energy consumption and delay maintaining a higher throughput, as compare to existing mechanisms. Through analysis and simulations, we have quantified the energy-delay performance and obtained results that expose the effectiveness of nW-MAC.     

Low-power ultrawideband wireless telemetry transceiver for medical sensor applications

An integrated CMOS ultrawideband wireless telemetry transceiver for wearable and implantable medical sensor applications is reported in this letter. This high duty cycled, noncoherent transceiver supports scalable data rate up to 10 Mb/s with energy efficiency of 0.35 nJ/bit and 6.2 nJ/bit for transmitter and receiver, respectively. A prototype wireless capsule endoscopy using the proposed transceiver demonstrated in vivo image transmission of 640 × 480 resolution at a frame rate of 2.5 frames/s with 10 Mb/s data rate.     

Low-power circuits for the wireless ligament balance measurement system in TKA

A low power system for the ligament balance measuring in Total Knee Arthroplasty is presented in this paper. The system consists two parts: a front-end Ligament Balance Measuring System (LBMS) which is inserted into the knee joint during the operation, and the display part. LBMS is comprised of a sensors array including eight precise force sensors, signal conditioning circuits that support up to 15 force sensors, a sub-threshold microprocessor, power circuits and a 433?MHz RF transceiver for data transmission. The force corresponding to its distribution is transmitted wirelessly and displayed in 3-D in real time with an accuracy of 0.049?N. The signal conditioning circuits, the sub-threshold 8?bit microprocessor and the application specific integrated circuits chip have been designed and fabricated in 0.18???m CMOS process. The tested resolution is 60.1???V_pp (1.35?g) with ±100?mV_pp input. The chip can operate under 1.2 to 3.6?V voltage supply for single battery application with 116?C160???A power consumption. The testing results of the microprocessor show that the leakage power is 46?nW and the dynamic power is 385?nW @ 165?kHz with operating voltage of 350?mV. The simulation results show that the power circuits can provide the supply voltage ranging from 0.3?V to 0.6?V for the sub-threshold microprocessor. Experimental results verified the system. Some clinical experiments will be carried out in the future.     

Wake-up radio receiver based power minimization techniques for wireless sensor networks: A review

In a short period of time Wireless Sensor Networks (WSN) captured the imagination of many researchers with the number of applications growing rapidly. The applications span large domains including mobile digital health, structural and environmental monitoring, smart home, energy efficient buildings, agriculture, smart cities, etc. WSN are also an important contributor to the fast emerging Internet of Things infrastructure. Some of the design specifications for WSN include reliability, accuracy, cost, deployment versatility, power consumption, etc. Power consumption is (most often) the dominant constraint in designing such systems. This constraint has multi-dimensional implications such as battery type and size, energy harvester design, lifetime of the deployment, intelligent sensing capability, etc. Power optimization techniques have to explore a large design search space. Energy neutral system implementation is the ultimate goal in wireless sensor networks ensuring a perpetual/greener use and represents a hot topic of research. Several recent advances promise significant reduction of the overall sensor network power consumption. These advances include novel sensors and sensor interfaces, low energy wireless transceivers, low power processing, efficient energy harvesters, etc. This paper reviews a number of system level power management methodologies for Wireless Sensor Networks. Especially, the paper is focusing on the promising technology of nano-Watt wake-up radio receiver and its combination with mature power management techniques to achieve better performance. Some of the presented techniques are then applied in the context of low cost and battery powered toy robots.     

CIS片上系统中伽玛校正的低功耗设计

为了实现CMOS图像传感器(CIS)片上系统(SoC)中伽玛(γ)校正的低功耗设计,同时又保证校正的精度,提出一种查找表和直线拟合相结合的γ校正技术。算法对灰度值较低的像素使用直接查找表方法校正,对于γ曲线上升缓慢部分的像素采用分段直线拟合的方法。在直线分段时,使用外层分段与内层分段相结合的方法,达到了分段优化的目的。算法保证了图像校正精度,与使用完全查找表法相比,误差在0.5 pixel之内。基于该方法设计了一个8 bit输入/8 bit输出的VLSI模块,通过FPGA对模块进行了验证,模块占用723个LE和195个LC寄存器,比完全查找表法减少了硬件资源耗费,实现了低功耗设计。系统最大工作频率可达148 MHz,完全满足实时处理的需求。     

A CMOS adaptive RF front-end receiver for wireless applications

The performance of signal-processing algorithms implemented in hardware depends on the efficiency of datapath, memory speed and address computation. Pattern of data access in signal-processing applications is complex and it is desirable to execute the innermost loop of a kernel in a single-clock cycle. This necessitates the generation of typically three addresses per clock: two addresses for data sample/coefficient and one for the storage of processed data. Most of the Reconfigurable Processors, designed for multimedia, focus on mapping the multimedia applications written in a high-level language directly on to the reconfigurable fabric, implying the use of same datapath resources for kernel processing and address generation. This results in inconsistent and non-optimal use of finite datapath resources. Presence of a set of dedicated, efficient Address Generator Units (AGUs) helps in better utilisation of the datapath elements by using them only for kernel operations; and will certainly enhance the performance. This article focuses on the design and application-specific integrated circuit implementation of address generators for complex addressing modes required by multimedia signal-processing kernels. A novel algorithm and hardware for AGU is developed for accessing data and coefficients in a bit-reversed order for fast Fourier transform kernel spanning over log?₂ N stages, AGUs for zig-zag-ordered data access for entropy coding after Discrete Cosine Transform (DCT), convolution kernels with stored/streaming data, accessing data for motion estimation using the block-matching technique and other conventional addressing modes. When mapped to hardware, they scale linearly in gate complexity with increase in the size.     

Low-power/low-voltage RF microsystems for wireless sensors networks

This paper presents radio-frequency (RF) microsystems (MSTs) composed by low-power devices for use in wireless sensors networks (WSNs). The RF CMOS transceiver is the main electronic system and its power consumption is a critical issue. Two RF CMOS transceivers with low-power and low-voltage supply were fabricated to operate in the 2.4 and 5.7 GHz ISM bands. The measurements made in the RF CMOS transceiver at 2.4 GHz, which showed a sensitivity of −60 dBm with a power consumption of 6.3 mW from 1.8 V supply. The measurements also showed that the transmitter delivers an output power of 0 dBm with a power consumption of 11.2 mW. The RF CMOS transceiver at 5.7 GHz has a total power consumption of 23 mW. The target application of these RF CMOS transceivers is for MSTs integration and for use as low-power nodes in WSNs to work during large periods of time without human operation, management and maintenance. These RF CMOS transceivers are also suitable for integration in thermoelectric energy scavenging MSTs.     

CMOS image sensors for sensor networks

We report on two generations of CMOS image sensors with digital output fabricated in a 0.6 μm CMOS process. The imagers embed an ALOHA MAC interface for unfettered self-timed pixel read-out targeted to energy-aware sensor network applications. Collision on the output is monitored using contention detector circuits. The image sensors present very high dynamic range and ultra-low power operation. This characteristics allow the sensor to operate in different lighting conditions and for years on the sensor network node power budget. Eugenio Culurciello (S’97–M’99) received the Ph.D. degree in Electrical and Computer Engineering in 2004 from Johns Hopkins University, Baltimore, MD. In July 2004 he joined the department of Electrical Engineering at Yale University, where he is currently an assistant professor. He founded and instrumented the E-Lab laboratory in 2004. His research interest is in analog and mixed-mode integrated circuits for biomedical applications, sensors and networks, biological sensors, Silicon on Insulator design and bio-inspired systems. Andreas G. Andreou received his Ph.D. in electrical engineering and computer science in 1986 from Johns Hopkins University. Between 1986 and 1989 he held post-doctoral fellow and associate research scientist positions in the Electrical and Computer engineering department while also a member of the professional staff at the Johns Hopkins Applied Physics Laboratory. Andreou became an assistant professor of Electrical and Computer engineering in 1989, associate professor in 1993 and professor in 1996. He is also a professor of Computer Science and of the Whitaker Biomedical Engineering Institute and director of the Institute’s Fabrication and Lithography Facility in Clark Hall. He is the co-founder of the Johns Hopkins University Center for Language and Speech Processing. Between 2001 and 2003 he was the founding director of the ABET accredited undergraduate Computer Engineering program. In 1996 and 1997 he was a visiting professor of the computation and neural systems program at the California Institute of Technology. In 1989 and 1991 he was awarded the R.W. Hart Prize for his work on mixed analog/digital integrated circuits for space applications. He is the recipient of the 1995 and 1997 Myril B. Reed Best Paper Award and the 2000 IEEE Circuits and Systems Society, Darlington Best Paper Award. During the summer of 2001 he was a visiting professor in the department of systems engineering and machine intelligence at Tohoku University. In 2006, Prof. Andreou was elected as an IEEE Fellow and a distinguished lecturer of the IEEE EDS society. Andreou’s research interests include sensors, micropower electronics, heterogeneous microsystems, and information processing in biological systems. He is a co-editor of the IEEE Press book: Low-Voltage/Low-Power Integrated Circuits and Systems, 1998 (translated in Japanese) and the Kluwer Academic Publishers book: Adaptive Resonance Theory Microchips, 1998. He is an associate editor of IEEE Transactions on Circuits and Systems I.     

Low-voltage subthreshold CMOS current mode circuits: Design and applications

The world has migrated to portable applications ranging from smart phones to Lab on a Chip applications. However they come with a new set of challenges for analog IC designers. Low voltage operation, small area and low noise are the critical design criteria for portable devices. This paper presents a g_m/I_D based design methodology for low voltage current mode circuits using standard CMOS technology. A second generation current conveyor (CCII) and a current feedback operational amplifier (CFA) are designed using the discussed design procedure. Both circuits operate from a single 0.4 V supply. The CCII is used to implement an instrumentation amplifier. Multiple applications are implemented using the CFA. Post layout simulation using TSMC 90 nm and UMC 130 nm technology show that the presented design procedure is an attractive solution for low voltage CMOS current mode circuits.