A novel design of local-feedback MOS transconductor using techniques for cancellation of mobility degradation and linearization of differential output current characteristic

In this article, a novel design of a local-feedback MOS transconductor using a technique of canceling mobility degradation and a linearization technique of differential output current characteristics is proposed. In the proposed techniques, adaptively biasing current sources are employed to improve linearity deterioration due to mobility degradation effect and to terminate differential output nodes for elimination of second-order nonlinear terms. The proposed transconductor has good linearity. Simulation results show that the proposed techniques are effective for improvement of linear characteristics.     

A linear compact tunable transconductor for Gm-C applications

A CMOS highly linear voltage-controlled transconductor suitable for Gm-C filter design is presented. The control loop to program the transconductance maintains the input transistors in triode region with a compact topology. Measurement results for the transconductor fabricated in a 0.5-??m CMOS technology feature a spurious-free dynamic range (SFDR) of 72?dB for 1 V_pp differential inputs at 1?MHz. The voltage to current converter ensures a high linearity level for a wide transconductance range. Functionality of the transconductor is shown in a fifth-order Gm-C tunable complex filter well suited for a dual-mode Bluetooth/Zigbee transceiver.     

New highly linear tunable transconductor circuits with low number of MOS transistors

In this article, two new highly linear tunable transconductor circuits are proposed. The transconductors employ only six MOS transistors operated in saturation region. The second transconductor is derived from the first one with a slight modification. Transconductance of both transconductors can be tuned by a control voltage. Both of the transconductors do not need any additional bias voltages and currents. Another important feature of the transconductors is their high input and output impedances for cascadability with other circuits. Besides, total harmonic distortions are less than 1.5% for both transconductors. A positive lossless grounded inductor simulator with a grounded capacitor is given as an application example of the transconductors. Simulation and experimental test results are included to show effectiveness of the proposed circuits.     

A high-linear wide-tunable CMOS transconductor for video frequency applications

In this paper a new CMOS transconductor structure based on a g_m-boosted degenerated differential pair is presented for applications in the video frequency range. The proposed circuit combines two techniques, a switchable array of source degenerating MOS resistors and a programmable output current mirror, in order to widen the G_m tuning range while maintaining linearity. Degeneration MOS resistors are made common-mode voltage independent thanks to a simple control circuit. Post-layout simulation results from a 0.35 μm design supplied at 3.3 V show a wide tuning range (10–100 MHz), good linearity (−58.4 dB for an output signal voltage of 1.1 V_p–p) and low excess phase (<0.5° over the whole tuning range).     

Low-voltage MOS linear transconductor/squarer and four-quadrant multiplier for analog VLSI

Analog computations such as four-quadrant multiplication, linear voltage-to-current conversion and sum-square or difference-square are fundamental for many analog signal processing systems. All these functions can be realized based on the principle of the linearized differential pair using floating-voltage sources. This paper describes an improved practical realization of this principle, which is particularly suited to analog VLSI computational systems. The proposed class-AB analog cells are very compact, exhibit low total harmonic distortion and low nonlinearity, have a wide bandwidth, and are compatible with low-power and low-voltage operation. A mathematical discussion on stability and harmonic distortion of the proposed realization is presented. Both simulated results and measurements from fabricated cell samples in a 0.8-/spl mu/m CMOS process are given. The described circuits operate from a single 2-V power supply.     

The design of high performance linear transconductor

An improved structure of linear transconductor is presented in this paper. It is analyzed in theory and simulated with Spectre based on 0.25μm CMOS process. The simulation results show that the differential input voltage of the proposed transconductor is 4.0Vpp（peak to peak）, whereas the differential input voltage of the existing source degeneration structure is 2.2Vpp, when their nonlinear errors are required to be less than 0.15%.     

Split length FGMOS MOS cell: a new block for low voltage applications

A new analog cell, called floating gate split length MOSFET (FGSLM), has been presented. This cell is based on the popular self-cascode structure, and has been found suitable for use in low voltage design applications. The proposed cell has been characterized using 130 nm technology at supply voltage of 1.2 V. Simulation results are presented to demonstrate the utility of the proposed cell in low voltage self cascode structures.     

Novel fully differential MOS transconductor for integrated continuous-time filters

A new fully differential MOS transconductor for integrated continuous-time filters is proposed. The transconductor consists of four MOS transistors biased in their linear operating region. Advantages of the transconductor include low distortion, large signal handling capability, a wide tuning range and simplicity of design.     

Making CMOS OTA a linear transconductor

In linear applications, the CMOS operational transconductance amplifiers (OTA) are only tolerable of small signals as they suffer from severe nonlinearity because of the source-coupled pairs. A new approach making ordinary OTA a linear transconductor capable of handling very large signals subject to the linear I-V restraint provided by a 2-MOSFET transresistor and feedback is presented.<>     

A low-voltage, highly linear voltage-controlled transconductor

A low-voltage fully differential, voltage-controlled transconductor is described. The proposed transconductor achieves a wide input/control voltage range, with a highly linear transconductance factor and truly fully differential output currents. The transconductor is used to implement a G/sub m/-C adaptive forward equalizer (FE) for a 125 Mbps wire line transceiver using digital core transistors with channel length of no more than double the feature size in a typical digital CMOS 180-nm process and supply voltage as low as 1.6 V. The adaptive FE enables IEEE 1394b transceivers to operate over UTP-5 cables for up to 100 m in length. The transconductor stage occupies 1945 /spl mu/m/sup 2/ and consumes an average power of 418 /spl mu/w at 125 Mbps and 1.8-V supply.     

A versatile CMOS linear transconductor/square-law function

A simple CMOS circuit technique for realizing both linear transconductance and a precision square-law function is described. The circuit provides two separate outputs in the linear as well as square-law modes. The linear outputs both have a range of 100% or more of the total quiescent current value. The theory of operation is presented and effects of transistor nonidealities on the performance are investigated. Design optimization techniques are developed. Experimental results measured on nonoptimized prototypes are: distortion of 0.2% for input signals up to 2.4 V/SUB p-p/ in the case of linear transfer function and 1.3% in the case of the square-law transfer function, with a DC to -3-dB bandwidth of up to 20 MHz. Improved performance is expected when the optimization techniques developed are applied. The circuit is versatile in application: diverse applications are demonstrated in the fields of linear amplifiers, continuous-time filters, and nonlinear function implementation.     

Digitally programmable CMOS transconductor for very high frequency

This paper describes a new approach for realizing digitally programmable VHF/UHF transconductors compatible with pure digital CMOS technologies. A programmable/tunable transconductor, based on a parallel connection of unit cascode cells, is used to implement a fully balanced current-mode G_m–C integrator to operate over the 30–200 MHz range with more than 70 dB of dynamic range for 1% of THD.     

An improved analysis for the bipolar linear transconductor

An improved analysis for the bipolar linear transconductor, assuming a finite value for the transistor current-gain β, is presented. A new expression for the normalized input-voltage as a function of the normalized output-current is obtained. A Fourier-series model is presented for this current-voltage relationship. Closed-form expressions are also derived for the harmonic and intermodulation components resulting from exciting the bipolar linear transconductor by a multisinusoidal input voltage. These expressions can be used to predict the limiting values of the input voltage amplitudes for a prescribed tolerable distortion percentage.     

High frequency gallium arsenide linearised transconductor for communications

The authors propose a linear transconductor circuit for implementation in GaAs MESFET technology. The application of the transconductor to linear microwave amplifiers and linear drive circuits for optical systems is described.<>     

A highly linear CMOS low noise amplifier for K-band applications

This paper describes a highly linear low noise amplifier (LNA) for K-band applications in a 0.18 µm RF CMOS technology. The core of the circuit is a two-stage LNA consisting of a common-source and a cascode stage. By adopting an improved post-linearisation technique at the common-source transistor of the second stage, more than 5 dB improvement in IIP3 is achieved with a minor effect on noise figure and input matching. The circuit level analysis and simulation results are presented to demonstrate the effectiveness of the proposed technique.     

CMOS linear programmable transconductor suitable for adjustable Gm-C filters

A novel CMOS linear programmable transconductor is presented. It is based on a telescopic cascode operational transconductance amplifier with source degeneration implemented by means of highly linear tunable active resistors. The transconductor has been designed in a 0.5 mum CMOS technology featuring a third-order intermodulation (IM3) of -54.8 dB at 10 MHz for a 1 V_pp output voltage. Its feasibility for Gm-C filter design has been experimentally validated with a 1 MHz tunable third-order Chebyshev lowpass filter suitable for Bluetooth applications.     

A novel two-dimensional MOS transistor for analog applications

In analog MOS integrated circuits, matching between transistors is a critical requirement because the circuit performance is determined by the device matching available. A new type of matched configuration is presented in this paper which utilizes the inherent 2-D geometry of an MOS transistor which was hitherto unexplored. This has been achieved by adding two more diffusion regions along the length of a normal MOS transistor. The characteristics of the device thus formed have been modeled in the linear region for different configurations, by solving the 2-D current continuity equation. For the saturation region, an empirical relation has been given. Theoretical and experimental results for a test chip have been presented. A few potential applications are mentioned.