Chaotic cellular neural network‐based true random number generator

This paper presents implementation of a chaotic cellular neural network (CNN)‐based true random number generator on a field programmable gate array (FPGA) board. In this implementation, discrete time model of the chaotic CNN is used as the entropy source. Random number series are generated for three scenarios. Obtained number series are tested by using NIST 800.22 statistical test suite. Also, the scale index technique is carried out for these three scenarios to determine the degree of non‐periodicity for key stream. Copyright © 2017 John Wiley & Sons, Ltd.     

Design and ARM‐embedded implementation of a chaotic map‐based multicast scheme for multiuser speech wireless communication

This paper proposes a chaotic map‐based multicast scheme for multiuser speech wireless communication and implements it in an ARM platform. The scheme compresses the digital audio signal decoded by a sound card and then encrypts it with a three‐level chaotic encryption scheme. First, the position of every bit of the compressed data is permuted randomly with a pseudo‐random number sequence (PRNS) generated by a 6‐D chaotic map. Then, the obtained data are further permuted in the level of byte with a PRNS generated by a 7‐D chaotic map. Finally, it is operated with a multiround chaotic stream cipher. The whole system owns the following merits: the redundancy in the original audio file is reduced effectively and the corresponding unicity distance is increased; the balancing point between a high security level of the system and real‐time conduction speed is achieved well. In the ARM implementation, the framework of communication of multicast–multiuser in a subnet and the Internet Group Manage Protocol is adopted to obtain the function of communication between one client and other ones. Comprehensive test results were provided to show the feasibility and security performance of the whole system. Copyright © 2016 John Wiley & Sons, Ltd.     

Generation of pseudo‐random numbers by chaos‐type function and its application to cryptosystems

The logistic map is known to be one of the nonlinear difference equations as a chaos map, and to generate pseudo‐random numbers. However, since the chaos has a highly sensitive dependence on initial conditions and accumulates inevitable round‐off errors caused by iterating the map, the numerical generation of exact chaotic time series is said to be impossible. The aim of this paper is, first, to propose an algorithm to generate exact chaotic time series of a chaos‐type function derived from the exact chaos solution. Next, the pseudo‐random numbers are evaluated by four tests and the accumulation of chi‐square values. Also, an application to cryptosystems, which do not need the synchronization in usual computer environments, is considered. © 2008 Wiley Periodicals, Inc. Electr Eng Jpn, 163(2): 67–74, 2008; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20436     

Markov-Middleton脉冲噪声模型的硬件实现方法

影响宽带电力线载波通信的关键因素之一是随机突发的脉冲噪声。目前的噪声研究大多停留在理论建模上,缺乏标准化的电力线噪声硬件实现方法。文中深入研究Markov-Middleton脉冲噪声模型,分析产生Markov性质的脉冲序列原理,利用System Generator和Xilinx Vivado联合仿真工具,设计出具有随机突发特性的电力线噪声生成系统,并完成该系统的硬件实现。通过对比现场可编程门阵列(FPGA)输出、Middleton Class A模型仿真与实测电力线噪声的统计特性,证明了该硬件实现方法能够生成具有随机突发性和时间相关性的脉冲噪声。通过搭建实验室环境下的电力线载波通信系统,测试不同参数下噪声对通信成功率的影响程度,对比其他的硬件实现方法,验证了所提方法的工程应用价值。     

Digital implementation of biologically inspired Wilson model,population behavior,and learning

Spiking neurons, as a computational unit, are the main part in biological information processing systems. This paper presents a digital hardware implementation of a biological neuron on a field‐programmable gate array due to its high accuracy and high speed, especially for large‐scale simulations which is a key objective in the neuromorphic research field. Although this is a computationally expensive task, the use of more biological realistic system results in higher accuracy in mimicking biological behaviors of neural networks. Given that, the Wilson model is one of the most important biological neuron models that can be used in the architecture of spiking neural networks. To be closer to biological systems, a method is proposed to test the possibility of implementation of the Wilson neuron model on digital platforms. The results of the hardware implementation of the Wilson neuron and a spiking network on a field‐programmable gate array, capable of character recognition with supervised learning algorithm, are presented in this paper; moreover, population behavior of this model is simulated. In large‐scale implementation of 2000 Wilson neuron model, population capability, feasibility, and costs are investigated. This paper presents a method to the implementation of Wilson neurons on digital platforms, suggesting that the available system is an attainable platform for the implementation of large‐scale biologically plausible neural networks on field‐programmable gate array devices. Hardware synthesis, physical implementation on field‐programmable gate array, and theoretical analysis confirm that the proposed model has hardware so that makes it an appropriate model for the large‐scale digital implementation.     

First direct implementation of a true random source on programmable hardware

True random sources are not implementable in digital hardware, so that many practical applications have historically relied on pseudo‐random generators in order to avoid the potentially long prototyping times and the costs of dedicated analog design. However, pseudo‐random sources have liabilities that make them hardly suitable for some tasks (notably security related ones). Previous attempts to conciliate security, cost‐effectiveness, and rapid development included the exploitation of the analog accessory parts often present on programmable devices. In these designs some analog blocks are used for their side effects (noise amplification) rather than for their originally intended behaviour. Conversely, here we report a direct implementation of a true random source on programmable, low‐cost, general‐purpose hardware, where all blocks are used only for their nominal function. To the best of the authors' knowledge, this is the first proposal of this sort. The design exploits an FPAA, and is based on a non‐linear system exhibiting chaotic behaviour. Measures confirm the correct operation, high throughput, and robustness of the system. Copyright © 2005 John Wiley & Sons, Ltd.     

Multiscroll floating gate–based integrated chaotic oscillator

In this work, we proposed a voltage‐to‐current cell based on a Complementary metal‐oxide‐semiconductor (CMOS) inverter designed by using floating gate transistors. We demonstrate its usefulness for the design of stair‐type and sawtooth functions to be used in the implementation of a multiscroll chaotic oscillator. The main advantage of using floating gate transistors to design the nonlinear functions is the elimination of external reference DC sources, as is typically done in most of the nonlinear functions that generate multiscroll attractors. The key guidelines for the design of our proposed voltage‐to‐current cell are given to provide good performances in the design of an integrated multiscroll chaotic oscillator. HSPICE simulations are presented to demonstrate the usefulness of the proposed cell to generate multiscroll attractors. Finally, simulation results before and after layout are presented to show the good agreement with respect to theoretical results. HSPICE simulations of the post‐layout design are in accordance with the system behavior. Copyright © 2011 John Wiley & Sons, Ltd.     

1/f Noise: threshold voltage and ON-current fluctuations in 45 nm device technology due to charged random traps

Discrete impurity effects in terms of their statistical variations in number and position in the inversion and depletion region of a MOSFET, as the gate length is aggressively scaled, have recently been investigated as being a major cause of reliability degradation observed in intra-die and die-to-die threshold voltage variation on the same chip resulting in significant variation in saturation drive (on) current and transconductance degradation—two key metrics for benchmark performance of digital and analog integrated circuits. In this paper, in addition to random dopant fluctuations (RDF), the influence of random number and position of interface traps lying close to Si/SiO₂ interface has been examined as it poses additional concerns because it leads to enhanced experimentally observed fluctuations in drain current and threshold voltage. In this context, the authors of this article present novel EMC based simulation study on trap induced random telegraph noise (RTN) responsible for statistical fluctuation pattern observed in threshold voltage, its standard deviation and drive current in saturation for 45 nm gate length technology node MOSFET device. From the observed simulation results and their analysis, it can be projected that with continued scaling in gate length and width, RTN effect will eventually supersede as a major reliability bottleneck over the already present RDF phenomenon. The fluctuation patterns observed by EMC simulation outcomes for both drain current and threshold voltage have been analyzed for the cases of single trap and two traps closely adjacent to one another lying in the proximity of the Si/SiO₂ interface between source to drain region of the MOSFET and explained from analytical device physics perspectives.     

Asynchronous delay doubler and binary low‐pass filter for a time‐delay chaotic circuit

In this paper, an asynchronous digital circuit is introduced for increasing the amount of delay in binary delay lines in an area efficient way. The circuit that uses its slave delay line twice per delay event is called asynchronous delay doubler (ADD). The delay increases exponentially, while the number of components increases linearly in the recursive utilization of ADD. An assumption on the event interval of the input 2signal helps to design the ADD in a very simple form. Therefore, the ADD can be implemented with a small amount of logical resource (gates or look‐up tables). For proper operation, interval between the events (positive edge or negative edge) on the binary input signal should be larger than the delay provided by the recursive ADD block. In order to satisfy this assumption, an auxiliary asynchronous circuit, which is called binary low‐pass filter (BLPF), is also proposed. The BLPF filters out the pulses narrower than the delay generated by its recursive ADD block. The proposed ADD design is suitable especially for the applications, like random number generation, in which the deviation in amount of delay is useful as an entropy source. In order to prove the concept, a chain of recursive ADD block is implemented with BLPFs on a field‐programmable gate array and utilized in a true random bit generator. Copyright © 2015 John Wiley & Sons, Ltd.     

Novel three‐phase current‐regulated digital PWM and its behavioral analysis

There have been various studies of PWM algorithms for a three‐phase voltage‐source AC/DC power converter since the analog modulation scheme based on a triangular carrier wave was proposed in the 1960s. The PWM algorithm can be considered the heart of electronic power conversion. With progress in digital technology, there is an increasing need for gate signals to be generated directly by digital ICs, such as MPU, DSP, or FPGA/CPLD. This paper analyzes quantitatively the precision of current control of digital PWM taking account of both the sampling period and the delay time (the latter is inevitably accompanied by a digital procedure). The delay time is shown to have a double effect on the current error. In addition, the paper theoretically derives the conditions for digital PWM to meet the PPCR (Pulse Polarity Consistency Rule, that is, the next gate command moves only to the adjacent ones or commands). So far as the authors know, no paper has presented the mathematical requirements for PPCR taking account of the effect of the delay time of digital PWM. The derived theoretical results are summarized as digital PWM design criteria for a three‐phase PWM converter in order to facilitate practical implementation of the theory, guaranteeing PPCR behavior as well as quantitative accuracy of current regulation. © 2004 Wiley Periodicals, Inc. Electr Eng Jpn, 150(2): 62–77, 2005; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.10330     

基于蒙特卡罗方法的虚拟仪器测量不确定度评估

提出一种数字化虚拟仪器测量结果不确定度的评估方法,其基本思路是利用概率事件仿真技术(Monte Carlo方法)产生服从特定概率分布的随机数来模拟虚拟仪器测量链中的随机误差源,模拟随机误差与采样数据一同进入虚拟仪器信号处理模块,获得一系列伪测量结果,再用伪测量结果的统计标准方差表征虚拟仪器测量结果的不确定度,并运用虚拟仪器设计平台提供的扩展机制,建立了PCI-6024数据采集卡的随机采样误差仿真模块.应用该模块实现对信号有效值测量结果不确定度的评估,并将评估结果与理论值相比较,获得了较好的一致性.     

Design and FPGA implementation of multiplierless comb filter

T he main objective of this paper is to design and implement minimum multiplier, low latency structures of a comb filter. Multipliers are the most area and power consuming elements; therefore, it is desirable to realize a filter with minimum number of multipliers. In this paper, design of comb filters based on lattice wave digital filters (LWDF) structure is proposed to minimize the number of multipliers. The fundamental processing unit employed in LWDF requires only one multiplier. These lattice wave digital comb filters (LWDCFs) are realized using Richards' and transformed first‐order and second‐order all‐pass sections. The resulting structural realizations of LWDCFs exhibit properties such as low coefficient sensitivity, high dynamic range, high overflow level, and low round‐off noise. Multiplier coefficients of the proposed structures are implemented with canonic signed digit code (CSDC) technique using shift and add operations leading to multiplierless implementation. This contributes in reduction of number of addition levels which reduces the latency of the critical loop. A field programmable gate array (FPGA) platform is used for evaluation and testing of the proposed LWDCFs to acquire advantages of the parallelism, low cost, and low power consumption. The implementation of the proposed LWDCFs is accomplished on Xilinx Spartan‐6 and Virtex‐6 FPGA devices. By means of examples, it is shown that the implementations of the proposed LWDCFs attain high maximum sampling frequency, reduced hardware, and low power dissipation compared with the existing comb filter structures. Copyright © 2017 John Wiley & Sons, Ltd.     

Optimal arcing fault detection using signal processing techniques

In this paper we present an application of classical detection theory as a solution to the problem of detection of high impedance faults in electric power systems. An efficient realization of the resulting optimal fault detector using digital signal processing techniques is also discussed. The fault detection problem is formulated as a statistical hypothesis testing of the presence of deterministic signals with random parameters in additive noise. The resulting optimal fault detector is a power detector and can be realized using a digital notch filter and a sliding sum of the squared output of the notch filter. Finally, a count of the number of energy bursts in the high-order harmonics during a time interval is used to distinguish between faults and routine disturbances. The results make intuitive sense and can be implemented using a programmable digital signal processor.     

基于并行数据处理结构的电能质量在线监测

提出了基于现场可编程门阵列器件FPGA与数字信号处理器DSP并行结构的在线电能质量监测与分析。由FPGA同步产生系统控制时序,并充分利用FPGA与DSP各自在数字信号处理领域中的特点,在FP GA内设计了16位浮点FFT运算模块用于谐波分析,应用DSP实现电压波动与闪变等电能质量指标数据的计算,采用FPGA与DSP并行数据处理的方式,达到采样与数据处理的同步进行的目的,从而完成对多路信号的无缝采样与分析。     

Design and implementation of a digitally controlled single‐inductor dual‐output (SIDO) buck converter

This paper describes design and implementation of a digitally controlled single‐inductor dual‐output (SIDO) buck converter operating in discontinuous conduction mode. This converter adopts time‐multiplexing control in providing two independent output voltages using only an inductor. The design issues of the digital controller are discussed, including static and dynamic characteristics. Implementation of the controller, a modified hybrid digital pulse width modulator and a single look‐up table are developed. The digital controller was implemented on a field‐programmable gate array‐based control board. Experimental results demonstrating system validity are presented for a SIDO buck converter with nominal 3.6 V input voltage, and the outputs are regulated at 1.8 and 2.2 V. Copyright © 2012 John Wiley & Sons, Ltd.     

High dynamic range pseudo–two-level digital pulse-width modulation for power-efficient RF transmitters

Radio frequency (RF) power amplification based on pulse-width modulation (PWM) has been widely discussed as a potential solution to achieve higher efficiency in RF transmitters. A digitally implemented PWM introduces a large amount of in-band distortion due to spectral aliasing. In this paper, a novel memoryless PWM modulator with a built-in anti-aliasing filter is proposed that effectively reduces the in-band distortion in digital implementation. The spectral characteristics of the proposed PWM modulator as well as the statistical properties of its output PWM signal are analytically studied. The pseudo–two-level output of the proposed modulator provides the capability to compromise between the efficiency, linearity, and complexity of transmitter, based on the given design targets. The proposed PWM method benefits from a simple circuit implementation in both digital and RF sections of the transmitter. Moreover, it preserves the low distortion property at low oversampling ratios of digital baseband. Simulations, as well as measurements, verify the performance of the proposed method.     

基于DSC控制的数字功率因数校正模块应用

数字控制技术和电力电子应用之间结合逐渐紧密,功率因数校正(PFC)是电力电子技术的一个重要应用,本文利用Freescale公司新数字信号控制器(DSC)MC56F8323,完成了基于DSC的功率因数校正模块应用研究.本文提供了PFC变换器的完整数字控制解决方案,包括改进的数字PFC算法设计、适用于数字控制特点的变换器模型分析和控制参数推导、基于DSC的PFC变换器的系统软件设计、以及PWM控制信号产生策略等,最后用一台500W实验样机验证了数字控制的优良系统性能.     

Simple implementation of control gate signals for the interleaved LLC resonant converter for high current application

A novel method of the gate signal generation for the interleaved LLC converter is proposed, which is based on the relationship between the output signal of a toggle flip‐flop having the double period of the input clock signal and the output gate signal of the LLC controller having almost half‐duty cycle. The gate signals for the master and slave converters are generated using the rising and falling edge instants from the original control gate signal of the controller, respectively. Therefore, the required 90° phase difference between two signals can be always kept at any instant and at any output load condition. Copyright © 2010 John Wiley & Sons, Ltd.     

采用或非门设计最简逻辑电路的方法

给出了采用或非门、利用卡诺图设计最简逻辑电路的方法，并用实例论证这个方法是最简捷的方法，同时也具有一般性。在以CMOS为开关器件的数字集成电路芯片的设计中，由于或非门优于与非门，故应该使用所介绍的方法，直接采用或非门设计组合逻辑电路芯片。     

Design and implementation of a hybrid DPWM under 50 ps resolution based on general‐purpose FPGA

High‐resolution pulse width modulators are used widely in different fields of electrical engineering, such as dimming of light‐emitting diode (LED) lighting, motor control, RF modulators, audio amplifiers, and switch‐mode power supplies. To realize a high‐resolution digital pulse‐width modulator (DPWM) in a limited inner system clock, a simple implementation of a hybrid DPWM with the resolution under 50 ps based on a general‐purpose field‐programmable gate array (FPGA) is described. The multiplexer device implementing the fast carry‐chain path and an AND gate controlling the selection input are used as a delay unit. The manual routing or placement is not required in the proposed approach, which just needs some conditional constraints. Some different conditional constraints influencing the monotonicity and resolution of DPWM are discussed. Finally, a 1 MHz switching frequency DPWM with 40 ps resolution is experimentally demonstrated, with high monotonicity and linearity. Further, a synchronous buck with and without this high‐resolution DPWM is experimentally compared to illustrate the regulation resolution.