共查询到20条相似文献，搜索用时 15 毫秒
1.
Tommaso Addabbo Davide De Caro Ada Fort Nicola Petra Santina Rocchi Valerio Vignoli 《International Journal of Circuit Theory and Applications》2012,40(1):1-14
In this paper we discuss the efficient implementation of pseudochaotic piecewise linear maps with high digitization accuracies, taking the R'enyi chaotic map as a reference. The proposed digital architectures are based on a novel algorithmic approach that uses carry save adders for the nonlinear arithmetic modular calculations arising when computing piecewise linear maps with a finite precision. As a result, the system can be implemented by digital circuits obtaining high throughputs, which are not dependent on the digital resolution while involving a hardware complexity linearly proportional to the number of bits used for representing the discretized state. The proposed solutions result to be particularly suitable for the implementation of pseudorandom number generators based on pseudochaos, or for the definition of efficient digital blocks that can be integrated in most of the pseudochaotic cyphers proposed in the literature. Copyright © 2010 John Wiley & Sons, Ltd. 相似文献
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A. Buonomo 《International Journal of Circuit Theory and Applications》2011,39(2):91-102
We present a nonlinear analysis of a new inductively tuned astable multivibrator obtained by connecting a timing inductor across a composite nonlinear resistor with a characteristic of N‐type, which is made up of the parallel connection of two complementary pairs of cross‐coupled MOS devices. Some possible practical applications of the circuit are also envisaged. Closed‐form expressions for the amplitude and the period of the periodic oscillation are derived in both cases when the circuit exhibits a relaxation oscillation and in the more difficult case when, due to the effect of parasitic capacitances of the devices, the circuit has an almost‐discontinuous relaxation oscillation with a nonzero switching time. The accuracy of the presented formulas, which are useful for both the analysis and design, is validated through circuit simulations and experimental results. Copyright © 2009 John Wiley & Sons, Ltd. 相似文献
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Alexandre Yakovlev Alexander Kushnerov Andrey Mokhov Reza Ramezani 《International Journal of Circuit Theory and Applications》2015,43(10):1243-1262
A new model to predict the dynamic behavior of a self‐timed autonomous digital system powered by a capacitor is derived. The model demonstrates the hyperbolic shape of the discharging process on the capacitor. It allows a symbolic analysis of the discharging process for complex digital loads comprised of series (stack) and parallel configurations of digital circuits. For example, for a stack configuration, important non‐trivial relationships between the hyperbolic discharging rates have been derived based on the knowledge of the velocity saturation index (alpha) of the semiconductor devices used in the digital part. For a realistic (modern complementary metal oxide semiconductor (CMOS) devices) value of alpha = 1.5, the discharging process for a stack of two identical circuits proceeds nearly three times slower than that of any of the stand‐alone circuits. This shows a potential way of extending the lifetime of the energy sources by means of stacking self‐timed circuits. Although the analysis is based on configurations consisting of ring oscillators in CMOS technology, the analysis method can be extended to other types of self‐timed systems and other semiconductor technologies in which the instantaneous switching activity of the digital load is determined by the instantaneous voltage levels provided by the capacitive power transfer mechanism. The analytical derivations have been validated by simulations and experiments carried out with real hardware. © 2014 The Authors. International Journal of Circuit Theory and Applications published by John Wiley & Sons, Ltd. 相似文献
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Sebastian Heunisch Lars Ohlsson Fhager Lars-Erik Wernersson 《International Journal of Circuit Theory and Applications》2020,48(1):103-114
We propose a technique for generating millimeter-wave radar waveforms using edge-triggered pulse generator circuits. By synchronizing the chip rate to the oscillation frequency of a binary control signal, a phase shift is introduced in the generated pulses. This way, the millimeter-wave signal can be phase-modulated without the need of additional circuit elements. We show that high-resolution radar waveforms with low range side lobes can be generated with this technique. Using brute-force optimization, we evaluate all possible sequences up to a sequence length of 25 chips and identify optimal waveforms for each length. Optimal sequences with the energy centered at zero delay and side lobes not exceeding unity are presented. The optimized waveforms are measured and verified using an in-house resonant tunneling diode (RTD) metal-oxide-semiconductor field-effect transistor (MOSFET) pulse generator. The matched filter response of the optimal waveforms is reproduced closely in the measurements. The results enable increased sensitivity in radar systems using coherent millimeter-wave pulse generators for low power applications, as for instance, radar gesture recognition in handheld devices. Using pulsed millimeter-wave radar systems with low duty cycles, continuously running oscillators can be avoided and systems with ultra-low power consumption are possible. 相似文献
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A. D. Grasso G. Palumbo S. Pennisi 《International Journal of Circuit Theory and Applications》2008,36(1):53-80
In this paper, design equations of the most common Nested Miller topologies are derived. Moreover, a coherent and comprehensive analytical comparison among the different topologies is also presented. In particular, after deriving design equations, following the approach previously proposed by the authors that have the phase margin as the main design parameter, the different solutions are compared by evaluating a novel figure of merit that expresses a trade‐off between gain‐bandwidth product, load capacitance and total transconductance, for equal values of phase margin. It is shown that there is no unique optimal solution as this depends on the load condition and the relative magnitude of the transconductance of each stage. From this point of view, the proposed comparison also provides useful design guidelines for the optimization of small‐signal performance. Simulations confirming the effectiveness of the comparison are also given. Copyright © 2006 John Wiley & Sons, Ltd. 相似文献
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M. Pilar Garde Antonio Lopez-Martin Jose M. Algueta Ramon G. Carvajal Jaime Ramirez-Angulo 《International Journal of Circuit Theory and Applications》2019,47(8):1199-1210
The design of a micropower class AB operational transconductance amplifier with large dynamic current to quiescent current ratio is addressed. It is based on a compact and power-efficient adaptive biasing circuit and a class AB current follower using the quasi-floating gate (QFG) technique. The amplifier has been designed and fabricated in a 0.5-μm CMOS process. Simulation and measurement results show a slew rate (SR) improvement factor versus the class A version larger than 4 for the same supply voltage and bias currents, as well as enhanced small-signal performance. 相似文献
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Aditya Japa Manoj Kumar Majumder Subhendu K. Sahoo Ramesh Vaddi 《International Journal of Circuit Theory and Applications》2020,48(4):524-538
Tunnel field-effect transistor (TFET) exhibits significant p-i-n forward leakage with the increase in drain-to-source voltage bias, and this adversely impacts the power consumption and reliability of TFET digital circuits. This work presents low-power circuit techniques that result in novel compact gates and recommends tristate gates to mitigate the leakage effects. The proposed novel compact gates and tristate gates demonstrate two and six times lower power consumption compared with conventional TFET transmission gates with enhanced reliability. Further, this work introduces a new design methodology that leverages TFET p-i-n forward leakage for hardware obfuscation applications. Utilizing the proposed design methodology, the optimization of 40% and 80% in area and power consumption of hardware security primitives like true random number generators is also accomplished. 相似文献
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Murat Alcin Ismail Koyuncu Murat Tuna Metin Varan Ihsan Pehlivan 《International Journal of Circuit Theory and Applications》2019,47(3):365-378
It is well observed that cryptographic applications have great challenges in guaranteeing high security as well as high throughput. Artificial neural network (ANN)–based chaotic true random number generator (TRNG) structure has not been unprecedented in current literature. This paper provides a novel type of high-speed TRNG based on chaos and ANN implemented in a Xilinx field-programmable gate array (FPGA) chip. The paper consists of two main parts. In the first part, chaos analyses of Pehlivan-Uyaroglu_2010 chaotic system (PUCS) have been accomplished to prove that PUCS operates in chaotic regime. So PUCS can be an efficient alternative to the entropy source for classical TRNGs. In the second part, the hardware design of the proposed TRNG has been created using VHDL in Xilinx platform. As a result, the implemented TRNG offers throughput up to 115.794 Mbps. Besides, the generated random numbers have been tested with the FIPS 140-1 and NIST 800.22 test suites. The high quality of generated true random numbers have been confirmed by passing all randomness tests. The results have shown that the proposed system can provide not only high throughput but also high quality random bit sequences for a wide variety of embedded cryptographic applications. 相似文献
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Fujihiko Matsumoto Shintaro Nakamura Hiroki Wasaki Yasuaki Noguchi 《International Journal of Circuit Theory and Applications》2004,32(4):255-274
This paper presents design of linear bipolar OTAs, which are composed of two function blocks; one is an exponential‐law circuit and the other is a core cell. Multi‐tanh cells are employed as the core cell. This kind of OTA has lower power dissipation relatively to the conventional multi‐tanh cell. According as the order of the multi‐tanh core cell becomes higher, the number of circuit realization for the core cell increases. For example, we have two OTAs for the core circuit of an emitter‐coupled pair and four OTAs for the doublet core cell. Thus, we consider the generalized OTAs for an arbitrary order n of the core cell and obtain a formula to give the realization number of the linear OTAs for n. According to the formula, there must be eight OTAs in the case of n=3. All of the eight OTAs are examined. Analysis and simulation results show that the OTAs have advantage in their characteristics, such as linear input range, power dissipation, noise, and frequency response. Copyright 2004 John Wiley & Sons, Ltd. 相似文献
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Celal Avci Ece Olcay Gunes Binboga Siddik Yarman 《International Journal of Circuit Theory and Applications》2019,47(8):1269-1292
In this paper, a novel digital phase shifter topology that achieves wideband and wide phase range is proposed. Wide frequency band operation is accomplished employing symmetrical all-pass lattice structures. Compact phase shifter size is obtained utilizing the miniaturized microwave monolithic integrated circuit (MMIC) design implementation technology. Therefore, resulting phase shifter units are suitable for various communication systems such as radar and cellular communication smart antenna arrays. This paper provides complete design equations together with design algorithm for the selected phase shift and the center frequency. Design algorithm is developed on MatLab environment. The proposed phase shifting circuit is implemented employing the commercially available 0.18-μm silicon CMOS technology. The new phase shifter topology provides 00 to 3600 phase shift range over X-band, even beyond. 相似文献
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Jesus Aguado‐Ruiz Antonio J. Lopez‐Martin Jaime Ramirez‐Angulo 《International Journal of Circuit Theory and Applications》2012,40(6):607-616
Three novel improved CMOS capacitance scaling schemes are presented and compared with some conventional schemes. The novel topologies that use a modified second‐generation current conveyor, an improved cascode current mirror and an OTA with two outputs connected in current steering configuration provide higher values of Q and better frequency responses than conventional structures using basic current mirror schemes, as the simple current mirror or cascode current mirrors. Simulation results and some measurements of a chip prototype are presented. Copyright © 2011 John Wiley & Sons, Ltd. 相似文献
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George Souliotis Costas Psychalinos 《International Journal of Circuit Theory and Applications》2007,35(2):165-173
New configurations of harmonic oscillators, realized using current amplifier blocks and only grounded capacitors, are introduced in this article. The proposed configurations are based on a grounded inductor simulator scheme and on a loop constructed from first‐order sections, respectively. Comparison with the already published topologies shows that the new configurations have attractive characteristics concerning their implementation in integrated form. Copyright © 2006 John Wiley & Sons, Ltd. 相似文献
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Khaldoon M. Mhaidat Daniel W. Hammerstrom 《International Journal of Circuit Theory and Applications》2011,39(3):299-311
In this paper, we present an efficient representation of the analog signal using the inter‐pulse interval (IPI) time. Based on this representation, methods and circuits for conversion and computation have been developed. To validate these methods and circuits, a test chip has been fabricated using a 0.35µm mixed‐signal CMOS process. Together, the circuits occupy 59.52 × 10?3mm2 of chip area and consume 8.8 mW of power from a 3.2 V supply. Test results at 10 MHz and simulations results at 100 MHz show good accuracy over ±600mV range. Copyright © 2010 John Wiley & Sons, Ltd. 相似文献
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C. Psychalinos K. Roumelioti F. A. Khanday N. A. Shah 《International Journal of Circuit Theory and Applications》2015,43(1):22-35
A first‐order Sinh‐Domain allpass filter topology is introduced in this paper. It is constructed from a class‐AB current mirror and appropriately configured non‐linear transconductor cells. Due to the inherent class‐AB nature of Sinh‐Domain filters, the proposed topology offers the capability for handling currents at levels greater than that of the dc bias current level. Also, it offers the well‐known features of companding filters such as electronic adjustment of its frequency characteristics and the capability for operation in a low‐voltage environment. In addition, a four‐phase sinusoidal oscillator design example has been provided. The behaviour of the proposed topology has been evaluated and compared with other already known configurations, where the most important performance factors have been considered. Copyright © 2013 John Wiley & Sons, Ltd. 相似文献
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George Souliotis Costas Psychalinos 《International Journal of Circuit Theory and Applications》2009,37(1):43-52
A novel current‐mode multiphase oscillator topology is introduced in this letter. This is realized by employing current amplifiers and only grounded capacitors. Attractive characteristics offered by the new topology are the electronic adjustment of the oscillation frequency, the absence of passive resistors, and the requirement of only grounded capacitors. Comparison with the corresponding already published current follower based structure shows that the proposed topology has better performance in terms of the number of required active elements, the employment of passive resistors, and the ability for electronic adjustment of the oscillation frequency. Copyright © 2008 John Wiley & Sons, Ltd. 相似文献
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Ilias Chlis Domenico Pepe Domenico Zito 《International Journal of Circuit Theory and Applications》2016,44(9):1697-1705
This paper reports a phase noise analysis in a differential Armstrong oscillator circuit topology in CMOS technology. The analytical expressions of phase noise due to flicker and thermal noise sources are derived and validated by the results obtained through SpectreRF simulations for oscillation frequencies of 1, 10, and 100 GHz. The analysis captures well the phase noise of the oscillator topology and shows the impact of flicker noise contribution as the major effect leading to phase noise degradation in nano‐scale CMOS LC oscillators. Copyright © 2016 John Wiley & Sons, Ltd. 相似文献
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Jiann-Jong Chen Yuh-Shyan Hwang Ying-Jie Liao Yitsen Ku Cheng-Chieh Yu 《International Journal of Circuit Theory and Applications》2019,47(12):1907-1921
A rail-to-rail ultra-wide bandwidth hybrid supply modulator for 5G applications is presented in this paper. The proposed supply modulator has 600-MHz bandwidth, which is the widest available bandwidth today. The hybrid supply modulator uses envelope tracking (ET) technique to achieve optimal efficiency. This circuit achieves high efficiency with wide bandwidth by combining the linear amplifier (LA) and the switching converter. The optimal size of the LA output stage provides a good tracking ability. The proposed hysteresis window circuit uses the simplified number of MOSFET that reduces the chip area and increases the efficiency of the overall system. This chip has been fabricated in TSMC 90-nm CMOS processes, and the maximum tracking ability can reach to 600-MHz sine wave. The output voltage range of the sine wave is from 0.19 to 0.79 V. The maximum load current is 122 mA. The proposed supply modulator is suitable for 5G applications. The chip area is 0.87 mm × 0.87 mm. 相似文献
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数字化电能表是数字化变电站广泛使用的设备,标准数字功率源是对其性能进行校验的主要设备。目前数字功率源输出的SV报文存在随机特性差的问题,无法满足相关国家及行业标准对数字化电能表的影响量的检测要求。针对这一问题,设计了一种基于混沌映射的随机序列生成算法,保证标准数字功率源输出报文数据丢失的随机性。硬件上通过FPGA配置光口以太网芯片输出IEC 61850-9-2序列,将芯片配置为RMII接口输出,保证报文发布时间离散度可控。测试结果表明,研制的数字功率源在丢包概率可控、报文发布时间离散度可控,且误差不超过200 ns,远小于标准中规定3μs的误差要求,满足数字化电能表异常通信状态的检测要求。该装置已应用于南方电网数字化电能表检测。 相似文献