低功耗IR-UWB接收机和LNA设计研究

在分析各种超宽带(UWB)接收机系统结构的基础上,提出了一种低功耗IR-UWB接收机结构.该结构基于非相干通信机制,使用自混频技术和脉冲宽度调制方式(PPM).在该结构中,低噪声放大器(LNA)的低功耗优化是系统低功耗实现的关键.综合分析各种宽带LNA结构,提出了一种低功耗LNA设计.该LNA采用65 nmCMOS标准...     

3.6~4.7GHz低噪声放大器

以一种经典的窄带低噪声放大器结构为基础,分析级联放大器的S参数,通过优化元件参数,获得了一种在3.6~4.7 GH z范围内具有低输入回波损耗、低噪声系数的放大器。采用标准的0.18μm RF CM O S工艺进行了设计和实现。芯片面积为0.6 mm×1.5 mm。测试结果表明:在3.6~4.7 GH z的范围内,该宽带低噪声放大器输入回波损耗小于-14 dB;噪声系数小于2.8 dB,增益大于10 dB。在1.8 V电源下功耗约为45 mW。     

Ultra-wideband CMOS low noise amplifier

A two-stage ultra-wideband CMOS low noise amplifier (LNA) is proposed. The first stage is optimised for wideband input matching and low noise figure, while the second stage is optimised to extend the -3 dB bandwidth of the overall amplifier. The combination of stages can provide lower noise figure and wider bandwidth simultaneously over that of previously reported feedback-based CMOS amplifiers. The implemented LNA shows a peak gain of 13.5 dB, more than 8.5 dB of input return loss, and a noise figure of 2.5-7.4 dB over a -3 dB bandwidth from 2 to 9 GHz with DC power consumption of 25.2 mW.     

一种用于卫星导航接收机的低噪声放大器设计

设计了一种可用于多模式卫星导航接收机的射频前端低噪声放大器,设计电路可在1.13～1.95 GHz工作,兼容了GPS,北斗及GLONOSS导航系统的工作频段。电路采用0.18 μm CMOS工艺实现。仿真结果表明,频带内S11和S22均在-10 dB以下,功率增益＞10 dB,带内最小噪声系数可达到2.2 dB,输出1 dB压缩点为-5.585 dBm,在1.8 V电源电压下,主体电路消耗12 mA电流。因此,该低频噪声放大器模块可满足当前各种导航系统的工作要求。     

CMOS宽带线性可变增益低噪声放大器设计

文章设计了一种48MHz~860MHz宽带线性可变增益低噪声放大器,该放大器采用信号相加式结构电路、控制信号转换电路和电压并联负反馈技术实现。详细分析了线性增益控制、输入宽带匹配和噪声优化方法。采用TSMC0.18μm RF CMOS工艺对电路进行设计,仿真结果表明,对数增益线性变化范围为-5dB~18dB,最小噪声系数为2.9dB,S11和S22小于-10dB,输入1dB压缩点大于-14.5dBm,在1.8V电源电压下,功耗为45mW。     

An ultra-wideband CMOS low noise amplifier for 3-5-GHz UWB system

An ultra-wideband (UWB) CMOS low noise amplifier (LNA) topology that combines a narrowband LNA with a resistive shunt-feedback is proposed. The resistive shunt-feedback provides wideband input matching with small noise figure (NF) degradation by reducing the Q-factor of the narrowband LNA input and flattens the passband gain. The proposed UWB amplifier is implemented in 0.18-/spl mu/m CMOS technology for a 3.1-5-GHz UWB system. Measurements show a -3-dB gain bandwidth of 2-4.6GHz, a minimum NF of 2.3 dB, a power gain of 9.8 dB, better than -9 dB of input matching, and an input IP3 of -7dBm, while consuming only 12.6 mW of power.     

Design of a fully differential CMOS LNA for 3.1-10.6 GHz UWB communication systems

A fully differential complementary metal oxide semiconductor （CMOS） low noise amplifier （LNA） for 3.1-10.6 GHz ultra-wideband （UWB） communication systems is presented. The LNA adopts capacitive cross-coupling common-gate （CG） topology to achieve wideband input matching and low noise figure （NF）. Inductive series-peaking is used for the LNA to obtain broadband flat gain in the whole 3.1-10.6 GHz band. Designed in 0.18 um CMOS technology, the LNA achieves an NF of 3.1-4.7 dB, an Sll of less than -10 dB, an S21 of 10.3 dB with ±0.4 dB fluctuation, and an input 3rd interception point （IIP3） of -5.1 dBm, while the current consumption is only 4.8 mA from a 1.8 V power supply. The chip area of the LNA is 1×0.94 mm^2.     

A new CMOS wideband low noise amplifier with gain control

In this paper, a new CMOS wideband low noise amplifier (LNA) is proposed that is operated within a range of 470 MHz-3 GHz with current reuse, mirror bias and a source inductive degeneration technique. A two-stage topology is adopted to implement the LNA based on the TSMC 0.18-μm RF CMOS process. Traditional wideband LNAs suffer from a fundamental trade-off in noise figure (NF), gain and source impedance matching. Therefore, we propose a new LNA which obtains good NF and gain flatness performance by integrating two kinds of wideband matching techniques and a two-stage topology. The new LNA can also achieve a tunable gain at different power consumption conditions. The measurement results at the maximum power consumption mode show that the gain is between 11.3 and 13.6 dB, the NF is less than 2.5 dB, and the third-order intercept point (IIP3) is about −3.5 dBm. The LNA consumes maximum power at about 27 mW with a 1.8 V power supply. The core area is 0.55×0.95 mm².     

Design a novel 5.8 GHz wideband low noise amplifier in CMOS technology for WLAN applications

A novel complementary metal-oxide semiconductor (CMOS) low noise amplifier (LNA) was designed in this paper for wireless local area network (WLAN) applications in the 5.8?GHz ISM band. The LNA presents low voltage and low power dissipation design integrated in TSMC 0.18?µm standard CMOS technology and achieves a gain of 15.2?dB, a noise figure of 2.5?dB and an IIP3 of ?6.5?dBm with input return loss ?38.5?dB, output return loss of ?46.1?dB while dissipating just 4.96 mW from a 1V supply voltage.     

A low power high gain UWB LNA in 0.18-μm CMOS

A low power high gain differential UWB low noise amplifier (LNA) operating at 3-5 GHz is presented.A common gate input stage is used for wideband input matching; capacitor cross coupling (CCC) and current reuse techniques are combined to achieve high gain under low power consumption. The prototypes fabricated in 0.18-μm CMOS achieve a peak power gain of 17.5 dB with a -3 dB bandwidth of 2.8-5 GHz, a measured minimum noise figure (NF) of 3.35 dB and -12.6 dBm input-referred compression point at 5 GHz, while drawing 4.4 mA from a 1.8 V supply. The peak power gain is 14 dB under a 4.5 mW power consumption (3 mA from a 1.5 V supply). The proposed differential LNA occupies an area of 1.01 mm~2 including test pads.     

采用0.18 μmCMOS工艺超宽带低噪声放大器的设计

提出了一个采用TSMC 0.18μmCMOS工艺设计的,工作频段为3.1～5.2 GHz的超宽带低噪声放大器.放大器采用了前置带通滤波器的并联负反馈共源共栅结构,并从宽带电路.高频电路器件选择等方面讨论了超宽带低噪声放大器的设计,结果表明,在整个工作频段,电路输入输出匹配S11S22均小于-14 dB,最高增益为15.92 dB,增益波动为1.13 dB,电路工作电压为1.8 V,功耗为27 mW,噪声系数NF为1.84～2.11 dB.     

A dual mode 2.4-GHz CMOS low noise amplifier employing body biasing

This paper presents a dual mode CMOS low noise amplifier (LNA) suitable for Worldwide Interoperability for Microwave Access applications, at 2.4?GHz. The design concept is based on body biasing. An off chip Digital to Analog Converter is used to generate the proper body bias voltage to control the LNA gain and linearity. Measurement results show that in the high gain mode, for V _BS?=?0.3?V, the cascode LNA, implemented in a 0.13???m CMOS standard process, exhibits a 14?dB power gain, a 3.6?dB noise figure (NF) and ?4.6?dBm of third order intercept point (IIP3) for a 4?mA current consumption under 1?V supply. Tuning V _BS to ?0.55?V, switches the LNA into the low gain mode. It achieves 8.6?dB power gain, 6.2?dB NF and 6?dBm IIP3 under a constrained power consumption of 1.7?mW.     

0.18m CMOS工艺3.1～5.2GHz低噪声放大器

基于共源级联放大器的小信号模型,详细分析了宽带放大器的输入阻抗特性和噪声特性。利用MOS晶体管的寄生容性反馈机理,采用TSMC公司标准0.18μmCMOS工艺设计实现了单片集成宽带低噪声放大器,芯片尺寸为0.6mm×1.5mm。测试结果表明,在3.1～5.2GHz频段内,S11<-15dB,S21>12dB,S22<-12dB,噪声系数NF<3.1dB。电源电压为1.8V,功耗为14mW。     

3.1～5.2GHz超宽带可变增益低噪声放大器设计

低噪声放大器是超宽带接收机系统中最重要的模块之一,设计了一种可应用于3.1～5.2GHz频段超宽带可变增益低噪声放大器。电路输入级采用共栅结构实现超宽带输入匹配,并引入电流舵结构实现了放大器的可变增益。仿真基于TSMC 0.18μm RF CMOS工艺。结果表明,在全频段电路的最大功率增益为10.5dB,增益平坦度小于0.5dB,噪声系数小于5dB,输入反射系数低于-15dB,在1.8V电源电压下,功耗为9mW。因此,该电路能够在低功耗超宽带射频接收机系统中应用。     

Noise current feedforward for noise cancellation in the wideband transformer shunt feedback low noise amplifier

A noise current feedforward (NCF) technique for noise cancellation in the wideband transformer shunt feedback (TSF) low noise amplifier (LNA) is proposed. The NCF can detect and cancel the thermal noise of the TSF network. It is also suitable to cancel those noise contributed by the passive unilateral shunt feedback networks in common current mode LNAs. Implemented in SMIC 0.18 μm CMOS process and operated in the typical radio astronomy frequency range from 0.6 GHz to 1.6 GHz, the TSF LNA that employs the NCF shows approximately 0.2–0.5 dB lower noise figure than the overwhelming resistive shunt feedback LNA that exploits a conventional noise voltage feedforward technique when consuming the same power.     

Design of Full Band UWB Common-Gate LNA

A two-stage, common-gate in cascade with cascode, ultra wideband low noise amplifier (LNA) topology is proposed for 3.1 to 10.5 GHz full band application. The common-gate first stage is adopted and optimized for low noise figure (NF) at high frequencies. The LNA implemented in 0.18 mum CMOS shows more than 10 dB input return loss, maximum gain of 16 dB, and NF of 3.8~4.0 dB over the full frequency band while dissipating 5.3 mA from 1.8 V supply.     

A Compact Wideband CMOS Low-Noise Amplifier Using Shunt Resistive-Feedback and Series Inductive-Peaking Techniques

A wideband low-noise amplifier (LNA) with shunt resistive-feedback and series inductive-peaking is proposed for wideband input matching, broadband power gain and flat noise figure (NF) response. The proposed wideband LNA is implemented in 0.18-mum CMOS technology. Measured results show that power gain is greater than 10 dB and input return loss is below -10 dB from 2 to 11.5 GHz. The IIP3 is about +3 dBm, and the NF ranges from 3.1 to 4.1 dB over the band of interest. An excellent agreement between the simulated and measured results is found and attributed to less number of passive components needed in this circuit compared with previous designs. Besides, the ratio of figure-of- merit to chip size is as high as 190 (mW^-1 /mm² ) which is the best results among all previous reported CMOS-based wideband LNA.     

High‐Gain Wideband CMOS Low Noise Amplifier with Two‐Stage Cascode and Simplified Chebyshev Filter

An ultra‐wideband low‐noise amplifier is proposed with operation up to 8.2 GHz. The amplifier is fabricated with a 0.18‐μm CMOS process and adopts a two‐stage cascode architecture and a simplified Chebyshev filter for high gain, wide band, input‐impedance matching, and low noise. The gain of 19.2 dB and minimum noise figure of 3.3 dB are measured over 3.4 to 8.2 GHz while consuming 17.3 mW of power. The Proposed UWB LNA achieves a measured power‐gain bandwidth product of 399.4 GHz.     

A wideband LNA employing gate-inductive-peaking and noise-canceling techniques in 0.18μm CMOS

正This paper presents a wideband low noise amplifier(LNA) for multi-standard radio applications.The low noise characteristic is achieved by the noise-canceling technique while the bandwidth is enhanced by gateinductive -peaking technique.High-frequency noise performance is consequently improved by the flattened gain over the entire operating frequency band.Fabricated in 0.18μm CMOS process,the LNA achieves 2.5 GHz of -3 dB bandwidth and 16 dB of gain.The gain variation is within±0.8 dB from 300 MHz to 2.2 GHz.The measured noise figure(NF) and average HP3 are 3.4 dB and -2 dBm,respectively.The proposed LNA occupies 0.39 mm2 core chip area.Operating at 1.8 V,the LNA drains a current of 11.7 mA.     

6?10 GHz ultra-wideband CMOS LNA

A two-stage matched ultra-wideband CMOS low noise amplifier (LNA) is presented. The LNA is designed to achieve a low noise figure with high voltage gain. The LNA fabricated in a 0.13 mum CMOS process shows a 3.9 dB average noise figure with a 27 dB voltage gain in the 6-10 GHz frequency band with a power consumption of 14 mW.