A GRINDING-BASED MANUFACTURING METHOD FOR SILICON WAFERS: DECOMPOSITION ANALYSIS OF WAFER SURFACES

It is difficult for the lapping-based manufacturing method currently used to manufacture the majority of silicon wafers to meet the ever-increasing demand for flatter wafers at lower costs. A grinding-based manufacturing method for silicon wafers has been investigated. It has been demonstrated that the site flatness on the ground wafers (except for a few sites at the wafer center) could meet the stringent specifications for future silicon wafers. The generation mechanisms of the dimples and bumps in the central areas on ground wafers have also been studied. This paper reports another study on the grinding-based method, aiming to reduce the cost of chemical-mechanical polishing - the final material removal process in manufacturing of silicon wafers. Using design of experiments, investigations were carried out to understand the influences of grinding process variables on the peak-to-valley values of the polished wafer surfaces. It was found that the peak-to-valley values over the entire wafer surfaces did not show any relationship with grinding process variables. However, after analyzing the surface profiles by decomposing them into different frequencies, it was observed that there is a correlation between grinding process variables and certain surface feature components. Based on this finding, it is recommended to optimize the grinding process variables by minimizing the peak-to-valley values for each surface feature component, one at a time. This methodology has not been published for wafer grinding and is of practical use to the wafer industry.     

Warping of silicon wafers subjected to back-grinding process

This study investigates warping of silicon wafers in ultra-precision grinding-based back-thinning process. By analyzing the interactions between the wafer and the vacuum chuck, together with the machining stress distributions in damage layer of ground wafer, the study establishes a mathematical model to describe wafer warping during the thinning process using the elasticity theory. The model correlates wafer warping with machining stresses, wafer final thickness, damage layer thickness, and the mechanical properties of the monocrystalline silicon. The maximum warp and the warp profile are measured on the wafers thinned to various thicknesses under different grinding conditions, and are used to verify the modeling results.     

A GRINDING-BASED MANUFACTURING METHOD FOR SILICON WAFERS: GENERATION MECHANISMS OF CENTRAL BUMPS ON GROUND WAFERS

Most integrated circuits (IC) are fabricated using silicon wafers. The continuing shrinkage of the size of IC features has imposed more and more stringent requirements on the wafer flatness. Furthermore, wafer manufacturers are under constant pressure to reduce the wafer cost. The traditional lapping-based manufacturing method is unable to satisfy the ever-increasing demand for better flatness and lower cost. Previous experimental study of a grinding-based manufacturing method has shown that excellent site flatness can be obtained on ground wafers except for a few sites at the wafer center. One cause for the poor flatness at the wafer center is the central bumps on the ground wafers. As a follow-up, this paper investigates the generation mechanisms of the central bumps on ground wafers, and provides solutions to eliminate or reduce them. The understanding and knowledge gained through this study can also be applied to the manufacturing of other semiconductor wafers (such as germanium, gallium arsenide, and silicon carbide).     

A GRINDING-BASED MANUFACTURING METHOD FOR SILICON WAFERS: GENERATION MECHANISMS OF CENTRAL BUMPS ON GROUND WAFERS

Most integrated circuits (IC) are fabricated using silicon wafers. The continuing shrinkage of the size of IC features has imposed more and more stringent requirements on the wafer flatness. Furthermore, wafer manufacturers are under constant pressure to reduce the wafer cost. The traditional lapping-based manufacturing method is unable to satisfy the ever-increasing demand for better flatness and lower cost. Previous experimental study of a grinding-based manufacturing method has shown that excellent site flatness can be obtained on ground wafers except for a few sites at the wafer center. One cause for the poor flatness at the wafer center is the central bumps on the ground wafers. As a follow-up, this paper investigates the generation mechanisms of the central bumps on ground wafers, and provides solutions to eliminate or reduce them. The understanding and knowledge gained through this study can also be applied to the manufacturing of other semiconductor wafers (such as germanium, gallium arsenide, and silicon carbide).     

工件旋转法磨削硅片的磨粒切削深度模型

半导体器件制造中,工件旋转法磨削是大尺寸硅片正面平坦化加工和背面薄化加工最广泛应用的加工方法。磨粒切削深度是反映磨削条件综合作用的磨削参量,其大小直接影响磨削工件的表面/亚表面质量,研究工件旋转法磨削的磨粒切削深度模型对于实现硅片高效率高质量磨削加工具有重要的指导意义。通过分析工件旋转法磨削过程中砂轮、磨粒和硅片之间的相对运动,建立磨粒切削深度模型,得到磨粒切削深度与砂轮直径和齿宽、加工参数以及工件表面作用位置间的数学关系。根据推导的磨粒切削深度公式,进一步研究工件旋转法磨削硅片时产生的亚表面损伤沿工件半径方向的变化趋势以及加工条件对磨削硅片亚表面损伤的影响规律,并进行试验验证。结果表明,工件旋转法磨削硅片的亚表面损伤深度沿硅片半径方向从边缘到中心逐渐减小,随着砂轮磨粒粒径、砂轮进给速度、工件转速的增大和砂轮转速的减小,加工硅片的亚表面损伤也随之变大,试验结果与模型分析结果一致。     

A new model of grit cutting depth in wafer rotational grinding considering the effect of the grinding wheel,workpiece characteristics,and grinding parameters

Wafer rotational grinding is widely employed for back-thinning and flattening of semiconducting wafers during the manufacturing process of integrated circuits. Grit cutting depth is a comprehensive indicator that characterizes overall grinding conditions, such as the wheel structure, geometry, abrasive grit size, and grinding parameters. Furthermore, grit cutting depth directly affects wafer surface/subsurface quality, grinding force, and wheel performance. The existing grit cutting depth models for wafer rotational grinding cannot provide reasonable results due to the complex grinding process under extremely small grit cutting depth. In this paper, a new grit cutting depth model for wafer rotational grinding is proposed which considers machining parameters, wheel grit shape, wheel surface topography, effective grit number, and elastic deformation of the wheel grit and the workpiece during the grinding process. In addition, based on grit cutting depth and ground surface roughness relationship, a series of grinding experiments under various grit cutting depths are conducted to produce silicon wafers with various surface roughness values and compare the predictive accuracy of the proposed model and the existing models. The results indicate that predictions obtained by the proposed model are in better agreement with the experimental results, while accuracy is improved by 40%–60% compared to the previous models.     

Forming limit diagram of aluminum/copper bi-layered tubes by bulge test

Chemo-mechanical-grinding (CMG) is a hybrid process which integrates chemical reaction and mechanical grinding between abrasives and workpiece into one process. It has been successfully applied into manufacturing process of silicon wafers where both geometric accuracy and surface quality are required. This paper aims to study the potential of CMG process in manufacturing process of single crystal sapphire wafers. The basic material removal mechanism in terms of chemical effect and mechanical effect in CMG process has been analysed based on experiment results of two different kinds of CMG wheels. The experiment results suggest that chromium oxide (Cr₂O₃) performs better than silica (SiO₂) in both material removal rate (MRR) and surface quality. It also reveals that, no matter under dry condition or wet condition, CMG is with potential to achieve excellent surface quality and impressive geometric accuracy of sapphire wafer. Meanwhile, test result by Raman spectrum shows that, by using Cr₂O₃ as abrasive, the sub-surface damage of sapphire wafer is hardly to be detected. Transmission electron microscopy (TEM) tells that the sub-surface damage, about less than 50 nm, might remain on the top surface if chemical effect is not sufficient enough to meet the balance with mechanical effect in CMG process.     

SIMULTANEOUS DOUBLE-SIDE GRINDING OF SILICON WAFERS: A REVIEW AND ANALYSIS OF EXPERIMENTAL INVESTIGATIONS

Simultaneous double-side grinding (SDSG) has become an important flattening process for manufacturing of 300 mm silicon wafers. However, the literature contains only a small number of papers on SDSG. In contrast, there are a large number of patents pertinent to this process. There is no review paper summarizing all these reported experimental results. This paper reviews the literature on experimental investigations on SDSG of silicon wafers. It first describes input variables in SDSG, and then presents their effects on output variables, covering warp, flatness, surface roughness, nanotopography, wafer-thickness variation, rotational asymmetry, grinding marks, subsurface damage, wheel wear, and process cycle time. It also discusses the definition, significance, and measurement of each of these output variables. Finally, it tabulates reported experiments to show what has and has not been reported in the literature.     

A state-of-the-art review of ductile cutting of silicon wafers for semiconductor and microelectronics industries

Silicon is a typical functional material for semiconductor and optical industry. Many hi-tech products like lenses in thermal imaging, solar cells, and some key products of semiconductor industry are made of single crystal silicon. Silicon wafers are used as substrate to build vast majority of semiconductor and microelectronic devices. To meet high surge in demand for microelectronics based products in recent years, the development of rapid and cost efficient processes is inevitable to produce silicon wafers with high-quality surface finish. The current industry uses a sequence of processes such as slicing, edge grinding, finishing, lapping, polishing, back thinning, and dicing. Most of these processes use grinding grains or abrasives for material removal. The mechanism of material removal in these processes is fracture based which imparts subsurface damage when abrasive particles penetrate into the substrate surface. Most of these traditional processes are extremely slow and inefficient for machining wafers in bulk quantity. Moreover, the depth of subsurface damage caused by these processes can be up to few microns and it is too costly and time consuming to remove this damage by heavy chemical–mechanical polishing process. Therefore, semiconductor industry requires some alternative process that is rapid and cost effective for machining silicon wafers. Ductile cutting of silicon wafer has the potential to replace the tradition wafer machining processes efficiently. If implemented effectively in industry, ductile cutting of silicon wafers should reduce the time and cost of wafer machining and consequently improve the productivity of the process. This paper reviews and discusses machining characteristics associated with ductile cutting of silicon wafers. The limitations of traditional wafer fabrication, the driving factors for switching to ductile cutting technology, basic mechanism of ductile cutting, cutting mechanics, cutting forces, surface topography, thermal aspects, and important factors affecting these machining characteristics have been discussed to give a systematic insight into the technology.     

单晶硅片磨削表面相变研究

为了揭示硅片自旋转磨削加工过程中材料的去除机理,采用显微拉曼光谱仪研究了硅片磨削表面的相变。结果表明：半精磨和精磨硅片表面存在-Si相、Si-III相、Si-IV相和Si-XII相,这表明磨削过程中Si-I相发生了高压金属相变（Si-II相）,Si-II相容易以塑性方式去除。粗磨硅片表面没有明显的多晶硅,只有少量的非晶硅出现,材料以脆性断裂方式去除。从粗磨到精磨,材料去除方式由脆性断裂去除向塑性去除过渡。粗磨向半精磨过渡时,相变强度越大,材料的塑性去除程度越大;半精磨向精磨过渡时,相变强度越小,材料的塑性去除程度越大。     

Wear analysis of electrolytically dressed wheels for finishing substrate materials

Finishing of silicon wafers is a billion dollar global business. The present process chain consists of several processes, which lead to long production times and increase the cost of the finished materials. In the recent years, several processes have been experimented as an alternate process for finishing substrate wafers with stringent specifications. However, there are no successful alternate processes, which have been adopted by the wafer processing industries. The electrolytic in-process dressing (ELID) grinding is one of the processes that has already been experimented on silicon wafers for producing mirror surface finish. However, the flatness achieved from the ELID grinding is not reported. The main influence on the flatness of the wafers during ELID grinding may be due to the wear of the grinding wheels. The wear mechanism of electrolytically dressed wheels has not been fully understood and reported. The main objective of this study is to report the wear behaviors of the wheels during thinning and fine finishing of substrate wafers. The experimental results provide the conditions for utilization of the non-linear behavior of the electrolytically dressed grinding wheels for thinning and fine finishing processes.     

湿式机械化学磨削单晶硅的软磨料砂轮及其磨削性能

针对干式机械化学磨削(Mechanical chemical grinding, MCG)单晶硅过程中易产生磨削烧伤、粉尘多、加工环境差等问题,研制一种可用于湿式MCG单晶硅的新型软磨料砂轮,并对砂轮的磨削性能及其磨削单晶硅的材料去除机理进行研究。根据湿式机械化学磨削单晶硅的加工原理和要求,制备出以二氧化硅为磨料、改性耐水树脂为结合剂的新型软磨料砂轮。采用研制的软磨料砂轮对单晶硅进行磨削试验,通过检测加工硅片的表面/亚表面质量对湿式MCG软磨料砂轮的磨削性能进行分析,并与传统金刚石砂轮、干式MCG软磨料砂轮的磨削性能进行对比。采用X射线光电子能谱仪对磨削前后硅片的表面成分进行检测,分析湿式MCG加工硅片过程中发生的化学反应。结果表明,采用湿式MCG软磨料砂轮加工硅片的表面粗糙度Ra值为0.98 nm,亚表面损伤层深度为15 nm,湿式MCG软磨料砂轮磨削硅片的表面/亚表面质量远优于传统金刚石砂轮,达到干式MCG软磨料砂轮的加工效果,可实现湿磨工况下硅片的低损伤磨削加工。在湿式MCG过程中,单晶硅、二氧化硅磨粒与水发生了化学反应,在硅片表面生成易于去除的硅酸化合物,硅酸化合物进一步通过砂...     

Surface integrity of silicon wafers in ultra precision machining

Silicon wafers are the most extensively used material for integrated circuit (IC) substrates. Before taking the form of a wafer, a single crystal silicon ingot must go through a series of machining processes, including slicing, lapping, surface grinding, edge profiling, and polishing. A key requirement of the processes is to produce extremely flat surfaces on work pieces up to 350 mm in diameter. A total thickness variation (TTV) of less than 15 μm is strictly demanded by the industry for an 0.18 μm IC process. Furthermore, the surfaces should be smooth (R_a<10 nm) and have minimum subsurface damage (<10 μm) before the final etching and polishing. The end product should have crack-free mirror surfaces with a micro-roughness less than 1.8 Å. In this paper, experiments are conducted to investigate the effects of various parameters on the subsurface damage of ground silicon wafers.     

硅片低损伤磨削砂轮及其磨削性能

针对传统金刚石砂轮磨削硅片存在的表面/亚表面损伤问题,研制了一种用于硅片化学机械磨削加工的新型常温固化结合剂软磨料砂轮。根据化学机械磨削加工原理和单晶硅的材料特性,设计的软磨料砂轮以氧化铈为磨料,二氧化硅为添加剂,氯氧镁为结合剂。研究了软磨料砂轮的制备工艺,分析了软磨料砂轮的微观组织结构和成分。通过测量加工硅片的表面粗糙度、表面微观形貌和表面/亚表面损伤,进一步研究了软磨料砂轮的磨削性能。最后,与同粒度金刚石砂轮磨削和化学机械抛光(CMP)加工的硅片进行了对比分析。结果表明,采用软磨料砂轮磨削的硅片其表面粗糙度Ra1nm,亚表面损伤仅为深度30nm的非晶层,远好于金刚石砂轮磨削硅片,接近于CMP的加工水平,实现了硅片的低损伤磨削加工。     

Understanding simultaneous double-disk grinding: operation principle and material removal kinematics in silicon wafer planarization

Simultaneous double-disk grinding (DDG) is a novel and powerful technology for precision-machining mono-crystalline silicon slices (“wafers”). With DDG the extreme degrees of planarity can be achieved, which the fabrication of micro-electronic devices with minimum lateral feature dimensions of 90 nm and below demands. In DDG, both sides of the wafer are ground simultaneously between two opposite grinding wheels on collinear spindle axes. It is a chuck-less process, in which the workpiece is machined in “free-floating” fashion. Machining kinematics, removal mechanism, and resulting wafer shape differ from those known from (chuck-mounted) single-side grinding or double-sided batch lapping, which are conventionally used in mechanical wafer shaping. This article explains the kinematics of DDG and derives the basic, method-inherent features always observed on DDG-ground wafers from simple kinematic considerations without further model assumptions: global wafer shape, center dip (“navel”), edge thickness roll-off, and symmetries. The expected results are compared with experimental data.     

Signal analysis and real-time monitoring for wafer polishing processes using the ch computing environment

There are several processes used in the silicon wafer fabrication industry to achieve the planarity necessary for photolithography requirements. Polishing is one of the important processes which influence surface roughness in the manufacturing of silicon wafers. As the level of a silicon wafer surface directly affects device line-width capability, process latitude, yield, and throughput in the fabrication of microchips, it is necessary for it to have an ultra precision surface and flatness. The surface roughness in wafer polishing is affected by many process parameters. To decrease the surface roughness of the wafer, controlling the polishing parameters is very important. Above all, a real-time monitoring technology of the polishing parameters is necessary for the control. In this study, parameters affecting the surface roughness of the silicon wafer are measured in real-time. In addition comparing the predicted value is done according to the process parameters using the artificial neural network. Through these results, we conduct research on the efficient parameters of silicon wafer polishing. Required programs are developed using the Ch computing environment.     

大尺寸硅片超精密磨削平整化加工机理与技术

在中国国家自然科学基金重大项目《先进电子制造中的重要科学技术问题研究》资助下，针对大尺寸硅片化学机械抛光(CMP)和超精密磨削平整化所涉及的“超精抛光中纳米粒子行为和化学作用及平整化原理与技术”，以300mm硅片为代表，归纳报告硅片超精密磨削加工机理、磨削平整化理论、超精密磨削表面/亚表面损伤、磨削加工工艺规律，以及大尺寸硅片超精密磨削平整化加工关键技术的研究进展。 从硅片旋转磨削过程的运动学仿真、硅片磨削过程的分子动力学仿真和硅片材料的脆性 延性转变等3方面研究了硅片的超精密磨削机理。 通过建立硅片旋转磨削过程的运动学理论模型，获得硅片旋转磨削的运动轨迹参数方程、磨纹长度、磨纹数量以及磨削稳定周期等模型，分析了磨纹间距、磨纹密度与磨削表面层质量的关系。在此基础上开发硅片旋转磨削纹理的计算机预测仿真软件对硅片超精密磨削过程进行数字模拟，通过硅片磨削实验对数字仿真结果进行实验验证。     

大直径太阳能硅片高效低损耗线切割技术研究

随着太阳能电池对大直径硅片的需求不断增加,大尺寸超薄硅片多线切割技术的发展趋势将日益明显。传统的外圆和内圆切割已经不能满足现有硅片大尺寸、小切缝、高质量和高效率的要求。本文对硅片切割方法、游离磨料多线切割基本原理、线切割硅片材料去除机理以及切割工艺因素进行了综述。     

太阳能硅片游离磨料电解磨削多线切割表面完整性研究

游离磨料多线切割是目前加工太阳能硅片的主要方法。然而,该方法切痕较深,损伤层较厚,进一步增大硅片尺寸、减小硅片厚度难度很大。游离磨料电解磨削多线切割,复合了机械磨削和电化学加工方法,通过在加工过程中给硅锭和切割线施加电场产生阳极钝化或腐蚀,可以有效降低切割负载,提高切割效率,改善硅片的表面质量。以156 mm×56 mm(8寸)、电阻率(1~3?·cm)P型多晶硅片切割为例,初步试验结果表明,采用相同的切割参数和原材料,相对于游离磨料多线切割,电解磨削多线切割硅片的弯曲度降低了3μm,分布区间集中在0~9μm之间;采用20%的Na OH溶液腐蚀硅片,表面的隐裂和深沟槽较少出现,说明硅片的表面损伤程度减轻,有利于减少后续制绒减薄量。该方法和现有游离或固结磨料多线切割技术兼容性好,设备改造成本低,工程应用前景十分广阔。     

RESPONSE SURFACE ANALYSIS OF SLICING OF SILICON INGOTS WITH FOCUS ON PHOTOVOLTAIC APPLICATION

Polycrystalline silicon wafers are widely used in Photovoltaic (PV) industry as a base material for the solar cells. The existing silicon ingot slicing methods typically provide minimum wafer thickness of 300–350 μm and a surface finish of 3–5 μm R_a while incurring considerable kerf loss of 35–40%. Consequently, efficient dicing methods need to be developed, and in the quest for developing new processes for silicon ingot slicing, the wire-EDM (electric discharge machining) is emerging as a potential process. Slicing of a 3′′ square silicon ingot into wafers of 500 μm in thickness has been performed to study the process capability. This article analyzes the effect of processing parameters on the cutting process. The objective of the experimental study is improvement in slicing speed, minimization of kerf loss and surface roughness. A central composite design-based response surface methodology (RSM) has been used to study the slicing of polycrystalline silicon ingot via wire-EDM. A zinc-coated brass wire, 100 μm in diameter, has been used as an electrode in the slicing experiments. It has been observed that the optimal selection of the process parameters results in an increase of 40–50% in the slicing rate along with a 20% reduction in the kerf loss as compared to the conventional methods. The machined surfaces on the sliced wafer were free of micro-cracks and wire material contamination, thereby making it useful for electronic applications.