Optimization-based methods for operations scheduling

The operations scheduling problem in electric power systems is to determine which generating units should be on-line and available for generation at each hour and the associated nominal generation or dispatch. This paper describes the scope of the operations scheduling problem, presents mathematical formulations to the problem, and surveys recent advances in optimization-based solution methods. It is mainly concerned with the shorter term aspects of the problem where the time horizon is of the order of a week. The unit commitment, short-term hydro scheduling, and hydro-thermal coordination problems as well as solution methods are emphasized.     

BiCMOS dynamic minimum circuit using a parallel comparison algorithm for fuzzy controllers

A BiCMOS dynamic minimum circuit using a parallel comparison algorithm for the VLSI implementation of fuzzy controllers is presented. Using BiCMOS dynamic circuits and a parallel comparison algorithm a four 4-bit-input minimum circuit, designed based on a 2 mu m BiCMOS technology shows a 7.4 ns comparison time, which is a *3 improvement in speed as compared with the CMOS circuit. In addition, this circuit has an expansion capability for realising large-scale minimum circuits.<>     

Low-voltage BiCMOS dynamic minimum circuit using a parallelcomparison algorithm for fuzzy controllers

The authors present a low-voltage BiCMOS dynamic minimum circuit using a parallel comparison algorithm for VLSI implementation of fuzzy controllers. Using low-voltage BiCMOS dynamic circuits and a parallel comparison algorithm, a four-4-bit-input minimum circuit designed, based on a 1μm BiCMOS technology, shows a 9.5ns comparison time, which is a ×2.5 improvement in speed as compared to that based on CMOS technology     

A DFE coefficient placement algorithm for sparse reverberantchannels

We develop an automated algorithm for determining the number and sparsely supported locations of coefficients in a multi-element array decision-feedback equalizer based on an estimated channel response. We aim for robustness to a wide variety of possible channel conditions, especially through taking advantage of the interplay between the MMSE-optimal feedforward and feedback filters     

An algorithm for near-optimal placement of sensor elements

An important question in array design is that of where to place the elements of a sparse array for optimal performance in terms of its ability to detect and resolve a greater number of sources than conventionally possible. In particular, it has been shown that when sensor elements are arranged in the minimum redundancy fashion, by performing an augmentation technique on the covariances obtained from the array outputs, an M element array can be made to estimate the directions of arrival of as many as M(M-1)/2 uncorrelated sources unambiguously. Constructive procedures are developed to evaluate integer locations for an array of given sensors that span a prescribed distance, such that any missing integer is expressible as the difference of two sensor locations. New upper bounds for the ratio of the square of the minimum number of elements to the spanning distance are also established     

Optimization-based congestion control for multicast communications

This article outlines an approach for multicast congestion control based on an economic model that has been successfully applied to unicast congestion control. In this model, congestion signals are interpreted as prices and congestion-controlled sessions as utility maximizing agents. A naive extension of the unicast model fails to achieve a reasonable balance between providing the incentives necessary to promote the use of multicast and ensuring that multicast sessions do not interact too aggressively with unicast sessions. We extend the model by introducing a rational definition of multicast utility. The revised model provides a basis for multicast congestion control protocols that provide incentives to use multicast but are necessarily unfair to unicast traffic. We show, however, that the degree of unfairness can be controlled by appropriately setting a design parameter with a limiting case of strict fairness     

Optimization-based transistor sizing

A combined heuristic and mathematical programming approach to transistor sizing is presented. A fast heuristic algorithm is used to obtain an initial sizing of the circuit and convert the transistor sizing problem into a nonlinear optimization problem. The problem is then solved, in spaces of reduced dimensionality, by mathematical programming techniques. To cope with the nondifferentiability of the circuit delays, the concept of generalized gradients is proposed to compute the delay sensitivities. Experiments justify the use of this sensitivity computation technique and show that the approach is a good compromise between the speed of the heuristic algorithm and the power of mathematical programming.<>     

An efficient macro-cell placement algorithm

A new approximation algorithm is presented for the efficient handling of large macro-cell placement problems. The algorithm combines simulated annealing with new features based on a hierarchical approach and a divide-and-conquer technique. Numerical results show that these features can lead to a considerable increase in efficiency of the placement algorithm without loss of effectiveness.     

A novel optimization algorithm for video placement and routing

In this paper, we propose a novel optimization algorithm for the solution of the video placement and routing problem based on Lagrangean relaxation,and decomposition. The main contribution can be stated as the use of integer programming models to obtain feasible solutions to the problem within the algorithm. Computational experimentation reveals that the use of such integer models help greatly in obtaining good quality solutions in a small amount of solution time.     

Optimization-based multifrequency test generation for analog circuits

A robust test set for analog circuits has to detect faults under maximal masking effects due to variations of circuit parameters in their tolerance box. In this paper we propose an optimization based multifrequency test generation method for detecting parametric faults in linear analog circuits. Given a set of performances and a frequency range, our approach selects the test frequencies that maximize the observability on a circuit performance of a parameter deviation under the worst masking effects of normal variations of the other parameters. Experimental results are provided and validated by HSpice simulations to illustrate the proposed approach.     

A two-dimensional placement algorithm for the layout of electronic circuits

A method is developed for the optimal placement of components or subsystems to specific locations on the backboard. The objective is to minimize the number of etches passing through unit space on the board (interconnection density) and the number of holes. This avoids the congested area on the board, makes a proper distribution of wiring and reduces the stray capacitances. X-Y coordinate wiring has been used.     

Distributed Dijkstra sparse placement routing algorithm for translucent optical networks

In this paper we study translucent optical networks as an alternative to fully transparent and fully opaque optical networks. In the former networks, a technique called sparse placement is used to overcome the lightpath blocking caused by the signal quality degradation, using much less regenerators, which must strategically be placed, in contrast to a fully opaque network. In this paper we propose a sparse placement algorithm based on two requirements. The first one is signal regeneration necessary to re-amplify, reshape, and retime the optical signals after some predefined transparent distance in order to successfully receive the signals at the destination node. The other is load balance of the traffic in the network aimed at efficient usage of the network capacity resources. We apply a distributed Dijkstra routing algorithm which dynamically changes weights of links during the process of locating regeneration capable nodes. We compare the performance of the proposed algorithm with commonly used sparse placement algorithms through simulation experiments. The benefits are such that load balancing of the network traffic is fully utilized, and with technological development it will be sufficient to equip up to 30% of nodes in the network with electronic regenerations in order to have the same performance as in an opaque network.

一种针对名义尺度变量的优化聚类算法

经典的聚类分析技术如系统聚类法和K-means等主要是处理间隔尺度的变量，而对于名义尺度变量则不适合。文章借鉴认知心理学和优化学习的思想，对名义尺度变量的聚类问题进行了研究，定义了名义尺度变量的距离度量——翻转距离，在此基础上，提出了一种目标函数优化制导的聚类算法，并演示了对名义尺度变量进行聚类的过程。实验表明，我们的算法结果可以得到合理的解释。     

BiCMOS circuit technology for high-speed DRAMs

A BiCMOS circuit technology featured by a novel bit-line sense amplifier has been developed. The bit-line sense amplifier is composed of a BiCMOS differential amplifier, the impedance-converting means featured by the CMOS current mirror circuit or the clocked CMOS inverter between the bit line and the base node of the BiCMOS differential amplifier, and a conventional CMOS flip-flop. This technology can reduce the access time to half that of a conventional CMOS DRAM access time. Applied to a 1-kb DRAM test chip, a new BiCMOS circuit technology was successfully verified. Furthermore, the sensitivity and area penalty of the new BiCMOS bit-line sense amplifier and future applications to megabit DRAMs are discussed     

Programmable BiCMOS transconductor for capacitor-transconductor filters

A simple linear programmable BiCMOS transconductor is introduced. It mainly consists of an inverting amplifier with an emitter degeneration. The driver transistor is bipolar and the equivalent resistor is an MOS transistor operating in the linear region. This transconductor can be employed in high frequency continuous-time current-mode filters. Simulated and experimental results of filters show the validity of the proposed transconductor.<>     

BiCMOS logic circuit for single-battery operation

A novel BiCMOS logic circuit is described that provides highspeed rail-to-rail operation with only one battery cell (1-1.5 V). The proposed circuit utilises a novel pull-down scheme that involves bootstrapping the base of the pull-down p-n-p bipolar junction transistor to a negative potential during the pull-down transient period. Circuit simulations have shown that the proposed circuit outperforms the transient-saturation full-swing BiCMOS and the bootstrapped bipolar circuits in terms of delay, power and cross-over capacitance for all simulated supply voltages     

BiCMOS技术

<正> BiCMOS是继CMOS后的新一代高性能VLSI工艺。CMOS以低功耗、高密度成为80年代VLSI的主流工艺。随着尺寸的逐步缩小,电路性能不断得到改进,但是当尺寸降到1μm以下时,由于载流子速度饱和等原因,它的潜力受到很大的限制。 把CMOS和Bipolar集成在同一芯片上,发挥各自的优点,克服缺点,可以使电路达到高速度、低功耗。     

Accurate delay models for digital BiCMOS

A detailed transient analysis of the MOSFET-BJT combination prevalent in digital BiCMOS gates is presented. The analysis accounts for high-level injection leading to BJT β roll-off, base pushout leading to BJT f_T roll-off, short-channel behavior of the MOS drain current, and parasitic capacitances at the base and output. Based on the transient analysis, a piecewise delay expression is derived that shows excellent agreement with measured gate delay and with SPICE simulated delay. The comparisons are made for a wide range of circuit parameters in the gate, namely, MOSFET/BJT size, load capacitance, and supply voltage for both 1- and 0.6-μm BiCMOS technologies. The model is used to optimally size gates, and to determine circuit and device design guidelines to minimize the delay degradation at reduced supply     

BiCMOS emerges for gate-arrays and memories

The integration of CMOS and bipolar technologies for applications involving gate-arrays, memories, and mixed-signal tasks is described. The specific features of bipolar and CMOS devices are reviewed, and the ways in which the best of these characteristics can be combined in BiCMOS ICs are discussed. Future trends in the applications of BiCMOS technology are discussed     

Thermal placement algorithm based on heat conduction analogy

A thermal force-directed placement algorithm, called TFPA, based on heat conduction analogy, is proposed for MCM design. TFPA begins with the transformation of the real substrate with chips into an unbounded substrate with an infinite number of chips. Then, each chip pushes every other chip with a force based on the heat conduction analogy. Thus, each chip will move in the direction of the force until the system achieves equilibrium. TFPA generates high quality placement results and maintains a cooler and uniform thermal profile, by distributing chip powers as evenly as possible. Unlike conventional force-directed algorithms, which might have serious component overlapping problems, TFPA places chips apart and only little or even no overlap occurs. In practice, the initial placements obtained by TFPA are very close to final placements.