高速VME—FASTBUS接口系统

本文介绍一种新型高速ＶＭＥ－ＦＡＳＴＢＵ接口系统，系统包括一个基于ＭＣ６８０４０处理器的ＦＡＳＴＢＵ控制器，一个ＶＭＥ双端口存储器插件和相应的软件，最后给出了测试结果。     

用于BELLE系统的FASTBUS软件包

本文介绍了一个作者设计和实现的将用地高能物理大型探测系统的数据采集系统的ＦＡＳＴＢＵＳ基本软件包。     

FASTBUS Implementation Review

For the last few years, enough has been known about the properties and capabilities of FASTBUS for it to be incorporated into the design of some experiments. As a result, despite the newness of the specification, a number of systems using FASTBUS are well advanced and a few even completed. We discuss some of these systems from several viewpoints, including why FASTBUS was chosen, how painful was the implementation and the role played by the software. FASTBUS systems in the United States, Europe and Japan are included in this review.     

A multi-function FASTBUS front-end for VAXBI computers

A versatile and high-performance interface between DEC computers based on VAXBI and FASTBUS has been designed to couple a general-purpose FASTBUS master with a specially developed intelligent module. The hardware capabilities of the interface are discussed, with particular reference to the Aleph event builder (AEB), which is a single-width FASTBUS card based on the MC68020 CPU and the MC68881 floating-point coprocessor, and the AEB-VAX interface. The software, as implemented in the Aleph experiment at the LEP (Large Electron Position) collider, is presented, covering the communication protocol, the software for the high-speed interface to the DEC DRB32 BI adapter, the AEB software, and the VAX software. The results of a performance evaluation for single-word and block transfer actions are presented     

FASTBUS Demonstration Systems

This paper will provide a demonstration of basic FASTBUS hardware and test software. The systems will include single crate segments, simple computer I/O, a fast sequencer and memory, some simple diagnostic and display devices and a UNIBUS to FASTBUS processor interface. The equipment will be set up to show the basic FASTBUS protocols and timing transactions, as well as some of the general initialization software features.     

DAQ software architecture for Aleph, a large HEP experiment

The Aleph experiment has over 700000 electronics channels and is expected to generate over 500 Mbytes of data per second. The data acquisition system (DAQ) has been designed to process information from different parts of the detector in parallel using a large number of processing elements. The authors describe the architecture of the software used to implement the readout functions and to configure the system for data acquisition. The software environment, data-flow architecture, control-flow architecture, FASTBUS management, Aleph resource manager, and Aleph partition manager are discussed     

The Vaxonline Software System at Fermilab

The VAXONLINE software system, started in late 1984, is now in use at 12 experiments at Fermilab, with at least one VAX or MicroVax. Data acquisition features now provide for the collection and combination of data from one or more sources, via a list-driven Event Builder program. Supported sources include CAMAC, FASTBUS, Front-end PDP-11's, Disk, Tape, DECnet and other processors running VAXONLINE. This paper describes the functionality provided by the VAXONLINE system, gives performance figures and discusses the ongoing program of enhancements.     

An integrated data acquisition and analysis system at GSI

The GOOSY data acquisition and analysis system has been extended to handle experimental setups and data from heavy-ion experiments at high energies. A front-end system has been designed and built. It is a VME-based multiprocessor system connected to CAMAC and FASTBUS by a standard VME subsystem bus. The system allows preanalysis and filtering of the raw data. The architecture of the system is presented, and a status report is given. Particular attention is given to integration of the front-end processors, event processing in the front-end system, and the VME network processor. Event data transfer from VME to VAX, test procedures, experimental setup control, and software used for the VME processors are briefly considered     

Multiprocessor data acquisition system for high event rates at theHeidelberg/Darmstadt crystal ball

The Heidelberg/Darmstadt crystal ball detector uses a distributed data acquisition system consisting of a FASTBUS/CAMAC front-end, the Heidelberg Polyp multiprocessor system with thirty processor modules, and an online VAX. For this heterogeneous multicomputer system a distributed real-time operating system, which allows for even rates up to 2×10⁴ events/s, was developed. It is managed user-transparently and fault-tolerantly. An overview of the system is given. The operating system is discussed, covering its general organization, event management, and control and communication. The data acquisition software is described     

A 32-Bit Computer for Large Memory Applications on the FASTBUS

A FASTBUS based 32-bit computer is being built at Los Alamos National Laboratory for use in systems requiring large fast memory in the FASTBUS environment. A separate local execution bus allows data reduction to proceed concurrently with other FASTBUS operations. The computer, which can operate in either master or slave mode, includes the National Semiconductor NS32032 chip set with demand paged memory management, floating point slave processor, interrupt control unit, timers, and time-of-day clock. The 16.0 megabytes of random access memory are interleaved to allow windowed direct memory access on and off the FASTBUS at 80 megabytes per second.     

FASTBUS State Generator a Simple, High Speed Module for Testing FASTBUS Interfaces

The FASTBUS State Generator provides a convenient method of independently controlling FASTBUS signals at normal bus speeds. Parallel generation or test of all FASTBUS lines at rates up to 25 MHz is possible using a simplified version of BASIC. The module may be programmed to emulate many of the sequential interface charateristics of standard FASTBUS devices     

快总线——新一代的高速数据获取和控制总线系统

快总线由机箱相电缆两种总线段互连而成。每一个段都是一个有自治能力的单元,可容纳多个处理机,段的操作完全是并行独立的。本文介绍快总线的发展和现状,并讨论了它的基本原理和操作。     

Design of a FASTBUS Programmable Sequencer Module and Memory Module

A programmable sequencer and a memory module have been designed and built to demonstrate high speed operation of the FASTBUS, and to study design implications of the FASTBUS specification. Both are implemented in ECL, and illustrate master and slave operation, arbitration circuit design, and logical and geographical addressing considerations.     

A dual-port FASTBUS memory to test the L3 data acquisition system

A dual-port 0.25-Mbytes (64 K×32 bits) FASTBUS memory module is described which implements a large set of functions on the Crate Port, while the Cable Port is mainly used for data transfers. Both linear and circular FIFO-like modes are software-selectable. Two pointers are available for write and read operations, respectively. The memory, successfully used to test the L3 event builders, exhibits features of an interesting, general purpose, FASTBUS module for event buffering in large data acquisition systems     

A high speed, fibre optic, link for Digital Equipment CorporationVAXes

The authors describe an optical fiber link that is used in conjunction with the CERN host interface family to connect high-performance VAXes to VMEbus or FASTBUS over distances up to 1000 m. The modular construction allows other permutations, including VAX/VAX, FASTBUS/FASTBUS, VMEbus/VMEbus, or FASTBUS/VMEbus connections, over similar distances. The link comprises two identical optical data interconnects (ODI) connected by two unidirectional multimode fibers. The ODI at each end of the link can be connected to any device conforming to the DRB32 user interface specification. The authors discuss the operation of an ODI, the testing of the optical link, and present and future ODI implementations     

FASTBUS Cable Segment Extender Based on TTL

A method to drive a FASTBUS cable segment over long distance is described. The signal level transmitted is converted from standard FASTBUS cable segment signal to a TTL differential output; the scheme increases noise immunity. In addition, the receiver has a wide tolerance of common mode range of +/-15 V. By applying a deskewing mechanism in the extender module, we have achieved more than 1010 transactions of FASTBUS without any error with a cable length of 100 m.     

A Data Acquisition Command Interface Using VAX/VMS DCL

The user interface to a data acquisition system is being developed at the Los Alamos Weapons Neutron Research Facility using the VAX/VMS command language interface DCL. Commands are being implemented which provide for system initialization and control functions and FASTBUS diagnostics. The data acquisition system incorporates the concept of a data acquisition "state" (running, halted, etc.) where a certain subset of input commands is allowed.     

A DSP based FASTBUS board for data acquisition or high leveltrigger control in DELPHI electromagnetic calorimeters

A versatile FASTBUS board that is based on fast digital signal processors (DSPs) and analog-to-digital converters is described. It has been developed for the real-time acquisition and online processing of signals produced in different electromagnetic calorimeters of the DELPHI detector at the LEP (Large Electron Positron) collider. The board contains six TMS32010 DSPs, six piggyback cards for the analog-to-digital conversion, a set of 512-word FIFO memories for data exchange between contiguous DSPs and with external devices and a 16 K×16 random-access memory for data storage, accessible both to the DSPs and to FASTBUS in an asynchronous way, with override privilege granted to the DSPs