Comparing the Impacts of the Capillary and the Molded Underfill Process on the Reliability of the Flip-Chip BGA

In the assembly process for the conventional capillary underfill (CUF) flip-chip ball grid array (FCBGA) packaging the underfill dispensing creates bottleneck. The material property of the underfill, the dispensing pattern and the curing profile all have a significant impact on the flip-chip packaging reliability. Due to the demand for high performance in the CPU, graphics and communication market, the large die size with more integrated functions using the low-K chip must meet the reliability criteria and the high thermal dissipation. In addition, the coplanarity of the flip-chip package has become a major challenge for large die packaging. This work investigates the impact of the CUF and the novel molded underfill (MUF) processes on solder bumps, low-K chip and solder ball stress, packaging coplanarity and reliability. Compared to the conventional CUF FCBGA, the proposed MUF FCBGA packaging provides superior solder bump protection, packaging coplanarity and reliability. This strong solder bump protection and high packaging reliability is due to the low coefficient of thermal expansion and high modulus of the molding compound. According to the simulation results, the maximum stress of the solder bumps, chip and packaging coplanarity of the MUF FCBGA shows a remarkable improvement over the CUF FCBGA, by 58.3%, 8.4%, and 41.8% (66 $mu {rm m}$), respectively. The results of the present study indicates that the MUF packaging is adequate for large die sizes and large packaging sizes, especially for the low-K chip and all kinds of solder bump compositions such as eutectic tin-lead, high lead, and lead free bumps.      

Reliability issues for flip-chip packages

In this article, we review the reliability issues for plastic flip-chip packages, which have become an enabling technology for future packaging development. The evolution of area-array interconnects with high I/O counts and power dissipation has made thermal deformation an important reliability concern for flip-chip packages. Significant advances have been made in understanding the thermo-mechanical behavior of flip-chip packages based on recent studies using moiré interferometry. Results from moiré studies are reviewed by focusing on the role of the underfill to show how it reduces the shear strains of the solder balls but shifts the reliability concern to delamination of the underfill interfaces. The development of the high-resolution moiré interferometry based on the phase-shift technique provided a powerful method for quantitative analysis of thermal deformation and strain distribution for high-density flip-chip packages. This method has been applied to study plastic flip-chip packages and the results and impacts on delamination at the die/underfill interface and in the underfill region above the plated through-hole via are discussed. Here a related reliability problem of die cracking during packaging assembly and test is also discussed. Finally, we discuss briefly two emerging reliability issues for advanced flip-chip packages, one on the packaging effect on Cu/low k interconnect reliability and the other on electromigration of solder balls in flip-chip packages.     

Design, assembly and reliability of large die and fine-pitch Cu/low-k flip chip package

This paper reports the design, assembly and reliability assessment of 21 × 21 mm² Cu/low-k flip chip (65 nm node) with 150 μm bump pitch and high bump density. To reduce the stress from the solder bump pad to low-k layers, Metal Redistribution Layer (RDL) and Polymer Encapsulated Dicing Lane (PEDL) are applied to the Cu/low-k wafer. Lead-free Sn2.5Ag, high-lead Pb5Sn and Cu-post/Sn37Pb bumps are evaluated as the first-level interconnects. It is found that the flip chip assembly of high-lead bumped test vehicle requires the right choice of flux and good alignment between the high-lead solder bumps and substrate pre-solder alloy to ensure proper solder bump and substrate pre-solder alloy wetting. Joint Electron Device Engineering Council (JEDEC) standard reliability is performed on the test vehicle with different first-level interconnects, underfill materials and PEDL.By integrating PEDL to the Cu/low-k chip, the reliability performance of the flip chip package has been improved by almost two times. This paper has demonstrated Moisture Sensitivity Test-Level 2 (MST-L2) qualified large die and fine-pitch Cu/low-k flip chip package. The presented results are significant for the development of flip chip packaging technologies for future advanced Cu/low-k generations.     

In process stress analysis of flip-chip assemblies during underfill cure

Low cost flip chip on board assemblies are analyzed during the underfill cure process to determine residual stress generation. In situ stress measurements are performed over the active face of the die during processing and relative in-plane stresses are measured. Experimental measurements are made using flip-chip test vehicles, based on the Sandia National Laboratories’ ATC04 assembly test chip. Four different commercial underfill materials have been evaluated and a relative comparison is presented with respect to the residual stresses produced by each underfill on the flip-chip assemblies. Significant stress variations are observed between the four underfills studied. Correlation between the glass transition temperature (T_g) and storage modulus (G^′) are made relative to residual stresses produced during underfill cure. Stress relaxation characteristics are also evaluated for the low cost flip-chip assemblies.     

Reliability evaluation of BOAC and normal pad stacked-chip packaging using low-K wafers

This work evaluates the wire bondability and the reliability tests for the stacked-chip TFBGA wire bond packaging with the Sn–4.0Ag–0.5Cu lead-free solder ball. The bonding-over-active-circuit (BOAC) pad is the top test chip and the normal pad is the bottom test chip and is combined in the stacked-chip packaging. Both test chips are 90 nm low-K dielectric with five copper layers and one layer aluminum pad and a background ranging from 775 μm to 150 μm. According to the simulation results, the maximum normal stress of low-K layer for the BOAC pad is higher than that of the normal pad by 146.4%. However, the maximum shear stress of Cu metal layer for the BOAC pad is lower than that of the normal pad by 64.2%. To compare the bonding pad strength for the BOAC and normal pad low-K wafers, this work uses the simplified two-layer model to extract the effective mechanical properties of the two bonding pad structures. The effective average Young’s modulus of the normal pad and the BOAC pad are 86 GPa and 69 GPa, respectively. The test results indicate that the effective Young’s modulus of the normal pad exceeds that of the BOAC pad by 17 GPa. The wire bondability test of the ball shear and the wire pull test results are superior to the specification by 80% and 83.75%, respectively. All stacked-chip TFBGA packaging samples underwent reliability tests, including HAST, TCT, and HTST. All the wire bondability and reliability tests passed the specification for the BOAC pad and the normal pad low-K structures. Accordingly, this work shows that the proposed stacked-chip TFBGA packaging passes the wire bondability and the reliability tests. The proposed packaging improves the electrical performance, enhances the utility of the active chip area and saves chip area through the use of low-K and BOAC chips. Furthermore, the results show that the equivalent stiffness of the bonding pad structure can be used as the bondability and reliability test index for the chip.     

超声扫描显微镜检查在倒装器件检测中的应用

随着倒装器件在型号产品中使用越来越广泛,倒装器件在使用过程中也暴露出一些问题,如底充胶分层、焊点空洞以及裂纹等,这些缺陷均能导致倒装器件失效。总结了几种倒装器件超声扫描的缺陷,重点对底充胶以及焊点进行分析。同时,论述了倒装器件超声检测中内部界面缺陷的辨别以及原理。     

Experimental study of filling behaviors in the underfill encapsulation of a flip-chip

An underfill encapsulant was used to fill the gap between the chip and the substrate around the solder joints to improve the long-term reliability of the flip-chip interconnecting system. The underfill encapsulant was filled by the capillary effect. In this study, experiments were designed to investigate the effects of bump pitch and the edge detour flow on the underfill encapsulation. The bump array was patterned on a glass plate using the lithography technology. This patterned glass plate was used to simulate a flip-chip with solder bumps. The patterned glass was bounded to a substrate to form a simulated flip-chip system. With the lithography technology, it is easy to construct the test samples for underfill flow experiments with different configuration of solder bumps. It was observed that the filling flow was affected by the bump pitch. The edge detour flow depends mainly on the arrangement of the underfill dispensing process.     

Effects of Phase Change of Pb-Free Flip-Chip Solders During Board-Level Interconnect Reflow

The impact of phase change (from solid to liquid) on the reliability of Pb-free flip-chip solders during board-level interconnect reflow is investigated. Most of the current candidates for Pb-free solder are tin-based with similar melting temperatures near 230 degC. Thus, Pb-free flip-chip solders melt again during the subsequent board-level interconnect reflow cycle. Solder volume expands more than 4% during the phase change from solid to liquid. The volumetric expansion of solder in a volume constrained by chip, substrate, and underfill creates serious reliability issues. The issues include underfill fracture and delamination from chip or substrate. Besides decreasing flip-chip interconnect reliability in fatigue, bridging through underfill cracks or delamination between neighboring flip-chip interconnects by the interjected solder leads to failures. In this paper, the volume expansion ratio of tin is experimentally measured, and a Pb-free flip-chip chip-scale package (FC-CSP) is used to observe delamination and solder bridging after solder reflow. It is demonstrated that the presence of molten solder and the interfacial failure of underfill can occur during solder reflow. Accordingly, Pb-free flip-chip packages have an additional reliability issue that has not been a concern for Pb solder packages. To quantify the effect of phase change, a flip-chip chip-scale plastic ball grid array package is modeled for nonlinear finite-element analysis. A unit-cell model is used to quantify the elongation strain of underfill and stresses at the interfaces between underfill and chip or underfill and substrate generated by volume expansion of solder. In addition, the strain energy release rate of interfacial crack between chip and underfill is also calculated     

Influence of underfill materials on the reliability of coreless flip chip package

A flip chip package was assembled by using 6-layer laminated polyimide coreless substrate, eutectic Sn37Pb solder bump, two kinds of underfill materials and Sn_3.0Ag_0.5Cu solder balls. Regarding to the yield, the peripheral solder joints were often found not to connect with the substrate due to the warpage at high temperature, modification of reflow profile was benefit to improve this issue. All the samples passed the moisture sensitive level test with a peak temperature of 260 °C and no delamination at the interface of underfill and substrate was found. In order to know the reliability of coreless flip chip package, five test items including temperature cycle test (TCT), thermal shock test (TST), highly accelerated stress test (HAST), high temperature storage test (HTST) and thermal humidity storage test (THST) were done. Both of the two underfill materials could make the samples pass the HTST and THST, however, in the case of TCT, TST and HAST, the reliability of coreless flip chip package was dominated by underfill material. A higher Young’s modules of underfill, the more die crack failures were found. Choosing a correct underfill material was the key factor for volume production of coreless flip chip package.     

A study in flip-chip UBM/bump reliability with effects of SnPb solder composition

This paper aims to investigate the electromigration phenomenon of under-bump-metallization (UBM) and solder bumps of a flip-chip package under high temperature operation life test (HTOL). UBM is a thin film Al/Ni(V)/Cu metal stack of 1.5 μm; while bump material consists of Sn/37Pb, Sn/90Pb, and Sn/95Pb solder. Current densities of 2500 and 5000 A/cm² and ambient temperatures of 150–160 °C are applied to study their impact on electromigration. It is observed that bump temperature has more significant influence than current density does to bump failures. Owing to its higher melting point characteristics and less content of Sn phase, Sn/95Pb solder bumps are observed to have 13-fold improvement in Mean-Time-To-Failure (MTTF) than that of eutectic Sn/37Pb. Individual bump resistance history is calculated to evaluate UBM/bump degradation. The measured resistance increase is from bumps with electrical current flowing upward into UBM/bump interface (cathode), while bumps having opposite current polarity cause only minor resistance change. The identified failure sites and modes from aforementioned high resistance bumps reveal structural damages at the region of UBM and UBM/bump interface in forms of solder cracking or delamination. Effects of current polarity and crowding are key factors to observed electromigration behavior of flip-chip packages.     

FEM modeling of temperature distribution of a flip-chip no-flow underfill package during solder reflow process

Flip chip on organic substrate has relied on underfill to redistribute the thermomechanical stress and to enhance the solder joint reliability. However, the conventional flip-chip underfill process involves multiple process steps and has become the bottleneck of the flip-chip process. The no-flow underfill is invented to simplify the flip-chip underfill process and to reduce the packaging cost. The no-flow underfill process requires the underfill to possess high curing latency to avoid gelation before solder reflow so to ensure the solder interconnect. Therefore, the temperature distribution of a no-flow flip-chip package during the solder reflow process is important for high assembly yield. This paper uses the finite-element method (FEM) to model the temperature distribution of a flip-chip no-flow underfill package during the solder reflow process. The kinetics of underfill curing is established using an autocatalytic reaction model obtained by DSC studies. Two approaches are developed in order to incorporate the curing kinetics of the underfill into the FEM model using iteration and a loop program. The temperature distribution across the package and across the underfill layer is studied. The effect of the presence of the underfill fillet and the influence of the chip dimension on the temperature difference in the underfill layer is discussed. The influence of the underfill curing kinetics on the modeling results is also evaluated.     

Investigation of the underfill delamination and cracking inflip-chip modules under temperature cyclic loading

In this paper, stress singularity in electronic packaging is described and three general cases are summarized. The characteristics of each stress singularity are briefed. In order to predict the likelihood of delamination at a bimaterial wedge, where two interfaces are involved, a criterion is proposed and the corresponding parameters are defined. The propagation of a crack inside a homogeneous material with the effects of delamination and stress singularity is predicted by the maximum hoop stress criterion. The proposed criteria are adopted in the analysis of a flip-chip with underfill under thermal cyclic loading. A finite element (FE) model for the package is built and the proper procedures in processing FE data are described. The proposed criterion can correctly predict the interface where delamination is more likely to occur. It can be seen that the opening stress intensity factor along the interface (or peeling stress) plays a very important role in causing interfacial failure. The analytical results are compared with experimental ones and good agreement is found. The effects of delamination and cracking inside the package on the solder balls are also mentioned. Further investigation into the fatigue model of the underfilled solder ball is discussed     

Underfill of flip chip on organic substrate: viscosity, surface tension, and contact angle

In flip-chip packaging, an underfill is dispensed on one or two adjacent sides of the die. The underfill is driven by a capillary flow to fill the gap between the die and substrate. The application of an underfill reduces the stress to solder bumps and enhances the reliability of the solder joints. Underfill materials consist of epoxy or cyanate ester resins, catalyst, crosslinker, wetting agent, pigment, and fillers. Underfill materials are highly filled with the filler loading ranging from 40% to 70%. In terms of underfill material processing, fast flow and curing are desired for high throughput. The viscosity, surface tension, and contact angle are key material properties affecting the gap filling process. In order to achieve fast filling, it is required that an underfill material has low viscosity and low contact angle at dispensing temperatures. Due to curing of an underfill material at dispensing temperature, the viscosity increases with time, which complicates the underfill flow process. The rheological behavior of several underfill materials was experimentally studied. All the underfill materials showed strong temperature dependence in viscosity before the curing. The time dependent viscosity and curing of underfill materials were examined by a dynamic time sweep test. The effects of viscosity and curing behavior of underfill materials on underfill material processing were investigated. The material with a longer gel time had more stable viscosity at room temperature, and therefore longer pot life. Experimental methods were developed to measure the surface tension and the contact angle of underfills at temperatures over 100 °C. Results showed that the contact angle for underfill on a substrate was time dependent. The interaction between underfill and substrate affects not only gap filling, but also filleting. The effect of surface energies of flip-chip substrates on wetting angles was also studied. Experiment results showed that for the same underfill, the higher the surface energy of substrate, the better the filleting.     

焊球分布模式对芯片下填充胶流动的影响

分析了在倒装芯片尺寸、相邻焊球中心之间距离相同的情况下,焊球点满布叉排排列和满布顺排排列对倒装芯片下填充流动的影响。并就焊球点布置密度不同,在顺排和叉排排列两种方式时,用相同的填充时间填充材料流动前端所走过的距离以及其分布情况进行了计算机模拟分析研究。     

Adhesion and toughening mechanisms at underfill interfaces forflip-chip-on-organic-substrate packaging

The flip chip-on-organic-substrate packaging technology utilizes a particulate reinforced epoxy as the underfill (UF) to adhere the chip to the package or board, Although the use of underfill encapsulation leads to improved reliability of flip-chip solder interconnections, delamination at various interfaces becomes a major concern for assembly yield loss and package reliability. In spite of their importance, the adhesion and fracture behaviors of the underfill interfaces have not been investigated until recently. Considerable controversy exists over the effects of underfill formulation and the adhesion and toughening mechanisms of the interfaces. The present work focuses on investigating the effects of several key variables on the interface adhesion strengths for UF/chip and UF/organic substrate systems. These variables are underfill organosilane content, filler particle content, rubber particle content, surface morphology and chemistry of the chip and organic substrates. The approach of this study is to measure the effect of these variables on the interfacial fracture energy using the double-cantilever-beam (DCB) techniques. The results demonstrate that the underfill interfacial adhesion and fracture characteristics are controlled by several distinct but competing mechanisms, such as formation of primary bonds, crack-pinning by glass fillers, debonding of glass filler from epoxy matrix (defect formation), and cavitation and shearing induced by rubber particles. Fundamental understanding of the interfacial adhesion and toughening mechanisms can provide guidance for developing new processes and materials to enhance interfacial adhesion and reliability     

Effects of pre-bump probing and bumping processes on eutectic solder bump electromigration

This paper investigates the electromigration reliability of flip chip packages with and without pre-bump wafer probing via high temperature operation life test (HTOL) using printed and electroplated bumps. Under bump metallization (UBM) of printed and electroplated bumps is a thin film of Al/Ni(V)/Cu and Ti/Cu/Ni, respectively, while the bump material consists of eutectic Sn/Pb solder. Current densities from 7380 to 20 100 A/cm² and ambient temperatures at 100, 125 and 150 °C are applied in order to study their impact on electromigration. The results reveal that the bump temperature has a higher influence than the current density when it comes to bump failures. The observed interconnect damage is from bumps with electrical current flowing upward into the UBM/bump interface (cathode). Identified failure sites and modes reveal structural damage at the region of the UBM and UBM/bump interface, in the form of solder voiding and cracking. The effects of current polarity, current crowding, and operation temperature are key factors to electromigration failures of flip chip packaging. The maximum allowable current density of the electroplated bumps is superior to the printed bumps by a factor of 3.0–3.7 times. Besides, the median time to failure (MTTF) of without-underfill packaging is preferred to that of with-underfill packaging by 1.5–2.2 times. Furthermore, the differences in MTTF between pre-bump and without pre-bump probing procedures are 2.0–19.4% and 1.6–10.3% for printed and electroplated bumps, respectively.     

Void Formation Study of Flip Chip in Package Using No-Flow Underfill

The advanced flip chip in package (FCIP) process using no-flow underfill material for high I/O density and fine-pitch interconnect applications presents challenges for an assembly process that must achieve high electrical interconnect yield and high reliability performance. With respect to high reliability, the voids formed in the underfill between solder bumps or inside the solder bumps during the no-flow underfill assembly process of FCIP devices have been typically considered one of the critical concerns affecting assembly yield and reliability performance. In this paper, the plausible causes of underfill void formation in FCIP using no-flow underfill were investigated through systematic experimentation with different types of test vehicles. For instance, the effects of process conditions, material properties, and chemical reaction between the solder bumps and no-flow underfill materials on the void formation behaviors were investigated in advanced FCIP assemblies. In this investigation, the chemical reaction between solder and underfill during the solder wetting and underfill cure process has been found to be one of the most significant factors for void formation in high I/O and fine-pitch FCIP assembly using no-flow underfill materials.     

Predictive Model for Optimized Design Parameters in Flip-Chip Packages and Assemblies

An analytical model is developed to predict the out-of- plane deformation and thermal stresses in multilayered thin stacks subjected to temperature. Coefficient of thermal expansion mismatches among the components (chip, substrate, underfill, flip-chip interconnect or C4s) are the driving force for both first and second levels interconnect reliability concerns. Die cracking and underfill delamination are the concerns for the first level interconnects while the ball grid array solder failure is the primary concern for the second level interconnects. Inadvertently, many researchers use the so-called rule of mixture in its effective moduli for the flip chip solder (C4)/underfill layer. In this study, a proper formula for effective moduli of solder (C4)/underfill layer, is presented. The classical lamination theory is used to predict the out-of-plane displacement of the chip substrate structure under temperature variation (DeltaT). The warpage and stresses resulting from the analytical formulation are compared with the 3-D finite element analysis. The study helps to design more reliable components or assemblies with the design parameters being optimized in the early stage of the development using closed form analytical solutions.     

Adhesion issues in flip-chip on organic modules

Flip chip attach on organic carriers is a novel electronic packaging assembly method which provides advantages of high input/output (I/O) counts, electrical performance and thermal dissipation. In this structure, the flip chip device is attached to organic laminate with predeposited eutectic solder. Mechanical coupling of the chip and the laminate is done via underfill encapsulant materials. As the chip size increases, the thermal mismatch between silicon and its organic carrier becomes greater. Adhesion becomes an important factor since the C4 joints fail quickly if delamination of the underfill from either chip or the solder mask interface occurs. Newly developed underfills have been studied to examine their properties, including interfacial adhesion strength, flow characteristics, void formation and cure kinetics. This paper will describe basic investigations into the properties of these underfills and also how these properties related to the overall development process. In addition, experiments were performed to determine the effects on adhesion degradation of flip chip assembly processes and materials such as IR reflow profile, flux quantity and residues. Surface treatment of both the chip and the laminate prior to encapsulation were studied to enhance underfill adhesion. Accelerated thermal cycling and highly accelerated stress testing (HAST) were conducted to compare various underfill properties and reliability responses     

Evaluation of Cu-bumps with lead-free solders for flip-chip package applications

Low cost electroplated Cu-bump with environmental friendly Sn solder was developed for flip-chip applications. The seed layer used was Ti/WN_x/Ti/Cu where WN_x was used as the Cu diffusion barrier and Ti was used to enhance the adhesion between bump and the chip pad. Thick negative photoresist (THB JSR-151N) with a high aspect ratio of 2.4 was used for electroplating of copper bump and Sn solder. The Sn solder cap was reflowed at 225° for 6 min at N₂ atmosphere. No wetting phenomenon was observed for the Sn solder as evaluated by energy-dispersed spectroscopy (EDS). The Cu-bump with Ti/WN_x/Ti/Cu seed layer not only have higher shear force than the Cu-bump with Ti/Cu seed layer but also has higher resistance to fatigue failure than the Au, SnCu, SnAg bumps.