4H-SiC normally-off vertical junction field-effect transistor with high current density

4H-silicon carbide (SiC) normally-off vertical junction field-effect transistor (JFET) is developed in a purely vertical configuration without internal lateral JFET gates. The 2.1-/spl mu/m vertical p/sup +/n junction gates are created on the side walls of deep trenches by tilted aluminum (Al) implantation. Normally-off operation with blocking voltage V/sub bl/ of 1 726 V is demonstrated with an on-state current density of 300 A/cm/sup 2/ at a drain voltage of 3 V. The low specific on-resistance R/sub on-sp/ of 3.6 m/spl Omega/cm/sup 2/ gives the V/sub bl//sup 2//R/sub on-sp/ value of 830 MW/cm/sup 2/, surpassing the past records of both unipolar and bipolar 4H-SiC power switches.     

930-V 170-m/spl Omega//spl middot/cm/sup 2/ lateral two-zone RESURF MOSFETs in 4H-SiC with NO annealing

The first lateral two-zone reduced surface field MOSFETs in 4H-SiC with NO annealing are reported. Interface properties of 4H-SiC-SiO/sub 2/ are improved, with inversion layer field-effect mobility increased to 25 cm/sup 2//V/spl middot/s, five times higher than that of dry reoxidation process, and with channel resistance significantly reduced. Devices are normally off with low leakage current. Threshold voltage is around 3 V. Blocking voltage of 930 V and specific on-resistance of 170 m/spl Omega//spl middot/cm/sup 2/ were obtained. Large-area devices with multifinger geometry are also demonstrated with scaled-up current. The output characteristics exhibit excellent linear and saturation regions.     

10-kV, 123-m/spl Omega//spl middot/cm/sup 2/ 4H-SiC power DMOSFETs

10-kV, 123-m/spl Omega//spl middot/cm/sup 2/ power DMOSFETs in 4H-SiC are demonstrated. A 42% reduction in R/sub on,sp/, compared to a previously reported value, was achieved by using an 8 /spl times/ 10/sup 14/ cm/sup -3/ doped, 85-/spl mu/m-thick drift epilayer. An effective channel mobility of 22 cm/sup 2//Vs was measured from a test MOSFET. A specific on-resistance of 123 m/spl Omega//spl middot/cm/sup 2/ were measured with a gate bias of 18 V, which corresponds to an E/sub ox/ of 3 MV/cm. A leakage current of 197 /spl mu/A was measured at a drain bias of 10 kV from a 4H-SiC DMOSFET with an active area of 4.24 /spl times/ 10/sup -3/ cm/sup 2/. A switching time of 100 ns was measured in 4.6-kV, 1.3-A switching measurements. This shows that the 4H-SiC power DMOSFETS are ideal for high-voltage, high-speed switching applications.     

A high current gain 4H-SiC NPN power bipolar junction transistor

This work reports the development of high power 4H-SiC bipolar junction transistors (BJTs) by using reduced implantation dose for p+ base contact region and annealing in nitric oxide of base-to-emitter junction passivation oxide for 2 hours at 1150/spl deg/C. The transistor blocks larger than 480 V and conducts 2.1 A (J/sub c/=239 A/cm/sup 2/) at V/sub ce/=3.4 V, corresponding to a specific on-resistance (R/sub sp on/) of 14 m/spl Omega/cm/sup 2/, based on a drift layer design of 12 /spl mu/m doped to 6/spl times/10/sup 15/cm/sup -3/. Current gain /spl beta//spl ges/35 has been achieved for collector current densities ranging from J/sub c/=40 A/cm/sup 2/ to 239 A/cm/sup 2/ (I/sub c/=2.1 A) with a peak current gain of 38 at J/sub c/=114 A/cm/sup 2/.     

High voltage (>1kV) and high current gain (32) 4H-SiC power BJTs using Al-free ohmic contact to the base

This letter reports the design and fabrication of 4H-SiC bipolar junction transistors with both high voltage (>1kV) and high dc current gain (/spl beta/=32) at a collector current level of I/sub c/=3.83A (J/sub c/=319 A/cm/sup 2/). An Al-free base ohmic contact has been used which, when compared with BJTs fabricated with Al-based base contact, shows clearly improved blocking voltage. A specific on-resistance of 17 m/spl Omega//spl middot/cm/sup 2/ has been achieved for collector current densities up to 289 A/cm/sup 2/.     

Fabrication and characterization of 11-kV normally off 4H-SiC trenched-and-implanted vertical junction FET

This letter reports the first demonstration of 101 kV trenched-and-implanted normally off 4H-SiC vertical junction field-effect transistor (TI-VJFET) with a 120 /spl mu/m /spl sim/4.9/spl times/10/sup 14/ cm/sup -3/-doped drift layer. Blocking voltages (V/sub B/) of 10 kV to 11 kV have been measured. The best specific on-resistance (R/sub SP/_/sub ON/) normalized to source active area has been determined to be 130 m/spl Omega//spl middot/cm/sup 2/. Three-dimensional computer modeling including current spreading effect shows that the TI-VJFET would have a specific resistance of 168 m/spl Omega//spl middot/cm/sup 2/ if it is scaled up substantially in size.     

1677 V, 5.7 m/spl Omega//spl middot/cm/sup 2/ 4H-SiC BJTs

This letter reports the development of a high-performance power 4H-SiC bipolar junction transistor (BJT) with, simultaneously, a high blocking voltage and a low specific on-resistance (R/spl I.bar//sub ON/). A single BJT cell with an active area of 0.61 mm/sup 2/ achieves an open base collector-to-emitter blocking voltage (V/sub ceo/) of 1677 V and conducts up to 3.2 A at a forward voltage drop of V/sub CE/=3.0 V, corresponding to a low R/spl I.bar//sub ON/ of 5.7 m/spl Omega//spl middot/cm/sup 2/ up to Jc=525 A/cm/sup 2/ and a record high value of V/sub B//sup 2//R/sub SP/spl I.bar/ON/ of 493 MW/cm/sup 2/.     

1000-V, 30-A 4H-SiC BJTs with high current gain

This paper presents the development of 1000 V, 30A bipolar junction transistor (BJT) with high dc current gain in 4H-SiC. BJT devices with an active area of 3/spl times/3 mm/sup 2/ showed a forward on-current of 30 A, which corresponds to a current density of 333 A/cm/sup 2/, at a forward voltage drop of 2 V. A common-emitter current gain of 40, along with a low specific on-resistance of 6.0m/spl Omega//spl middot/cm/sup 2/ was observed at room temperature. These results show significant improvement over state-of-the-art. High temperature current-voltage characteristics were also performed on the large-area bipolar junction transistor device. A collector current of 10A is observed at V/sub CE/=2 V and I/sub B/=600 mA at 225/spl deg/C. The on-resistance increases to 22.5 m/spl Omega//spl middot/cm/sup 2/ at higher temperatures, while the dc current gain decreases to 30 at 275/spl deg/C. A sharp avalanche behavior was observed at a collector voltage of 1000 V. Inductive switching measurements at room temperature with a power supply voltage of 500 V show fast switching with a turn-off time of about 60 ns and a turn-on time of 32 ns, which is a result of the low resistance in the base.     

Novel FRESURF LDMOSFET devices with improved BV/sub dss/-R/sub dson/

In this letter, we propose and demonstrate a novel device based on a floating reduced surface field (FRESURF) concept which allows the realization of significantly higher breakdown voltage in a thin epitaxy-based power IC technology. The newly proposed device with the floating buried layer pulled back from the source side is able to realize an enhanced breakdown voltage (BV/sub dss/) without degrading the specific on-resistance (R/sub dson/A). BV/sub dss/-R/sub dson/A values like 47 V-0.28 m/spl Omega//spl middot/cm/sup 2/ or 93 V-0.82 m/spl Omega//spl middot/cm/sup 2/ have been realized with a conventional power IC technology without any added process complexity.     

Design optimization of high breakdown voltage AlGaN-GaN power HEMT on an insulating substrate for R/sub ON/A-V/sub B/ tradeoff characteristics

High breakdown voltage AlGaN-GaN power high-electron mobility transistors (HEMTs) on an insulating substrate were designed for the power electronics application. The field plate structure was employed for high breakdown voltage. The field plate length, the insulator thickness and AlGaN layer doping concentration were design parameters for the breakdown voltage. The optimization of the contact length and contact resistivity reduction were effective to reduce the specific on-resistance. The tradeoff characteristics between the on-resistance and the breakdown voltage can be improved by the optimization of the above design parameters, and the on-resistance can be estimated to be about 0.6 m/spl Omega//spl middot/cm/sup 2/ for the breakdown voltage of 600 V. This on-resistance is almost the same as that for the device on a conductive substrate.     

Lateral RESURF MOSFET fabricated on 4H-SiC(0001/sup ~/) C-face

Lateral reduced surface field (RESURF) metal-oxide-semiconductor field-effect transistors (MOSFETs) have been fabricated on 4H-SiC(0001/sup ~/) carbon face (C-face) substrates. The channel mobility of a lateral test MOSFET on a C-face was 41 cm/sup 2//V/spl middot/s, which was much higher than 5 cm/sup 2//V/spl middot/s for that on a Si-face. The specific on-resistance of the lateral RESURF MOSFET on a C-face was 79/spl Omega/ /spl middot/ cm/sup 2/, at a gate voltage of 25 V and drain voltage of 1 V. The breakdown voltage was 460 V, which was 79% of the designed breakdown voltage of 600 V. We measured the temperature dependence of R/sub on, sp/ for the RESURF MOSFET on the C-face. The R/sub on, sp/ increased with the increase in temperature.     

Design, fabrication, and characterization of low forward drop, low leakage, 1-kV 4H-SiC JBS rectifiers

The 1-kV 4H-SiC planar junction barrier Schottky (JBS) rectifiers were designed, fabricated, and characterized. Different p+ implantation dosages and activation anneal methods were used to determine an optimum baseline process. Using the optimized process, the forward drop of our JBS rectifiers is <1.5 V while the reverse leakage current density is <1/spl times/10/sup -5/ A/cm/sup -2/. Blocking voltage>1 kV was achieved using a single-zone junction termination extension termination. It was shown experimentally that 4-/spl mu/m p-type implantation window spacing gives an optimum tradeoff between forward drop voltage and leakage current density for these rectifiers, yielding a specific on-resistance of 3 m/spl Omega//spl middot/cm/sup 2/.     

Recessed-gate structure approach toward normally off high-Voltage AlGaN/GaN HEMT for power electronics applications

A recessed-gate structure has been studied with a view to realizing normally off operation of high-voltage AlGaN/GaN high-electron mobility transistors (HEMTs) for power electronics applications. The recessed-gate structure is very attractive for realizing normally off high-voltage AlGaN/GaN HEMTs because the gate threshold voltage can be controlled by the etching depth of the recess without significant increase in on-resistance characteristics. With this structure the threshold voltage can be increased with the reduction of two-dimensional electron gas (2DEG) density only under the gate electrode without reduction of 2DEG density in the other channel regions such as the channel between drain and gate. The threshold-voltage increase was experimentally demonstrated. The threshold voltage of fabricated recessed-gate device increased to -0.14 V while the threshold voltage without the recessed-gate structure was about -4 V. The specific on-resistance of the device was maintained as low as 4 m/spl Omega//spl middot/cm/sup 2/ and the breakdown voltage was 435 V. The on-resistance and the breakdown voltage tradeoff characteristics were the same as those of normally on devices. From the viewpoint of device design, the on-resistance for the normally off device was modeled using the relationship between the AlGaN layer thickness under the gate electrode and the 2DEG density. It is found that the MIS gate structure and the recess etching without the offset region between recess edge and gate electrode will further improve the on-resistance. The simulation results show the possibility of the on-resistance below 1 m/spl Omega//spl middot/cm/sup 2/ for normally off AlGaN/GaN HEMTs operating at several hundred volts with threshold voltage up to +1 V.     

AlGaN/GaN power HFET on silicon substrate with source-via grounding (SVG) structure

We have developed a high-power AlGaN/GaN HFET fabricated on 4-in conductive Si substrate with a source-via grounding (SVG) structure. The SVG structure enables efficient chip layout and high packing density by the vertical configuration. By establishing a high-quality epitaxial technology on a Si substrate and by significantly reducing the parasitic resistance, a very low specific on-state resistance of 1.9 m/spl Omega//spl middot/cm/sup 2/ is achieved. The breakdown voltage is as high as 350 V, which is attributed to the Si substrate acting as a backside field plate. Because of reduction of the parasitic inductance, very high level of current (2.0 kA/cm/sup 2/) transients, i.e., a turn-on time of 98 ps and a turn-off time of 96 ps, are successfully measured for the first time.     

Vertical RESURF diodes manufactured by deep-trench etch and vapor-phase doping

A new technique to manufacture vertical reduced surface field (RESURF)/superjunction devices is presented, in which the alternating p-n-junctions in the drift region are formed by a combination of a trench etch and vapor-phase doping process. Electrical measurements on Schottky RESURF diodes exhibit breakdown voltages up to 160 V with an on-resistance of 182 m/spl Omega/.mm/sup 2/ using a 10 /spl mu/m n-type drift region doped at 7.5/spl middot/10/sup 15/ cm/sup -3/. We show experimentally that such a device concept is able to display specific on-resistance well below the one-dimensional silicon limit and is a good candidate to manufacture vertical power RESURF MOSFETs.     

1330 V, 67 m/spl Omega//spl middot/cm/sup 2/ 4H-SiC(0001) RESURF MOSFET

Design and fabrication of 4H-SiC(0001) lateral MOSFETs with a two-zone reduced surface field structure have been investigated. The dose dependencies of experimental breakdown voltage show good agreement with simulation. Through the optimization of implant dose, high-temperature (1700/spl deg/C) annealing after ion implantation, and reduction of channel length, a breakdown voltage of 1330 V and a low on-resistance of 67 m/spl Omega//spl middot/cm/sup 2/ have been obtained. The figure-of-merit (V/sub B//sup 2//R/sub on/) of the present device reaches 26 MW/cm/sup 2/, being the best performance among lateral MOSFETs reported. The temperature dependence of static characteristics is also presented.     

Design criteria of high-Voltage lateral RESURF JFETs on 4H-SiC

Integrated power electronics on SiC have great potential in future power electronics applications. In this paper, a novel vertical channel lateral junction field-effect transistor structure with reduced surface electric field effect is proposed for the first time on 4 H-SiC to address existing challenges in lateral power devices on SiC. Based on an experimentally proven channel design, the detailed design procedure of such a device has been investigated. Design criteria to optimize device forward blocking as well as conduction characteristics are studied. Parameter tolerance and design windows are discussed considering practical issues in device fabrication. Designs that will lead to an optimized tradeoff between device breakdown voltage and specific on-resistance are shown. With an 8-/spl mu/m-long drift region, a 1535-V breakdown voltage and 3.24 m/spl Omega//spl middot/cm/sup 2/ specific on-resistance can be achieved. This represents a figure-of-merit of 737 MW/cm/sup 2/, about 100 times higher than that of the best normally off lateral power devices reported in the literature. The proposed device can be an attractive candidate for power integrated circuit on SiC.     

8.5 m/spl Omega/ /spl middot/ cm/sub 2/ 600-V double-epitaxial MOSFETs in 4H-SiC

The most important issue in realizing a 4H-SiC vertical MOSFET is to improve the poor channel mobility at the MOS interface, which is related to high on-resistance. This letter focuses on a novel 4H-SiC vertical MOSFET device structure where a low acceptor concentration epitaxial layer is used as a channel. We call this structure a double-epitaxial MOSFET (DEMOSFET). In the structure, the p-well is composed of two p-type epitaxial layers, while an n-type region between the p-wells is formed by low-dose n-type ion implantation. A buried channel is formed at the surface of the upper p/sup $/epitaxial layer. A fabricated DEMOSFET showed an on-resistance of 8.5 m/spl Omega//spl middot/cm/sup 2/ at a gate voltage of 15 V and a blocking voltage of 600 V. This on-resistance is the lowest so far reported for a vertical MOSFET with a blocking voltage of 600 V.     

A novel technique for fabricating high reliable trench DMOSFETs using self-align technique and hydrogen annealing

A novel technique for fabricating high reliability trench DMOSFETs using three mask layers is realized to obtain cost-effective production capability, higher cell density and current driving capability, and higher reliability. This technique provides a unit cell with 2.3/spl sim/2.4 /spl mu/m pitch and a channel density of 100 Mcell/in/sup 2/. Specific on-resistance is 0.36 m/spl Omega//spl middot/cm/sup 2/ with a blocking voltage of 43 V at a gate voltage of 10 V and 5 A source-to-drain current. The time to breakdown of gate oxide grown on the hydrogen annealed trench surface is much longer than that of oxide grown on a nonhydrogen annealed trench surface.     

1300-V 6H-SiC lateral MOSFETs with two RESURF zones

A two-zone, lateral RESURF field 6H-SiC MOSFET with breakdown voltage as high as 1300 V and specific on-resistance of 160 m/spl Omega//spl middot/cm/sup 2/ has been fabricated. These MOSFETs exhibit stable and reversible breakdown indicating avalanche breakdown in SiC that has not been reported in earlier lateral SiC MOSFETs.