Semi-Analytical Modeling of Short-Channel Effects in Si and Ge Symmetrical Double-Gate MOSFETs

A simple analytical expression of the 2-D potential distribution along the channel of silicon symmetrical double-gate (DG) MOSFETs in weak inversion is derived. The analytical solution of the potential distribution is compared with the numerical solution of the 2-D Poisson's equation in terms of the channel length L, the silicon thickness t _Si, and the gate oxide thickness t _OX. The obtained results show that the analytical solution describes, with good accuracy, the potential distribution along the channel at different positions from the gate interfaces for well-designed devices when the ratio of L/t _Si is ges 2-3. Based on the 2-D extra potential induced in the silicon film due to short-channel effects (SCEs), a semi-analytical expression for the subthreshold drain current of short-channel devices is derived. From the obtained subthreshold characteristics, the extracted device parameters of the subthreshold slope, drain-induced barrier lowering, and threshold voltage are discussed. Application of the proposed model to devices with silicon replaced by germanium demonstrates that the germanium DG MOSFETs are more prone to SCEs.     

A comparative study of NEGF and DDMS models in the GAA silicon nanowire transistor

In this article, we have used quantum and semiclassical models to analyse the electrical characteristics of gate all around silicon nanowire transistor (GAA SNWT). A quantum mechanical transport approach based on non-equilibrium Green's function (NEGF) method with the use of mode space approach in the frame work of effective mass theory has been employed for this analysis. Semiclassical drift diffusion mode space (DDMS) approach has also been used for the simulation of GAA SNWT. We have studied the short-channel effects on the performance of GAA SNWT and evaluated the variation of the threshold voltage, the subthreshold slope (SS), the leakage current and the drain-induced barrier lowering (DIBL) when channel length gets shorter. The results showed that quantum mechanical effects increase the threshold voltage and decrease the leakage current, whereas it has also an impact on the SS and DIBL. We have also investigated the effects of high-κ materials as gate dielectric on the device performance.     

Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied-independent gate and symmetric-asymmetric options

Novel analytical models for subthreshold current and subthreshold slope of a generic underlap DGMOSFET are proposed. The proposed models are validated with published models, experimental data along with numerical simulation results. The reasonably good agreement shows the accuracy of the proposed model. It is demonstrated how device subthreshold leakage current and subthreshold slope values can be favorably affected by proper back gate biasing, back gate asymmetry and gate work function engineering in combination with gate underlap engineering. It is demonstrated that independent gate operation in combination with gate underlap engineering significantly reduce subthreshold leakage currents as compared to nonunderlap-tied gate DGMOSFET. With the reduction in body thickness, an improvement in subthreshold slope value of underlap 4T DGMOSFET is seen, particularly as back/front gate oxide asymmetry. Developed models demonstrate that asymmetric work function underlap 4T DGMOSFETs would have better device subthreshold slope value along with increased back gate oxide asymmetry.     

New optimized Dual-Material (DM) gate design to improve the submicron GaN-MESFETs reliability in subthreshold regime

In this paper, new Dual-Material-gate (DM) concept and optimization approach are proposed to improve the device immunity against the hot carrier and short channel effects (SCEs), and optimize the subthreshold electrical performance of the submicron Gallium Nitride (GaN)-MESFET. The 2D analytical analysis includes the modeling of the channel potential, subthreshold swing, threshold voltage, Drain-Induced Lowering Barrier (DIBL) and parasitic resistances. The influence of gate length and the work function of each gate region on subthreshold behavior was investigated using the developed analytical models. The developed analytical approaches are verified and validated by the good agreement found with the 2D numerical simulations for wide range of device parameters and bias conditions. The presented compact models are used to formulate the different objective functions, which are the pre-requisite of multi-objective genetic algorithms optimization, which will be used to optimize the device subthreshold performances. The optimized design can alleviate the critical problem and further improve the immunity of SCEs of submicron GaN-MESFET-based digital circuits for low power and high speed applications.     

Characteristics and Modeling of Sub-10-nm Planar Bulk CMOS Devices Fabricated by Lateral Source/Drain Junction Control

Sub-10-nm planar bulk CMOS devices were demonstrated by a lateral source/drain (S/D) junction control, which consists of the notched gate electrode, shallow S/D extensions, and steep halo in a reverse-order S/D formation. Furthermore, the transport properties were also evaluated by using those sub-10-nm planar bulk MOSFETs. The direct-tunneling currents between the S/D regions, with not only the gate length but also the “drain-induced tunneling modulation (DITM)” effects, are clearly observed for the sub-10-nm CMOS devices at low temperature. Moreover, a quantum mechanical simulation reveals that the tunneling currents increase with the increase in the temperatures and gate voltages, resulting in a certain amount of contribution to the subthreshold current even at 300 K. Therefore, it is strongly required that the supply voltage should be reduced to suppress the DITM effects for the sub-10-nm CMOS devices even under the room-temperature operations.     

Band-Structure Effects in Ultrascaled Silicon Nanowires

In this paper, we investigate band-structure effects on the transport properties of ultrascaled silicon nanowire FETs operating under quantum-ballistic conditions. More specifically, we expand the dispersion relationship epsiv(kappa) in a power series up to the third order in kappa² and generate the corresponding higher order operator to be used within the single-electron Hamiltonian for the solution of the Schrodinger equation. We work out a hierarchy of nonparabolic models accounting for the following: 1) the shift of the subband edges and the change in the transport effective masses; 2) the higher order Hamiltonian operator; and 3) the splitting of the fourfold unprimed subbands in nanometer-size FETs. We then compute the device turn-on characteristics, the threshold shift versus diameter, and the subthreshold slope (SS) versus gate length. By compensating for the different threshold voltages, i.e., by reducing the turn- on characteristics to the same leakage current at zero gate bias, it turns out that the current discrepancies between the most general model and the bulk-parabolic model are contained within 20%. Finally, it turns out that the nonparabolic band structure gives an improved SS at the lowest gate lengths due to a reduced source-drain tunneling, reaching up to 30% enhancement.     

Simulation of Schottky barrier MOSFETs with a coupled quantuminjection/Monte Carlo technique

A full-band Monte Carlo device simulator has been used to analyze the performance of sub-0.1 μm Schottky barrier MOSFETs. In these devices, the source and drain contacts are realized with metal silicide, and the injection of carriers is controlled by gate voltage modulation of tunneling through the source barrier. A simple model treating the silicide regions as metals, coupled with an Airy function approach for tunneling through the barrier, provides injecting boundary conditions for the Monte Carlo procedure. Simulations were carried out considering a p-channel device with 270 Å gate length for which measurements are available. Our results show that in these structures there is not a strong interaction with the oxide interface as in conventional MOS devices and carriers are injected at fairly wide angles from the source into the bulk of the device. The Monte Carlo simulations not only give good agreement with current-voltage (I-V) curves, but also easily reproduce the subthreshold behavior since all the computational power is devoted to simulation of channel particles. The simulations also clarify why these structures exhibit a large amount of leakage in subthreshold regime, due to both thermionic and tunneling emission. Computational experiments suggest ways to modify the doping profile to reduce to some extent the leakage     

Simulation of Silicon Nanowire Transistors Using Boltzmann Transport Equation Under Relaxation Time Approximation

An efficient approach for the simulation of electronic transport in nanoscale transistors is presented based on the multi-subband Boltzmann transport equation under the relaxation time approximation, which takes into account the effects of quantum confinement and quasi-ballistic transport. This approach is applied to the study of electronic transport in circular gate-all-around silicon nanowire transistors. Comparison with the nonequilibrium Green's function method shows that the new method gives reasonably accurate terminal characteristics. We study the influence of silicon body diameter and gate length on the terminal current and subthreshold slope (SS). We have found that the calculated ON current is inversely proportional to the gate length to the power 1/2, and that the silicon body diameter should be smaller than roughly 2/3 of the channel length in order to maintain the SS within 80 mV/dec.     

The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor

As MOSFET is scaled below 90 nm, many daunting challenges arise. Short-channel effects (SCEs; drain-induced barrier lowering and V_THmiddotrolloff), off-state leakage, parasitic capacitance, and resistance severely limit the performance of these transistors. New device innovations are essential to overcome these difficulties. In this paper, we propose the concept of a novel tunnel source (PNPN) n-MOSFET based on the principle of band-to- band tunneling. It is found that the PNPN n-MOSFET has the potential of steep subthreshold swing and improved Ion in addition to immunities against SCEs. Therefore, such a PNPN n-MOSFET can overcome the ever-degrading on-off characteristics of the deeply scaled conventional MOSFET. The design of the PNPN n-MOSFET was extensively examined using simulations. Devices with source-side tunneling junctions were fabricated on bulk substrates using spike anneal, and the experimental data is presented.     

绝缘体上硅FinFET亚阈值摆幅研究

在新型多栅器件栅电容模型的研究中,量子电容随着沟道长度及栅氧化层厚度的不断减小而变得越发不可忽略。推导了基于绝缘体上硅(SOI)工艺技术的鳍式场效应晶体管(FinFET)的量子电容,并通过构建囊括量子电容的内部电容网络模型推导了亚阈值摆幅。采用Matlab软件,仿真验证了量子电容对亚阈值摆幅的影响。提出了亚阈值摆幅的优化方法,为如何选取合适的器件尺寸来优化某个特定设计目标的性能提供了指导。     

Analytical threshold voltage and subthreshold swing model for TMG FinFET

An analytical modelling of the subthreshold surface potential, threshold voltage (V_T) and subthreshold swing (SS) for a triple material gate (TMG) FinFET is presented. The basis of the 3D solution is two separate 2D solutions. The FinFET is separated into two 2D structures: asymmetric triple material double gate (TMDG) and symmetric TMDG MOSFETs. Their potential distributions are obtained by solving the corresponding 2D Poisson’s equations. The potential distribution in TMG FinFET is obtained by a parameter-weighted sum of the two 2D solutions. Utilising the concept of minimum source barrier as the leakiest channel path, the minimum value of the surface potential is developed from the potential model. This leads to the derivations for the threshold voltage and SS. Furthermore, the effects of variation in gate work function and gate length are investigated for analytically developed SS and V_T models. Our models are validated against TCAD Sentaurus-simulated results and found to be quite accurate.     

Unified MOSFET compact I-V model formulation through physics-basedeffective transformation

A one-region compact I_ds model from subthreshold to saturation, which resembles the same form as the well-known long-channel model but includes all major short-channel effects (SCEs) in deep-submicron (DSM) MOSFETs, has been formulated through physics-based effective transformation. The model has 23 process-dependent fitting parameters, which requires an 11-step, one-iteration extraction procedure. The new approach to modeling channel-length modulation (CLM), subthreshold diffusion current, and edge-leakage current, all in a compact form, has been verified with the 0.25-μm experimental data. The model covers the full range of gate length (without “binning”) and bias conditions, and can be correlated to true process variables for aiding technology development     

沟道形状对无结型多栅器件性能影响探究

随着集成电路特征尺寸进入纳米尺度,摩尔定律的延续受到一定的挑战,纳米技术代的晶体管亟需全新的材料、器件结构和工艺集成技术。在器件结构方面,无结型场效应晶体管由于其近似理想的电流电压特性、优良的等比例缩小能力以及极其简单的制造工艺,受到了人们广泛的关注。通过三维数值仿真工具Synopsys Sentaurus 3DTCAD,对多栅的无结型MOS晶体管进行了数值模拟仿真。并在此基础上探究了无结型器件沟道形状对其电学特性的影响,提出了具有倒角正梯形沟道的多栅无结型晶体管结构,验证了其相较于普通无结多栅型器件更加优良的电学特性,以及栅长下降至20nm以下节点时对短沟道效应的进一步抑制作用。     

Compact modeling of short-channel effects in symmetric and asymmetric 3-T/4-T double gate MOSFETs

In this paper, a two dimensional compact model for the potential distribution of double gate MOSFETs is presented. The approach uses the evanescent method along with the assumption of a parabolic potential distribution in the direction transverse to the channel in the subthreshold region and at the threshold condition. The model introduces a characteristic length which is obtained using an explicit expression. The model may be applied to all double gate structures including both symmetric and asymmetric, 3-terminal (3-T) and 4-terminal (4-T) devices. Based on this potential distribution model, the main short-channel effects including subthreshold swing, drain induced barrier lowering, and the threshold voltage are investigated. The model shows an excellent fit to data obtained from a numerical simulator in predicting the characteristics of an arbitrary DGMOSFET.     

Atomistic Full-Band Design Study of InAs Band-to-Band Tunneling Field-Effect Transistors

Band-to-band tunneling field-effect transistors (BTBT FETs) are expected to exhibit a subthreshold swing (SS) better than the 60-mV/dec limit of conventional metal–oxide–semiconductor FETs at room temperature. Through atomistic modeling of a suite of realistically extended InAs p-i-n single-gate (SG) and dual-gate (DG) ultrathin-body (UTB) and gate-all-around nanowire (GAA NW) devices with a gate length of 20 nm, we demonstrate that such a reduced SS can only be achieved if the electrostatic potential under the gate contact is very well controlled. We find that GAA NWs keep an SS less than 60 mV/dec for diameters larger than 10 nm, while the bodies in DG and SG UTBs must be scaled down to 7 and 4 nm, respectively. Still, all the considered devices are characterized by an on current smaller than the ITRS requirements.      

Resonant tunneling transistors with controllable negative differential resistances

Three-terminal devices based on resonant tunneling through two quantum barriers separated by a quantum well are presented and analyzed theoretically. Each proposed device consists of a resonant tunneling double barrier heterostructure integrated with a Schottky barrier field-effect transistor configuration. The essential feature of these devices is the presence, in their output current-voltage (I_{D} - V_{D}) curves, of negative differential resistances controlled by a gate voltage. Because of the high-speed characteristics associated with tunnel structures, these devices could find applications in tunable millimeter-wave oscillators, negative resistance amplifiers, and high-speed digital circuits.     

Improved performance of nanoscale junctionless transistor based on gate engineering approach

In this paper, we propose an effective method to improve the electrical characteristics of dual-material-gate (DMG) junctionless transistor (JLT) based on gate engineering approach, with the example of n-type double gate (DG) JLT with total channel length down to 30 nm. The characteristics are demonstrated and compared with conventional DMG DGJLT and single-material gate (SMG) DGJLT. The results show that the novel DMG DGJLT presents superior subthreshold swing (SS), drain-induced barrier lowering (DIBL), transconductance (G_m), ON/OFF current ratio, and intrinsic delay (τ). Moreover, these unique features can be controlled by engineering the length and workfunction of the gate material. In addition, the sensitivities of the novel DMG device with respect to structural parameters are investigated.     

基于二维电势分布的一种新型复合多晶硅栅LDMOS阈值电压模型

本文提出了一种新型的复合多晶硅栅LDMOS结构.该结构引入栅工程的概念,将LDMOST的栅分为n型多晶硅栅和p型多晶硅栅两部分,从而提高器件电流驱动能力,抑制SCEs(short channel effects )和DIBL(drain-induced barrier lowering).通过求解二维泊松方程建立了复合多晶硅栅LDMOST的二维阈值电压解析模型.模型考虑了LDMOS沟道杂质浓度分布和复合栅功函数差的共同影响,具有较高的精度.与MEDICI数值模拟结果比较后,模型得以验证.     

Analytical computation of electrical parameters in GAAQWT and CNTFET with identical configuration using NEGF method

A two-dimensional quantum mechanical model is presented for calculating carrier transport in ultra-thin gate-all-around quantum wire transistor (GAAQWT) and carbon nanotube field effect transistor (CNTFET) using coupled mode space approach. Schrödinger and Poisson’s equations are self-consistently solved involving Non-Equilibrium Green’s Function (NEGF) formalism under the ballistic limit along with dissipative effects in terms of self-energy at both the source and drain ends. Effect of structural parameters on drain current, channel length modulation parameter, quantum capacitance, transconductance, subthreshold swing (SS) and drain induced barrier lowering (DIBL) are studied assuming occupancy of only a few lower sub-bands, where comparison is performed taking all other factors, biases and dimensions identical. High-k dielectric (HfO₂) independently surrounding the quantum wire (GaAs) and carbon nanotube shows higher drain current and transconductance for GAAQWT but lower quantum capacitance than that obtained for CNTFET. A smaller variation of CLM for CNFET speaks in favour of it for digital quantum circuit applications, whereas GAAQWT is suitable candidate for low-power applications. Effect of structural parameters is investigated within fabrication limit to analyse the effect on electrical characteristics under lower biasing ranges.