An FIR-Embedded Noise Filtering Method for $Delta Sigma$ Fractional-N PLL Clock Generators

This paper describes a noise filtering method for $Delta Sigma$ fractional- $N$ PLL clock generators to reduce out-of-band phase noise and improve short-term jitter performance. Use of a low-cost ring VCO mandates a wideband PLL design and complicates filtering out high-frequency quantization noise from the $Delta Sigma$ modulator. A hybrid finite impulse response (FIR) filtering technique based on a semidigital approach enables low-OSR $Delta Sigma$ modulation with robust quantization noise reduction despite circuit mismatch and nonlinearity. A prototype 1-GHz $Delta Sigma$ fractional-$N$ PLL is implemented in 0.18 $muhbox{m}$ CMOS. Experimental results show that the proposed semidigital method effectively suppresses the out-of-band quantization noise, resulting in nearly 30% reduction in short-term jitter.      

A Programmable 25-MHz to 6-GHz $K/L$ Frequency Multiplier With Digital $K_{rm vco}$ Compensation

A programmable rational-$K/L$ frequency multiplier that can synthesize any frequency between 25 MHz and 6 GHz from an input clock ranging from 1 to 5.5 GHz is presented. The architecture employs a fractional-$N$ input clock divider followed by a fractional- $N$ PLL. In contrast to conventional architectures, this allows large $K$ and $L$ , whose maximum values are limited only by the word-length of digital $SigmaDelta$ modulators. Additionally, to alleviate large $K_{rm vco}$ variation and fractional spurs, which are inevitable in wide tuning range VCOs and fractional-$N$ synthesizers, new compensation techniques are implemented without involving additional circuitry. This is an ideal solution to support a programmable serializer/deserializer on a field-programmable gate array.      

A Hybrid Spur Compensation Technique for Finite-Modulo Fractional-N Phase-Locked Loops

A finite-modulo fractional-$N$ PLL utilizing a low-bit high-order $DeltaSigma$ modulator is presented. A 4-bit fourth-order $DeltaSigma$ modulator not only performs non-dithered 16-modulo fractional-$N$ operation but also offers less spur generation with negligible quantization noise. Further spur reduction is achieved by charge compensation in the voltage domain and phase interpolation in the time domain, which significantly relaxes the dynamic range requirement of the charge pump compensation current. A 1.8–2.6 GHz fractional-$N$ PLL is implemented in 0.18 $mu{hbox {m}}$ CMOS. By employing high-order deterministic $DeltaSigma$ modulation and hybrid spur compensation, the spur level of less than $-$55 dBc is achieved when the ratio of the bandwidth to minimum frequency resolution is set to 1/4. The prototype PLL consumes 35.3 mW in which only 2.7 mW is consumed by the digital modulator and compensation circuits.      

A 100 MS/s 4 MHz Bandwidth 70 dB SNR $Delta Sigma$ ADC in 90 nm CMOS

This paper describes the results of an implementation of a high speed $Delta Sigma$ ADC in 90 nm CMOS process, which is developed for a direct-conversion digital TV receiver. The $Delta Sigma$ ADC is based on a switched-capacitor fourth-order single-loop $Delta Sigma$ modulator with a 4-bit quantizer. The ADC uses a triple sampling technique and a two-step summation scheme for low power and high speed operation. Also, a digital signal processing block, including a decimation filter, a channel selection filter and a digital programmable gain amplifier (PGA), is implemented in the same process. The decimation filter is based on a polyphase IIR filter with a decimation ratio of 5, while the channel selection filter is based on two path lattice wave digital IIR filter. The ADC achieves 69.95 dB SNR and 66.85 dB SNDR over a 4 MHz bandwidth with a sampling frequency of 100 MHz. The fabricated $Delta Sigma$ ADC and the digital signal processing block occupy 0.53$~$mm$^2$ and 0.09 mm$^{2}$, and consume 11.76 mW per channel.      

A 5-GHz CMOS Type-II PLL With Low $K_{rm VCO}$ and Extended Fine-Tuning Range

A 5-GHz dual-path integer-$N$ Type-II phase-locked loop (PLL) uses an LC voltage-controlled oscillator and softly switched varactors in an overlapped digitally controlled integral path to allow a large fine-tuning range of approximately 160 MHz while realizing a low susceptibility to noise and spurs by using a low $K_{rm VCO}$ of 3.2 MHz/V. The reference spur level is less than $-$70 dBc with a 1-MHz reference frequency and a total loop-filter capacitance of 26 pF. The measured phase noise is $-$75 and $-$115 dBc/Hz at 10-kHz and 1-MHz offsets, respectively, using a loop bandwidth of approximately 30 kHz. This 0.25-${hbox{mm}}^{2}$ PLL is fabricated in a 90-nm digital CMOS process and consumes 11 mW from a 1.2-V supply.      

Pulsed $I_{d}$– $V_{g}$ Methodology and Its Application to Electron-Trapping Characterization and Defect Density Profiling

The pulsed current–voltage ($I$– $V$) measurement technique with pulse times ranging from $sim$17 ns to $sim$ 6 ms was employed to study the effect of fast transient charging on the threshold voltage shift $Delta V_{t}$ of MOSFETs. The extracted $Delta V_{t}$ values are found to be strongly dependent on the band bending of the dielectric stack defined by the high-$kappa$ and interfacial layer dielectric constants and thicknesses, as well as applied voltages. Various hafnium-based gate stacks were found to exhibit a similar trap density profile.      

A $DeltaSigma$ Fractional-N Synthesizer With Customized Noise Shaping for WCDMA/HSDPA Applications

This paper describes a quantization noise reduction method in $DeltaSigma$ fractional-N synthesizer design based on a semidigital approach. By employing a phase shifting technique, a low power hybrid finite impulse response (FIR) filtering is realized which is suitable for RF applications. Combined with the hybrid FIR filtering, single-loop topology makes 4th-order and 5th-order $DeltaSigma$ modulators possible for the type-2 4th-order PLL. A prototype fractional-N synthesizer is implemented in 180 nm CMOS for WCDMA/HSDPA applications. Experimental results show that the proposed method can effectively suppress out-of-band phase noise to meet the phase noise mask requirements in various RF applications.      

Analysis of Clock-Jitter Effects in Continuous-Time $Delta Sigma $ Modulators Using Discrete-Time Models

This paper proposes a simple discrete-time (DT) modeling technique for the rapid, yet accurate, simulation of the effect of clock jitter on the performance of continuous-time (CT) $Delta Sigma $ modulators. The proposed DT modeling technique is derived from the impulse-invariant transform and is applicable to arbitrary-order lowpass and bandpass CT $Delta Sigma $ modulators, with single-bit or multibit feedback digital-to-analog converters (DACs) employing delayed return-to-zero (RZ) or non-return-to-zero (NRZ) rectangular pulses. Its accuracy is independent of both the power spectrum of the clock jitter and the loop transfer function of the $Delta Sigma $ modulator.      

$N times N$ Cyclic-Frequency Router With Improved Performance Based on Arrayed-Waveguide Grating

We have developed an $N times N$ cyclic-frequency router with improved performance by employing two types of modified configuration; a uniform-loss and cyclic-frequency (ULCF) arrayed-waveguide grating (AWG) and an interconnected multiple AWG. We have demonstrated a compact 50-GHz-spacing 64 $,times,$64 ULCF-AWG router with low and uniform insertion losses of 5.4–6.8 dB and frequency deviations from the grid of less than $pm {8}~{rm GHz}$. We have also demonstrated a 100-GHz-spacing 8$,times,$8 interconnected multiple-AWG router with a practical configuration, very low and uniform insertion losses of 2.3–3.4 dB, and frequency deviations from the grid of less than $pm {6}~{rm GHz}$. We discuss the suitable or realizable scale $N$ of the two types of routers by comparison with a conventional AWG router in terms of optical and dimensional performance and productivity.      

Equivalent Circuit Model for the Gate Leakage Current in Broken Down $hbox{HfO}_{2}/hbox{TaN/TiN}$ Gate Stacks

We propose an equivalent circuit model for the post-breakdown (BD) current–voltage ( $I$–$V$) characteristics in $hbox{HfO}_{2}/hbox{TaN/TiN}$ gate stacks in n-MOSFETs. The model consists of two opposite-biased diodes with series resistances and a shunt leakage path. The circuit admits analytical solution using the Lambert $W$-function and is tested for both negative and positive gate biases in the voltage range of $-$1.5 to $+$1.5 V. We also show the versatility of the proposed approach to deal with the post-BD $I$– $V$ when source and drain contacts are grounded or floating and analyze the obtained results in terms of the charge available for conduction.      

$S$ - and $C$ -Band Ultra-Compact Phase Shifters Based on All-Pass Networks

Ultra-compact phase shifters are presented. The proposed phase-shifting circuits utilize the lumped element all-pass networks. The transition frequency of the all-pass network, which determines the size of the circuit, is set to be much higher than the operating frequency. This results in a significantly small chip size of the phase shifter. To verify this methodology, 5-bit phase shifters have been fabricated in the $S$ - and $C$ -band. The $S$ -band phase shifter, with a chip size of 1.87 mm $,times,$0.87 mm (1.63 mm $^{2}$), has achieved an insertion loss of ${hbox{6.1 dB}} pm {hbox{0.6 dB}}$ and rms phase-shift error of less than 2.8$^{circ}$ in 10% bandwidth. The $C$ -band phase shifter, with a chip size of 1.72 mm $,times,$0.81 mm (1.37 mm $^{2}$), has demonstrated an insertion loss of 5.7 dB $pm$ 0.8 dB and rms phase-shift error of less than 2.3 $^{circ}$ in 10% bandwidth.      

An Analytical Method to Extract the Physical Parameters of a Solar Cell From Four Points on the Illuminated $J{-}V$ Curve

For a variety of solar cells, it is shown that the single exponential $J{-}V$ model parameters, namely—ideality factor $eta$ , parasitic series resistance $R_{s}$, parasitic shunt resistance $R_{rm sh}$, dark current $J_{0}$, and photogenerated current $J_{rm ph}$ can be extracted simultaneously from just four simple measurements of the bias points corresponding to $V_{rm oc}$, $sim!hbox{0.6}V_{rm oc}$, $J_{rm sc}$, and $sim! hbox{0.6}J_{rm sc}$ on the illuminated $J{-}V$ curve, using closed-form expressions. The extraction method avoids the measurements of the peak power point and any $dJ/dV$ (i.e., slope). The method is based on the power law $J{-}V$ model proposed recently by us.      

An Edge Missing Compensator for Fast Settling Wide Locking Range Phase-Locked Loops

An edge missing compensator (EMC) is proposed to approach the function of an ideal PD with $pm 2 ^{N-1} times 2pi $ linear range with $N$-bit EMC. A PLL implemented with a 9-bit EMC achieves 320 MHz frequency hopping within 10 $~mu{hbox {s}}$ logarithmically which is about 2.4 times faster than the conventional design. The reference spur of the PLL is ${-}{hbox {48.7~dBc}}$ and the phase noise is ${-}hbox{88.31~dBc/Hz}$ at 10 kHz offset with $K_{rm VCO}= -$ 2 GHz/V.      

A 14 mW Fractional-N PLL Modulator With a Digital Phase Detector and Frequency Switching Scheme

In this work an all-digital phase detector for a fractional-${N}$ PLL is proposed and demonstrated. The phase detector consists of a single flip-flop, which acts as an oversampled 1 bit phase quantizer. A digital sampling scheme that enables FSK modulation rates much larger than the loop bandwidth is demonstrated, without compromising on the frequency accuracy of the output signal. A prototype 2.2 GHz fractional-${N}$ synthesizer incorporating the digital phase detector and sampling scheme is presented as a proof of concept. Although the loop bandwidth is only 142 kHz, an FSK modulation rate of 927.5 kbs is achieved. The 0.7 ${hbox{mm}}^{2}$ prototype is implemented in 0.13 $mu{hbox{m}}$ CMOS consumes 14 mW from a 1.4 V supply.      

A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, ${-}$ 98 dB THD, and 79 dB SNDR

This paper describes a wideband high-linearity $Delta Sigma $ ADC. It uses noise coupling combined with time interleaving. Two versions of a two-channel time-interleaved noise-coupled $Delta Sigma $ ADC were realized in a 0.18- $mu{hbox {m}}$ CMOS technology. Noise coupling between the channels increases the effective order of the noise-shaping loops, provides dithering, and prevents tone generation in all loops. Time interleaving enhances the effects of noise coupling. Using a 1.5 V supply, the device achieved excellent linearity (${rm SFDR} > {hbox {100~dB}}$, ${rm THD}= -{hbox {98~dB}}$) and an SNDR of 79 dB in a 4.2 MHz signal band.      

High-Performance Poly-Silicon TFTs Using a High-$k$ $hbox{PrTiO}_{3}$ Gate Dielectric

In this letter, a polycrystalline-silicon thin-film transistor (poly-Si TFT) with a high- $k$ $hbox{PrTiO}_{3}$ gate dielectric is proposed for the first time. Compared to TFTs with a $hbox{Pr}_{2}hbox{O}_{3}$ gate dielectric, the electrical characteristics of poly-Si TFTs with a $hbox{PrTiO}_{3}$ gate dielectric can be significantly improved, such as lower threshold voltage, smaller subthreshold swing, higher $I_{rm on}/I_{rm off}$ current ratio, and larger field-effect mobility, even without any hydrogenation treatment. These improvements can be attributed to the high gate capacitance density and low grain-boundary trap state. All of these results suggest that the poly-Si TFT with a high- $k$ $hbox{PrTiO}_{3}$ gate dielectric is a good candidate for high-speed and low-power display driving circuit applications in flat-panel displays.      

$hbox{TiN/ZrO}_{2}$/Ti/Al Metal–Insulator–Metal Capacitors With Subnanometer CET Using ALD-Deposited $hbox{ZrO}_{2}$ for DRAM Applications

We provide the first report of the structural and electrical properties of $hbox{TiN/ZrO}_{2}$/Ti/Al metal–insulator–metal capacitor structures, where the $hbox{ZrO}_{2}$ thin film (7–8 nm) is deposited by ALD using the new zirconium precursor ZrD-04, also known as Bis(methylcyclopentadienyl) methoxymethyl. Measured capacitance–voltage ($C$– $V$) and current–voltage ( $I$–$V$) characteristics are reported for premetallization rapid thermal annealing (RTP) in $hbox{N}_{2}$ for 60 s at 400 $^{circ}hbox{C}$, 500 $^{circ}hbox{C}$, or 600 $^{ circ}hbox{C}$. For the RTP at 400 $^{circ}hbox{C}$ , we find very low leakage current densities on the order of nanoamperes per square centimeter at a gate voltage of 1 V and low capacitance equivalent thickness values of $sim$ 0.9 nm at a gate voltage of 0 V. The dielectric constant of $ hbox{ZrO}_{2}$ is 31 $pm$ 2 after RTP treatment at 400 $^{circ}hbox{C}$.      

A Phase-Locked Loop With Injection-Locked Frequency Multiplier in 0.18-$mu{hbox{m}}$ CMOS for $V$ -Band Applications

In this paper, a novel CMOS phase-locked loop (PLL) integrated with an injection-locked frequency multiplier (ILFM) that generates the $V$-band output signal is proposed. Since the proposed ILFM can generate the fifth-order harmonic frequency of the voltage-controlled oscillator (VCO) output, the operational frequency of the VCO can be reduced to only one-fifth of the desired frequency. With the loop gain smaller than unity in the ILFM, the output frequency range of the proposed PLL is from 53.04 to 58.0 GHz. The PLL is designed and fabricated in 0.18-$mu{hbox{m}}$ CMOS technology. The measured phase noises at 1- and 10-MHz offset from the carrier are $-$ 85.2 and $-{hbox{90.9 dBc}}/{hbox{Hz}}$, respectively. The reference spur level of $-{hbox{40.16 dBc}}$ is measured. The dc power dissipation of the fabricated PLL is 35.7 mW under a 1.8-V supply. It can be seen that the advantages of lower power dissipation and similar phase noise can be achieved in the proposed PLL structure. It is suitable for low-power and high-performance $V$-band applications.      

A Wideband PLL-Based G/FSK Transmitter in 0.18 $mu$m CMOS

A wideband phase-locked loop (PLL)-based G/FSK transmitter (TX) architecture is presented in this paper. In the proposed TX, the G/FSK data is applied outside the loop; hence, the data rate is not constrained by the PLL bandwidth. In addition, the PLL remains locked all the time, preventing the carrier frequency from drifting. In this architecture, the G/FSK modulation signal is generated from a proposed Sigma-Delta modulated Phase Rotator $(SigmaDelta{hbox{-PR}})$. By properly combining the multi-phase signals from the PLL output, the $SigmaDelta{hbox{-PR}}$ effectively operates as a fractional frequency divider, which can synthesize modulation signals with fine-resolution frequencies. The proposed $SigmaDelta{hbox{-PR}}$ adopts the input signal as the phase transition trigger, facilitating a glitch-free operation. The impact of the $SigmaDelta{hbox{-PR}}$ on the TX output noise is also analyzed in this paper. The proposed TX with the $SigmaDelta{hbox{-PR}}$ is digitally programmable and can generate various G/FSK signals for different applications. Fabricated in a 0.18 $muhbox{m}$ CMOS technology, the proposed TX draws 6.3 mA from a 1.4 V supply, and delivers an output power of $-$11 dBm. With a maximum data rate of 6 Mb/s, the TX achieves an energy efficiency of 1.5 nJ/bit.      

Improved Stress Reliability of Analog Metal–Insulator–Metal Capacitors Using $hbox{TiO}_{2}/hbox{ZrO}_{2}$ Dielectrics

We have studied the stress reliability of high-$kappa$ $hbox{Ni/TiO}_{2}/hbox{ZrO}_{2}/hbox{TiN}$ metal–insulator–metal capacitors under constant-voltage stress. The increasing $hbox{TiO}_{2}$ thickness on $hbox{ZrO}_{2}$ improves the 125-$^{circ}hbox{C}$ leakage current, capacitance variation $(Delta C/C)$, and long-term reliability. For a high density of 26 $hbox{fF}/mu hbox{m}^{2}$ , good extrapolated ten-year reliability of small $Delta C/ break C sim hbox{0.71}%$ is obtained for the $ hbox{Ni/10-nm-}hbox{TiO}_{2}/hbox{6.5-nm-} hbox{ZrO}_{2}/break hbox{TiN}$ device at 2.5-V operation.