Comparison of electrical characteristics between AlGaN/GaN and lattice-matched InAlN/GaN heterostructure Schottky barrier diodes

Lattice-matched Pt/Au–In_0.17Al_0.83N/GaN hetreojunction Schottky barrier diodes (SBDs) with circular planar structure have been fabricated. The electrical characteristics of InAlN/GaN SBD, such as two-dimensional electron gas (2DEG) density, turn-on voltage, Schottky barrier height, reverse breakdown voltage and the forward current-transport mechanisms, are investigated and compared with those of a conventional AlGaN/GaN SBD. The results show that, despite the higher Schottky barrier height, more dislocations in InAlN layer causes a larger leakage current and lower reverse breakdown voltage than the AlGaN/GaN SBD. The emission microscopy images of past-breakdown device suggest that a horizontal premature breakdown behavior attributed to the large leakage current happens in the InAlN/GaN SBD, differing from the vertical breakdown in the AlGaN/GaN SBD.     

采用场板和边缘终端技术的大电流Ni/4H-SiC SBDs

研究了4H-SiC低缺陷密度外延层的制造和Ni/SiC肖特基势垒二极管的正、反向电学特性。采用了偏8°4H-SiC衬底上台阶控制外延方法进行同质外延,外延温度1580℃,最后得到了低缺陷密度的3英寸外延片。采用了原子力显微镜和扫描电子显微镜进行了测试。在外延片上进行的Ni/4H-SiC肖特基势垒二极管的制造,采用了B+离子注入形成的一个非晶区域作为边缘终端,然后使用经过1000℃下退火10min的PECVD生长的SiO2作为场板介质。最终得到的Ni/4H-SiC肖特基势垒二极管的理想因子为1.03,势垒高度为1.6eV,在反向偏压1102V时,漏电流密度只有1.15×10-3A/cm2。在正向压降3.5V时得到了7.47A的大电流输出,特征导通电阻为6.22Ω.cm2。     

标准CMOS工艺集成肖特基二极管设计与实现

提出了一种在标准CMOS工艺上集成肖特基二极管的方法,并通过MPW在charted 0.35μm工艺中实现.为了减小串连电阻,肖特基的版图采用了交织方法.对所设计的肖特基二极管进行了实测得到I-V,C-V和S参数,并计算得出所测试肖特基二极管的饱和电流、势垒电压及反向击穿电压.最后给出了可用于SPICE仿真的模型.     

JTE结构4H-SiC肖特基二极管的研究

借助半导体仿真软件Silvaco,仿真一种具有结终端扩展（JTE）结构的碳化硅（SiC）肖特基二极管（SBD）。其机理是通过JTE结构降低肖特基结边缘的电场集中效应,从而优化肖特基二极管的反向耐压能力。研究JTE区深度、宽度及掺杂浓度对碳化硅肖特基二极管的反向耐压的影响。通过优化结终端结构的结构参数使碳化硅肖特基二极管的反向耐压特性达到更好的性能要求。     

Electrical characteristics of a 6H-SiC epitaxial layer grown by chemical vapor deposition on porous SiC substrate

Porous SiC (PSC) has been proposed as a buffer layer for reducing defects in epitaxial SiC layers. In this study, electrical characteristics of a 6H-SiC epitaxial layer grown by chemical vapor deposition on a porous SiC substrate (SiC-on-PSC) have been compared to those simultaneously grown on a standard SiC substrate (SiC-on-STD). Schottky barrier diodes (SBDs) have been fabricated on both epitaxial layers and then investigated with temperature-dependent current-voltage (I-V), capacitance-voltage (C-V), and deep-level transient spectroscopy (DLTS) measurements. The SBDs on both SiC-on-PSC and SiC-on-STD show about the same I-V and C-V characteristics, and at least four electron traps, i.e., B (0.75 eV), C (0.63 eV), D (0.40 eV), and E (0.16 eV), can be identically found in both SBDs by DLTS measurements. Thus, we conclude that the electrical quality of SiC-on-PSC is comparable to that of SiC-on-STD, and that the higher breakdown voltages observed in SBDs on SiC-on-PSC are not obviously related to a different defect structure.     

选区外延生长半极性GaN材料上的肖特基接触特性

半极性GaN材料的研究在光电器件和电子器件领域有重要意义.采用选区外延生长技术在Si衬底上生长半极性GaN材料,并制备肖特基势垒二极管(SBD).通过测量SBD在不同温度下的Ⅰ-Ⅴ特性曲线,观察到电流的大小随着温度的增加而增加,且受反向偏压影响,证明半极性GaN基SBD的电流传输机制为热电子场发射模型.光致发光光谱和X射线光电子能谱测试进一步表明,相比极性c面GaN材料,半极性GaN材料表面存在较高的氧杂质原子浓度和氮空位,此为半极性GaN肖特基特性偏离热电子发射模型的主要因素.     

A 4.15 kV 9.07-m/spl Omega//spl middot/cm/sup 2/ 4H-SiC Schottky-barrier diode using Mo contact annealed at high temperature

In this letter, we report the fabrication of high-voltage and low-loss 4H-SiC Schottky-barrier diodes (SBDs) with a performance close to the theoretical limit using a Mo contact annealed at high-temperature. High-temperature annealing for the Mo contact was found to be effective in controlling the Schottky-barrier height at 1.2-1.3 eV without degradation of n-factor and reverse characteristics. We successfully obtained a 1-mm/sup 2/ Mo-4H-SiC SBD with a breakdown voltage (V/sub b/) of 4.15 kV and a specific on resistance (R/sub on/) of 9.07 m/spl Omega//spl middot/cm/sup 2/, achieving a best V/sub b//sup 2//R/sub on/ value of 1898 MW/cm/sup 2/. We also obtained a 9-mm/sup 2/ Mo-4H-SiC SBD with V/sub b/ of 4.40 kV and R/sub on/ of 12.20 m/spl Omega//spl middot/cm/sup 2/.     

一种提高ESD性能的高压SBD器件结构研究

提出了一种新型SBD器件结构,并应用于高压SBD产品的研制。该结构通过在肖特基势垒区的硅表面增加一层表面缓冲掺杂层(Improved Surface Buffer Dope),将高压SBD的击穿点从常规结构的PN结保护环区域转移到平坦的肖特基势垒区,从根本上提高了器件的反向静电放电(ESD)和浪涌冲击能力。经流片验证,采用该结构的10A150VSBD产品和10A200VSBD产品均通过了反向静电放电(HBM模式)8kV的考核,达到目前业界领先水平。该结构工艺实现简单,可以应用于100V以上SBD的批量生产。     

Comparison of GaN p-i-n and Schottky rectifier performance

The performance of GaN p-i-n and Schottky rectifiers fabricated on the same wafer was investigated as a function of device size and operating temperature. There was a significant difference in reverse breakdown voltage (490 V for p-i-n diodes; 347 V for the Schottky diodes) and forward turn-on voltage (~5 V for the p-i-n diodes; ~3.5 V for the Schottky diodes). Both types of device showed a negative temperature coefficient for reverse breakdown, with value -0.34±0.05 V·K^-1     

一种隐埋缓冲掺杂层高压SBD器件新结构

提出了一种新型隐埋缓冲掺杂层(IBBD)高压SBD器件,对其工作特性进行了理论分析和模拟仿真验证.与常规高压SBD相比,该IBBD-SBD在衬底上方引入隐埋缓冲掺杂层,将反向击穿点从常规结构的PN结保护环区域转移到肖特基势垒区域,提升了反向静电释放(ESD)能力和抗反向浪涌能力,提高了器件的可靠性.与现有表面缓冲掺杂层...     

一种阳极连接P型埋层的AlGaN/GaN肖特基二极管

在传统AlGaN/GaN肖特基二极管中,阳极漏电始终是制约器件耐压提高的一个重要因素。因此文中研究了在缓冲层中生长P型埋层并与阳极相连的AlGaN/GaN肖特基二极管结构 AC-PBL FPs SBD来抑制阳极的泄漏电流。同时,在二极管的两级均加上场板来调制该器件的表面电场分布。经过仿真验证可知,该结构的阳极关断泄漏电流得到了有效抑制,同时辅助耗尽沟道内的2DEG,扩大空间电荷区,进而提高了器件的耐压特性。该结构的击穿电压为733 V,与传统GET SBD器件相比,击穿电压提高了近3.4倍,Baliga优值提升了近11.6倍,说明该器件可以应用在电力电子线路中。     

一种新型SiC SBD的高温反向恢复特性

与传统硅基功率二极管相比,碳化硅肖特基势垒二极管(SiC SBD)可提高开关频率并大幅减小开关损耗,同时有更高的耐压范围.设计并制作了具有场限环结终端和Ti肖特基接触的1.2 kV/30 A SiC SBD器件,研究了该SiC SBD在100~300℃时的反向恢复特性.实验结果表明,温度每上升100℃,SiC SBD反向电压峰值增幅为5%左右,而反向恢复电流与反向恢复时间受温度影响不大;温度每升高50℃,反向恢复损耗功率峰值降低5%.实验结果表明该SiCSBD在高温下能够稳定工作,且具有良好的反向恢复特性,适用于卫星、航空和航天探测、石油以及地热钻井探测等需要大功率、耐高温和高速器件的领域.     

采用场板和B+离子注入边缘终端技术的Ti/4H-SiC肖特基势垒二极管

采用自主外延的4H-SiC外延片,利用PECVD生长的SiO2做场板介质,B+离子注入边缘终端技术,制造了Ti/4H-SiC肖特基势垒二极管.测试结果表明,Ti/4H-SiC肖特基势垒二极管的理想因子n=1.08,势垒高度(ψe)=1.05eV,串联电阻为6.77mΩ·cm2,正向电压为4V时,电流密度达到430A/cm2.反向击穿电压大于1.1kV,室温下,反向电压为1.1kV时,反向漏电流为5.96×10-3 A/cm2.     

功率肖特基二极管反向EOS量化检测及改善

由于抗反向过压或过流冲击能力不足而导致的功率肖特基势垒二极管(SBD)的潜在失效,会影响电路的可靠性,也是器件制造中最难解决的问题.根据SBD特点和应用要求,给出了静电放电(ESD)、反向浪涌电流冲击、单脉冲雪崩能量三种抗反向过电应力(EOS)能力的量化检测方法.针对三种检测方法的特点,明确了失效机理,并从工艺参数、器件结构等方面给出了解决办法.以2 A 100 V SBD芯片为例,通过器件仿真、流片验证,给出了通过p+保护环结深、p+结浓度、外延层厚度、保护环面积等工艺和结构参数改善ESD、反向浪涌电流冲击、单脉冲雪崩能量的方法.提出了一种p+-p-保护环的结构,可提高功率SBD的抗反向瞬态冲击特性.     

Low breakdown voltage Schottky diode as voltage regulator

Experimental evidence is given showing that Ag-n-Si Schottky diodes with resistivity about 40 m?cm have steeper reverse breakdown characteristics than corresponding low-voltage p-n junction regulator diodes fabricated by local epitaxy. Avalanche multiplication in such a diode starts at 1.7 V, and the device has a low positive temperature coefficient of breakdown voltage.     

High voltage 4H-SiC Schottky barrier diodes

Characteristics of 4H-SiC Schottky barrier diodes with breakdown voltages up to 1000 V are reported for the first time. The diodes showed excellent forward I-V characteristics, with a forward voltage drop of 1.06 V at an on-state current density of 100 A/cm². The specific on-resistance for these diodes was found to be low (2×10 ^-3 Ω-cm² at room temperature) and showed a T ^1.6 variation with temperature. Titanium Schottky barrier height was determined to be 0.99 eV independent of the temperature. The breakdown voltage of the diodes was found to decrease with temperature     

High-breakdown characteristics of the InP-based heterostructurefield-effect transistor withIn0.34Al0.66As0.85Sb0.15Schottky layer

We report improved breakdown characteristics of InP-based heterostructure field-effect transistors (HFET's) utilizing In_0.34 Al_0.66As_0.85Sb_0.15 Schottky layer grown by low-pressure metalorganic chemical vapor deposition. Due to high energy bandgap and high Schottky barrier height (>0.73 eV) of the In_0.34Al_0.66As_0.85Sb_0.15 Schottky layer, high two-terminal gate-to-drain breakdown voltage of 40 V, three-terminal off-state breakdown voltage of 40 V three-terminal threshold-state breakdown voltage of 31 V, and three-terminal on-state breakdown voltage of 18 V at 300 K for In_0.75Ga_0.25As channel, are achieved. Moreover, the temperature dependence of two-terminal reverse leakage current is also investigated. The two-terminal gate-to-drain breakdown voltage is up to 36 V at 420 K. A maximum extrinsic transconductance of 216 mS/mm is obtained with a gate length of 1.5 μm     

4H-SiC SBD和JBS退火研究

在4H-SiC外延材料上制备了SBD和JBS器件,研究并分析了退火温度对这两种器件正反向特性的影响。结果表明,低于350℃退火可同时提高SBD和JBS的正反向特性。当退火温度高于350℃时,二者的正向特性都出现退化,SBD退化较JBS更为严重。JBS阻断电压随退火温度升高而增大,在退火温度高于450℃时增加趋势变缓。SBD阻断电压随退火温度升高先升后降,在500℃退火时达到一个最大值。可见一定程度的退火有助于提高4H-SiCSBD和JBS器件的正反向特性,但须考虑其对正反向特性的不同影响。综合而言,退火优化后JBS优于SBD器件性能。     

A novel low on-resistance Schottky-barrier diode with p-buried floating layer structure

A novel low on-resistance Schottky-barrier diode (SBD) structure with a p-buried floating layer is demonstrated by fabricating 300-V SBDs using a buried epitaxial growth technique. The fabricated SBDs realize a 50% reduction of chip area and show a possibility of higher breakdown voltage SBD of over 100 V. In addition, both the low on-resistance and the soft-recovery characteristics can be realized by the p-buried floating layer structure. The demonstrated structure is very attractive for reduction of power dissipation without electromagnetic interference noise increase.     

3 A/40 V新型肖特基势垒二极管的设计与研制

为提高传统肖特基二极管的击穿电压,减小了器件的漏电流,提高芯片利用率,文中设计研制了适合于裸片封装的新型肖特基势垒二极管(SBD)。利用Silvaco Tcad软件模拟,在器件之间采用PN结隔离,器件周围设计了离子注入形成的保护环,实现了在浓度和厚度分别为7.5×1012 cm-3和5 μm的外延层上,制作出了反向击穿电压45 V和正向导通压降0.45 V的3 A/45 V肖特基二极管,实验和仿真结果基本吻合。此外,还开发了改进SBD结构、提高其电特性的工艺流程。