基于HSIM的铁电电容性能的研究

基于对铁电电容实际测试性能及物理模型的分析,在仿真软件HSIM原始电容模型库的基础上,通过对实验室制备的铁电电容电滞回线的拟合,得出新的模型库参数。将这些参数导入HSIM中对铁电存储器(FRAM)进行仿真,根据仿真结果对比铁电电容的性能,并由此优化铁电电容的性能,使之更匹配于电路特性。     

铁电电容的特理模型研究

用一种物理方法解释了非理想铁电电容器的电路行为。在该方法中反分立的铁电电容假设为堆积状的介电层结构,包括铁电层和非开关介电层。通过这种方法改进了Sawyer-Tower电路并测量了其电特性。用该模型较准确地测量了由于输入信号频率变化而引起的电滞回线的畸变,并且输入信号幅度的影响与实验结果比较吻合。     

Effect of imprint on operation and reliability of ferroelectricrandom access memory (FeRAM)

The effect of the imprint on the operation of the ferroelectric random access memory (FeRAM) was estimated by a quasitheoretical model, including the hysteresis shift along the voltage axis and the depolarization induced by the hysteresis shift. Based on the experimental data of the imprint up to 90 days, the hysteresis shift and the depolarization are expressed by a stretched exponential equation as the aging time, and a hyperbolic tangent as the shifted voltage, respectively. Using this model, nonlinear phenomena of bit-line voltage change with the aging time is successfully predicted, and the aging reliability for two transistor and two capacitor (2T/2C) cell architecture with the imprinted capacitors is estimated for the first time. This technique is applied to the evaluation of aging reliability for the Pb(Zr,Ti)O₃ and (Pb,La)(Zr,Ti)O₃ capacitors, revealing that the latter has higher reliability than the former     

电容的分数阶等效电路建模与分析

实际的电容器件都是非理想的,其特性受到各种因素的影响,建立精确的电容模型对于电路系统分析与设计十分必要。考虑到电容的分数阶微积分特性,文中基于传统的电容整数阶等效电路模型,提出电容的分数阶等效电路模型,并采用差分进化算法辨识出模型参数,然后将该模型应用于Buck电路进行纹波电压的分析。仿真结果表明,同传统整数阶等效电路模型相比,分数阶等效电路模型拟合电容实际数据的准确度更高,验证了该电容分数阶等效电路模型的有效性。     

一种新的铁电电容模型及其在1T/1C FeRAM中的应用

随着集成铁电工艺的迅速发展和铁电电容的广泛应用 ,铁电电容模型的缺乏已成为制约基于铁电电容电路设计和优化的瓶颈。文中提出的非线性双电容铁电电容模型是线性双电容铁电电容模型的改进 ,它不仅与线性双电容模型一样易于用宏模型实现 ,而且比后者具有更高的精度和更简单的控制方式。以 1 T/1 C单元作为基于铁电电容电路设计优化的实例 ,定性分析了位线寄生电容对读出窗口的影响 ,并在 HSPICE中用非线性双电容模型进行了仿真 ,得到位线寄生电容与 1 T/1 C单元铁电电容比例 (CBL/CF E)对读出窗口的最优值 :CBL/CF E=2 .4     

A survey of circuit innovations in ferroelectric random-accessmemories

This paper surveys circuit innovations in ferroelectric memories at three circuit levels: memory cell, sensing and architecture. A ferroelectric memory cell consists of at least one ferroelectric capacitor, where binary data are stored, and one or two transistors that either allow access to the capacitor or amplify its contents for a read operation. Once a cell is accessed for a read operation, its data are presented in the form of an analog signal to a sense amplifier, where it is compared against a reference voltage to determine its logic level. The circuit techniques used to generate the reference voltage must be robust to semiconductor processing variations across the chip and the device imperfections of ferroelectric capacitors. We review six methods of generating a reference voltage, two being presented for the first time in this paper. These methods are discussed and evaluated in terms of their accuracy, area overhead and sensing complexity. Ferroelectric memories share architectural features such as addressing schemes and input/output circuitry with other types of random-access memories such as dynamic random-access memories. However, they have distinct features with respect to accessing the stored data, sensing, and overall circuit topology. We review nine different architectures for ferroelectric memories and discuss them in terms of speed, density and power consumption     

DC voltage control strategy for a five-level converter

This paper describes a control method for a three-phase five-level diode-clamp pulse width modulation (PWM) converter considering DC-link capacitor voltage balancing problem. The proposed control circuit uses multiband hysteresis comparators (MHCs) to simplify the control of the main circuit. The DC-link capacitor voltage balancing problem is solved by changing the shape of the MHC. The proposed method can (1) overcome voltage imbalance at the DC-link capacitors; (2) achieve a unity power factor; (3) generate nearly sinusoidal input currents; and (4) regenerate electric power back to the power system. Simulation and experimental results demonstrate the validity of the proposed method     

High Security FeRAM‐Based EPC C1G2 UHF (860 MHz‐960 MHz) Passive RFID Tag Chip

The metal‐ferroelectric‐metal (MFM) capacitor in the ferroelectric random access memory (FeRAM) embedded RFID chip is used in both the memory cell region and the peripheral analog and digital circuit area for capacitance parameter control. The capacitance value of the MFM capacitor is about 30 times larger than that of conventional capacitors, such as the poly‐insulator‐poly (PIP) capacitor and the metal‐insulator‐metal (MIM) capacitor. An MFM capacitor directly stacked over the analog and memory circuit region can share the layout area with the circuit region; thus, the chip size can be reduced by about 60%. The energy transformation efficiency using the MFM scheme is higher than that of the PIP scheme in RFID chips. The radio frequency operational signal properties using circuits with MFM capacitors are almost the same as or better than with PIP, MIM, and MOS capacitors. For the default value specification requirement, the default set cell is designed with an additional dummy cell.     

Recent Developments in Fault Detection and Power Loss Estimation of Electrolytic Capacitors

This paper proposes a comparative study of current-controlled hysteresis and pulsewidth modulation (PWM) techniques, and their influence upon power loss dissipation in a power-factor controller (PFC) output filtering capacitors. First, theoretical calculation of low-frequency and high-frequency components of the capacitor current is presented in the two cases, as well as the total harmonic distortion of the source current. Second, we prove that the methods already used to determine the capacitor power losses are not accurate because of the capacitor model chosen. In fact, a new electric equivalent scheme of electrolytic capacitors is determined using genetic algorithms. This model, characterized by frequency-independent parameters, redraws with accuracy the capacitor behavior for large frequency and temperature ranges. Thereby, the new capacitor model is integrated into the converter, and then, software simulation is carried out to determine the power losses for both control techniques. Due to this model, the equivalent series resistance (ESR) increase at high frequencies due to the skin effect is taken into account. Finally, for hysteresis and PWM controls, we suggest a method to determine the value of the series resistance and the remaining time to failure, based on the measurement of the output ripple voltage at steady-state and transient-state converter working.      

Loss-Free Balancing Circuit for Series Connection of Electrolytic Capacitors Using an Auxiliary Switch-Mode Power Supply

Most of today's power converters such as three-phase variable-speed drives, uninterruptible power systems, welding converters, and telecom and server power supplies are based on voltage-source converters equipped with bulky dc-link electrolytic capacitors. To be able to handle full dc bus voltage, the dc bus capacitor is arranged as series-connected electrolytic capacitors rated at lower voltage. An electrolytic capacitor, however, is not an ideal capacitor. It has significant leakage current that strongly depends on the capacitor temperature, voltage, and ageing conditions. To compensate large dispersion of the leakage current and ensure acceptable sharing of the total dc bus voltage among the series-connected capacitors, a passive balancing circuit is often used. Drawbacks of the ordinary passive balancing circuit, such as size, significant losses, and standby consumption are discussed in this paper. An active loss-free balancing circuit, which utilizes an auxiliary switch-mode power supply (SMPS) to equalize the capacitor voltages, is proposed. The capacitors midpoint (MP) is connected to the SMPS via two devices; namely a current injection device and a compensation device. The current injection device injects current into the capacitors MP, while the compensation device sinks the difference between the capacitor leakage currents and the injected current. As a result, the capacitor voltages are controlled and maintained in the desired ratio. The proposed balancing technique is theoretically analyzed and experimentally verified on a laboratory setup. The results are presented and discussed.      

基于高压陶瓷电容器放电回路的优化设计

针对使用高压电容器的几种放电回路,开展了回路参数仿真分析研究。参数辨识结果表明采用高压陶瓷电容和固态开关组成的放电回路参数明显优于采用高压固体电容器和触发管的放电回路,改进装配方式后回路参数也比改进之前明显减小。该改进技术的提出,在不改变既定电性能指标的基础上大大改善了整个回路电路的体积与质量。该改进技术已成功应用于多个爆破项目中。     

PA-Cap聚合物电容器在模拟CPU电源中的应用

在计算机CPU的电源电路中,采用电解电容器作为电源的去耦电容。研究了CPU的负载高速变化时,三种类型电容器提供瞬时电流以稳定电源电压的情况。结果显示:PA-Cap聚合物片式叠层铝电解电容器(56μF)的Res为23mΩ,△V为–90mV,而220μF钽电容Res为73mΩ,△V为–172mV,1000μF液体铝电解电容Res为56mΩ,△V为–232mV。因此,PA-Cap聚合物电容器用在开关电源和数字电路中应用前景广阔。     

Optimization of word-line booster circuits for low-voltage flashmemories

Two word-line booster circuits, which output a word-line voltage for reading dash memory data, are analyzed and optimized. A capacitor-switched booster circuit outputs a voltage higher than the supply voltage by switching the connection state of one of more boosting capacitors with the load capacitor from parallel to series. The optimum number of capacitors and capacitance per boosting capacitor are obtained as a function of the voltage ratio of the required high voltage to the supply voltage. The operation current consumed by the boosting operation is also analytically derived. In addition, another booster circuit-Dickson charge-pump circuit-is optimized under the condition to maximize the output current at a high word-line voltage. Characteristics of the booster circuits are compared, and the selection of booster circuit for low-voltage flash memory is discussed     

Investigation of PECVD dielectrics for nondispersivemetal-insulator-metal capacitors

Metal-insulator-metal (MIM) capacitors with PECVD nitride exhibit trap-induced dispersive behavior, which leads to degradation in capacitor linearity at low frequencies, limiting the accuracy in precision analog circuits. While LPCVD oxide results in nondispersive behavior, the high deposition temperature excludes the use of LPCVD dielectrics for MIM capacitors using the standard back-end metal layers as capacitor bottom plates. The latter is preferred in view of the low substrate coupling needed for RF applications. In this work, alternative PECVD dielectrics have been investigated with respect to frequency dependence of voltage linearity, hysteresis, matching, and leakage characteristics. It will be shown that ONO stacks offer a combination of good voltage linearity, absence of dispersive behavior and hysteresis, excellent matching, and low leakage     

采用有源电容倍增器改善开关电容DC-DC变换器的性能

研究了开关电容DC-DC变换器输出电压与电容的关系,分析了变换器输出电压波纹产生的原因.针对变换器中大电容难集成的问题,提出了一种基于跨导放大器和第二代电流传输器的有源电容倍增器的新型拓扑结构.该电路只用较少的元件就可以实现开关电容变换器中的浮地和接地电容.以二阶开关电容DC-DC变换器为例,用PSPICE软件分别对采用了有源电容倍增器的新型结构和传统结构进行了仿真.结果显示,基于有源电容倍增器的开关电容变换器仅用100pF电容就等效了200nF电容的输出性能,而且具有更低的输出电压波纹.     

Effects of nonlinear storage capacitor on DRAM READ/WRITE

Important aspects of nonlinear storage capacitor switching and their impact on DRAM READ/WRITE operations are explained using a simple model and PSpice simulation. The voltage signal and charge-transfer rate are found to be dependent not only on the total charged stored, but also on the exact shape of the storage capacitor Q-V curve. Typical paraelectric capacitors are shown to deliver a smaller voltage signal than a linear capacitor that has the same stored charge at the operating voltage. Further, typical paraelectric capacitors have slower READ but faster WRITE compared to the linear capacitor     

高压薄膜脉冲电容器放电性能的研究

高压薄膜脉冲电容器是放电触发电路中的重要储能器件,通常用于产生高功率大电流脉冲.分析高压薄膜电容器性能检测指标及实际放电过程,找出了高压薄膜电容器样本失效原因,采取提高卷绕电容器芯工艺水平措施后,所制高压薄膜电容器常规指标合格,放电触发次数可靠性指标达到系统要求的6 000次以上.     

On the pinched hysteresis behavior in a state-controlled resistor

We show that the pinched hysteresis behavior observed in a voltage-controlled resistor with state-feedback self-control can be attributed to the current flowing in the parasitic capacitance holding the voltage across this resistor. A mathematical model describing this circuit structure is derived and validated numerically. To provide experimental evidence of this proposal, a circuit representing a voltage-controlled resistor is placed in parallel with a capacitor and then the current in this capacitor, which is proportional to the derivative of the applied voltage, is sensed, converted into a voltage and used to control the resistance value. This leads to the appearance of a pinched hysteresis loop as theoretically predicted. This work provides further insight into the origin of this behavior in fabricated solid-state devices that can be shown to follow the proposed circuit structure.     

Printable Ferroelectric PVDF/PMMA Blend Films with Ultralow Roughness for Low Voltage Non‐Volatile Polymer Memory

Here, a facile route to fabricate thin ferroelectric poly(vinylidene fluoride) (PVDF)/poly(methylmethacrylate) (PMMA) blend films with very low surface roughness based on spin‐coating and subsequent melt‐quenching is described. Amorphous PMMA in a blend film effectively retards the rapid crystallization of PVDF upon quenching, giving rise to a thin and flat ferroelectric film with nanometer scale β‐type PVDF crystals. The still, flat interfaces of the blend film with metal electrode and/or an organic semi‐conducting channel layer enable fabrication of a highly reliable ferroelectric capacitor and transistor memory unit operating at voltages as low as 15 V. For instance, with a TIPS‐pentacene single crystal as an active semi‐conducting layer, a flexible ferroelectric field effect transistor shows a clockwise I–V hysteresis with a drain current bistability of 10³ and data retention time of more than 15 h at ±15 V gate voltage. Furthermore, the robust interfacial homogeneity of the ferroelectric film is highly beneficial for transfer printing in which arrays of metal/ferroelectric/metal micro‐capacitors are developed over a large area with well defined edge sharpness.     

Error correction techniques for high-performance differential A/Dconverters

Error correction techniques that overcome several error mechanism that can affect the accuracy of charge-redistribution analog-to-digital converters (ADCs) are described. A correction circuit and a self-calibration algorithm are used to improve the common-mode rejection of the differential ADC. A modified technique is used to self-calibrate the capacitor ratio errors and obtain higher linearity. The residual error of the ADC due to capacitor voltage dependence is minimized using a quadratic voltage coefficient (QVC) self-calibration scheme. A dual-comparator topology with digital error correction circuitry is used to avoid errors due to comparator threshold hysteresis. A fully differential charge-redistribution ADC implemented with these techniques was fabricated in a 5-V 1-μm CMOS process using metal-to-polysilicide capacitors. The successive-approximation converter achieves 16-b accuracy with more than 90 dB of common-mode rejection while converting at a 200-kHz rate