A 0.8V 40 Gb/s Novel CMOS Regulated Cascode Trans-impedance Amplifier for Optical Sensing Applications

This paper describes a 0.8 V 700 μW CMOS low-voltage regulated cascode trans-impedance amplifier (TIA). It reduces the need for extra bias voltages compared to other recent low-voltage regulated cascode topologies. A trans-impedance gain of around 60 dBΩ along with a 40 GHz bandwidth was achieved using the 0.13 μm IBM CMOS process technology. The input referred noise current spectral density was below $ {{{18{\mathrm{pA}}}} \left/ {{\sqrt {\mathrm{Hz}} }} \right.} $ within the -3 dB noise bandwidth. Eye diagram simulations using a ?53dBm input photo-diode current signal and a 2³¹-1 pseudo random bit sequence data pattern, indicates an eye opening of 90 % at 10Gbit/s and 50 % at 40Gbit/s. This proposed RGC TIA is thus a robust building block for numerous optical sensing applications with low bit error ratio (BER) figure.     

Design and modeling of high-resolution multibit log-domain \Delta \Sigma modulators

Log-domain Delta-Sigma ( $\Delta \Sigma$ ) modulators are attractive for implementing analog-to-digital (A/D) converters (ADCs) targeting low-power low-voltage applications. Previously reported log-domain $\Delta \Sigma$ modulators were limited to 1-bit quantization and, hence, could not benefit from the advantages associated with multibit quantization (namely, reduced in-band quantization noise, and increased modulator stability). Unlike classical $\Delta \Sigma$ modulators, directly extending a log-domain $\Delta \Sigma$ modulator with a 1-bit quantizer to a log-domain $\Delta \Sigma$ modulator with a multibit quantizer is challenging, in terms of CMOS circuit implementation. Additionally, the realization of log-domain $\Delta \Sigma$ modulators targeting high-resolution applications necessitates minimization of distortion and noise in the log-domain loop-filter. This paper discusses the challenges of multibit quantization and digital-to-analog (D/A) conversion in the log-domain, and presents a novel multibit log-domain $\Delta \Sigma$ modulator, practical for CMOS implementation. SIMULINK models of log-domain $\Delta \Sigma$ modulator circuits are proposed, and the effects of various circuit non-idealities are investigated, including the effects of log-domain compression–expansion mismatch. Furthermore, this paper proposes novel low-distortion log-domain analog blocks suitable for high-resolution analog-to-digital (A/D) conversion applications. Circuit simulation results of a proposed third-order 3-bit class AB log-domain $\Delta \Sigma$ loop-filter demonstrate 10.4-bit signal-to-noise-and-distortion-ratio (SNDR) over a 10 kHz bandwidth with a $0.84\,V_{pp}$ differential signal input, while operating from a 0.8 V supply and consuming a total power of $35.5\,\upmu \hbox {W}.$      

On the reduction of thermal and flicker noise in ENG signal recording amplifiers

Because of the extremely low amplitude of the input signal, the design of electro-neuro-graph (ENG) amplifiers involves a special care for flicker and thermal noise reduction. The task becomes really challenging in the case of implantable electronics, because power consumption is restricted to few hundreds μW. In this work, two different circuit techniques aimed to reduce flicker and thermal noise, in ultra-low noise amplifiers for implantable medical devices, are demonstrated. The circuit design, and measurement results are presented, in both cases showing an excellent performance, and noise to power consumption trade-off. In the first circuit, a very simple low-pass G_m–C chopper amplifier is used for flicker noise cancellation. It consumes only 28 mW, with a measured input referred noise and offset of 2  $ {{{\text{nV}}} \mathord{\left/ {\vphantom {{{\text{nV}}} {\sqrt {{\text{Hz}}} }}} \right. \kern-0em} {\sqrt {{\text{Hz}}} }} $ , and 2.5 μV, respectively. In the second circuit, a ultra-low noise amplifier, a energy-efficient DC–DC down-converter, and low voltage design techniques are combined, for the reduction of thermal noise with a minimum power consumption. Measured input referred noise in this case was 5.5  $ {{{\text{nV}}} \mathord{\left/ {\vphantom {{{\text{nV}}} {\sqrt {{\text{Hz}}} }}} \right. \kern-0em} {\sqrt {{\text{Hz}}} }} $ at only 380 μW power consumption. Both circuits were fabricated in a 1.5 μm technology.     

Low phase-noise VCO utilizing modified symmetric load and partial positive feedback for FDSM

The voltage-controlled oscillator (VCO) in frequency-based $\Updelta\Upsigma$ modulator (FDSM) systems behaves as a voltage-to-phase integrator converting an analog input voltage to phase information. Tuning range and phase noise are the most important factors of the basic design of a VCO in FDSM systems. In this paper a novel low phase-noise and wide tuning-range differential VCO based on a differential ring oscillator with modified symmetric load and a partial positive feedback in the differential delay cell is presented. The VCO is combined with a new bias circuit and implemented using 90 nm CMOS process technology. By using modified NMOS symmetric loads and a PMOS tail for delay cells, the VCO phase noise can be reduced with more than 13 dB compared to that of the conventional approach, achieving ?125 dBc/Hz at 500 kHz offset from the center frequency of 450 MHz. The wide tuning-range by using two added transistors (parallel with the active loads) increases the operating frequency range by about 22%, while the partial positive feedback provides the necessary bias condition for the circuit to oscillate. The designed VCO operating at a low power supply voltage of 0.6V can achieve low power consumption of 670???W at oscillation frequency of 800 MHz and good linearity reducing harmonic distortion in the $\Updelta\Upsigma$ modulator.     

A highly linear CMOS transconductance amplifier in 180?nm process technology

The present article describes the design and analysis of an operational transconductance amplifier (voltage to current converter) with wide linear input range. The proposed configuration combines the techniques of signal attenuation and source degeneration in order to reduce the odd order harmonic distortion significantly. The proposed circuit is compared with several circuit topologies based on MOS differential pairs with respect to their achievable linearity, input referred noise and power consumption. The linear transconductor is designed and simulated in 180?nm CMOS process technology with 1.8?V power supply. Simulation results show third order harmonic distortion (HD ₃) of ?70?dB for 600?mV_pp input signal. For 1% transconductance variation the linear range is about 1.2?V_pp. The input referred noise of the transconductor is $70\,\hbox{nV}/\sqrt{\text {Hz}}$ at 10?MHz. The quiescent power consumption is only 450???W.     

Analog baseband chain of synthetic aperture radar (SAR) receiver

An analog baseband chain for a synthetic aperture radar receiver implemented in a 130 nm CMOS technology is presented in this paper. Occupying 0.23 mm² of silicon area, the baseband chain consists of a three-stage variable gain amplifier (VGA), a 5th-order gm-C low-pass filter (LPF) and an output buffer. The gain of the chain can be controlled by tuning the control voltages of the VGA and has a range from 25 to 34 dB. 8 dB of the gain is embedded into the LPF. The bandwidth of the LPF is programmable from 100 to 190 MHz by means of capacitor matrices. The chain, which uses a 1.2 V supply voltage, achieves an input-referred noise density of 4 nV/ $ \sqrt {\text{Hz}} $ and an in-band IIP3 of ?46 dBV rms.     

70-MHz IF 10-MHz bandwidth bandpass \Upsigma\Updelta modulator for WCDMA applications

A MASH bandpass $\Upsigma\Updelta$ modulator for wide-band code division multiple access (WCDMA) applications is presented. The signal bandwidth of the proposed modulator is 10?MHz centered around an intermediate frequency (IF) of 70.5?MHz. Two two-path second-order bandpass $\Upsigma\Updelta$ modulators make the MASH architecture, which realizes a noise transfer function with four couples of complex conjugate zeros. The proposed circuit, fabricated with a 0.18???m CMOS technology, uses a sampling frequency of 180?MHz to obtain a resolution of about 12?bits in the 10?MHz bandwidth around the IF. The measured modulator power consumption is 95?mW with a supply voltage of 1.8?V. The achieved figure-of-merit (FoM _BP ) is 0.37?pJ/conversion-level.     

A Low-Voltage and Low-Power 3-GHz CMOS LC VCO for S-Band Wireless Applications

A fully integrated 0.18- \(\upmu \hbox {m}\) CMOS LC-tank voltage-controlled oscillator (VCO) suitable for low-voltage and low-power S-band wireless applications is proposed in this paper. In order to meet the requirement of low voltage applications, a differential configuration with two cross-coupled pairs by adopting admittance-transforming technique is employed. By using forward-body-biased metal oxide semiconductor field effect transistors, the proposed VCO can operate at 0.4 V supply voltage. Despite the low power supply near threshold voltage, the VCO achieves wide tuning range by using a voltage-boosting circuit and the standard mode PMOS varactors in the proposed oscillator architecture. The simulation results show that the proposed VCO achieves phase noise of \(-\) 120.1 dBc/Hz at 1 MHz offset and 39.3 % tuning range while consuming only \(594~\upmu \hbox {W}\) in 0.4 V supply. Figure-of-merit with tuning range of the proposed VCO is \(-\) 192.1 dB at 3 GHz.     

一种用于水听器电压检测的模拟前端电路

提出了一种用于水听器电压检测的模拟前端电路,包括低噪声低失调斩波运算放大器,跨导电容(gm-C)低通滤波器,增益放大器三部分主体电路;低噪声低失调斩波运算放大器用于提取水听器前端传感器输出的微弱电压信号;gm-C低通滤波器用于滤除电压信号频率外的高频噪声和高次谐波;最后经过增益放大器放大至后级模数转换器的输入电压范围,输出数字码流;芯片采用台积电(TSMC)0.18μm单层多晶硅六层金属(1P6M)CMOS工艺实现。测试结果表明,在电源电压1.8 V,输入信号25 kHz和200 kHz时钟频率下,斩波运放输入等效失调电压小于110μV;整体电路输出信号动态范围达到80 dB,功耗5.1 mW,满足水听器的检测要求。     

Electronically scanned RF-to-bits beam aperture arrays using 2-D IIR spatially bandpass digital filters

A beamforming system based on two-dimensional (2-D) spatially bandpass infinite impulse response (IIR) plane wave filtering is presented in a multi-dimensional signal processing perspective and the implementation details are discussed. Real-time implementation of such beamforming systems requires modeling of computational electromagnetics for the antennas, radio frequency (RF) analog design aspects for low-noise amplifiers (LNAs), mixed-signal aspects for signal quantization and sampling and finally, digital architectures for the spatially bandpass plane wave filters proposed in Joshi et al. (IEEE Trans Very Large Scale Integr Syst 20(12):2241–2254, 2012). Multi-dimensional spatio-temporal spectral properties of down-converted RF plane wave signals are reviewed and derivation of the spatially bandpass filter transfer function is presented. An example of a wideband antipodal Vivaldi antenna is simulated at 1 GHz. Potential RF receiver chains are identified including a design of a tunable combline microstrip bandpass filter with tuning range 0.8–1.1 GHz. The 1st-order sensitivity analysis of the beam filter 2-D $\mathbf z $ -domain transfer function shows that for a 12-bits of fixed-point precision, the maximum percentage error in the 2-D magnitude frequency response due to quantization is as low as $0.3\,\%$ . Monte-Carlo simulations are used to study the effect of quantization on the bit error rate (BER) performance of the beamforming system. 5-bit analog to digital converter (ADC) precision with 8-bit internal arithmetic precision provides a gain of approximately 16 dB for a BER of $10^{-3}$ with respect to the no beamforming case. ASIC Synthesis results of the beam filter in 45 nm CMOS verifies a real time operating frequency of 429 MHz.     

A 20 Gbps inductorless CMOS optical receiver for short-distance VCSEL-based 850 nm optical links

This paper presents a circuit design and experimental results for a 20 Gbps CMOS inductorless optical receiver, a transimpedance amplifier (TIA) and a limiting amplifier, for a vertical-cavity surface emitting laser based 850 nm optical link. The proposed optical receiver apply a power supply noise canceling technique, an additional path from the power supply to the TIA output to generate a reversed phase signal that reduces the power supply noise, and bandwidth enhancement circuit design that dose not require internal inductors. The simulation results shows a power supply rejection ratio of ?96.6 dB at 10 MHz, a total gain of $82.8\,\hbox{dB}\Upomega$ and a ?3 dB bandwidth of 15.5 GHz. A test chip fabricated in 90 nm CMOS technology and demonstrated with a PIN photo-diode, a bandwidth of 17 GHz and a responsibility of 0.53 A/W. The measurement results show a 25 % eye opening and an input sensitivity of ?7.1 dBm at a bit error rate of 10^?12 with a 2⁹ ? 1 pseudo-random test pattern at 20 Gbps. The core circuit of the optical receiver occupies only an area of 0.02 mm².     

A broadband, differential transimpedance amplifier in 0.35 μm SiGe BICMOS technology for 10 Gbit/s fiber optical front-ends

This study focuses on 10 Gbit/s differential transimpedance amplifier. At the beginning of the work, the amplifier circuit is deeply analyzed and is optimized for the best phase linearity over the bandwidth resulted in a group delay variation less than 1 ps. The amplifier circuit is designed with 0.35 μm SiGe heterojunction bipolar transistor BICMOS process. 9 GHz bandwidth, almost 58 dBΩ transimpedance gain with less than 11.18 pA/ $ \sqrt {\text{Hz}} $ averaged input-referred noise current are achieved. Electrical sensitivity is 15 μA_pp. Power consumption is 71 mW at 3.3 V single power supply.     

Experimental implementation of $$\Delta \Sigma $$AD modulator with dynamic analog components

This paper presents an experimental prototype of 2nd-order multi-bit \(\Delta \Sigma \)AD modulator with dynamic analog components for low power and high signal to noise and distortion (SNDR) application. The integrators in the modulator are realized by ring amplifier without static current. Multi-bit quantizer and analog adder in the feed-forward modulator is realized by a passive-adder embedded successive approximation register analog to digital converter which consists of capacitor array and a dynamic comparator. The dynamic comparator does not dissipate static power at all when a pre-amplifier is not used. Proposed modulator is fabricated in TSMC 90 nm CMOS technology. Measurement results of the modulator dynamic range is over 84 dB. Measured peak SNDR = 77.51 dB, SNR = 80.08 dB are achieved for the bandwidth of BW = 94 kHz while a sinusoid differential \(-1\) dBFS input is sampled at 12 MS/s. The total analog power consumption of the modulator is 0.37 mW while the supply voltage is 1.1 V.     

A High Gain and Low Flicker Noise CMOS Mixer with Low Flicker Noise Corner Frequency Using Tunable Differential Active Inductor

This paper presents the design of a high conversion gain and low flicker noise down conversion CMOS double balanced Gilbert cell mixer using \(0.18\,\upmu \hbox {m}\) CMOS technology. The high conversion gain and low flicker noise mixer is implemented by using a differential active inductor (DAI) circuit and cross-coupled current injection technique within the conventional double-balanced Gilbert cell mixer. A cross-coupled current bleeding circuit is used to inject the current to the switching stage to decrease the flicker noise. Instead of spiral inductor, a DAI with high tunability of the inductor and quality factor is used to tune out the parasitic capacitance effect and decrease the leakage current that has a harmonic component and produce the flicker noise. By tuning the DAI, the flicker noise corner frequency is reduced to 150 Hz. The proposed circuit is simulated with Cadence Spectra and the simulation results shows the NF of 11.2 dB, conversion gain of 23.7 dB and IIP3 of \(-6\)  dB for an RF frequency of 2.4 GHz. The excellent LO-RF, LO-IF, RF-LO and RF-IF isolations of \(-60, -110, -52\) and \(-64\)  dB are achieved respectively. The total power consumption is 10.5 mW from a 1.8 V DC power supply.     

0–30?V common mode range, 120?dB CMRR, and 10?nV/ \sqrt {\text{Hz}} noise floor current shunt monitor IC with an embedded ΣΔ modulated digital interface

Sensing and controlling current flow is a fundamental requirement for many electronic systems, including power management (DC?CDC converters and LDOs), battery chargers, electric vehicles, solenoid positioning, motor control, and power monitoring. Current shunt monitor (CSM) system enables current measurement across an external sense resistor (R _S ) in series to current flow. Proposed CSM system can sense a system (power supply) current from 1 to 500?mA across a typical board Cu-trace resistance of 1??? with less than 10???V input-referred offset, 150?nV/°C offset drift and 0.1% accuracy. Instead of using a costly zero-TC sense resistor (R _S ) that is used in typical CSM systems; proposed method uses existing Cu board trace for sensing. The sense amplifier uses chopper stabilization in the signal chain of the amplifier to suppress input-referred offset down to less than 10???V. Switching current-mode (SI) FIR filtering is used at the instrumentation amplifier output to filter out the chopping ripple at the harmonics of the chopping frequency. A frequency domain Sigma Delta (????FD) ADC enables a digital interface to processor applications. The CSM is fabricated on a 0.7???m CMOS process with three levels of metal with maximum Vds tolerance of 8?V, and operates across a common mode range of 0?C30?V achieving less than 10?nV/ $ \sqrt {\text{Hz}} $ of flicker noise at 100?Hz. By using a semi-digital SI FIR filter, residual chopper ripple is suppressed by more than 7.5?mV_pp from the base line of 8?mV_pp, which is equivalent to 25?dB suppression.     

Capacitor Cross-Coupled Fully-differential CMOS Folded Cascode LNAs with Ultra Low Power Consumption

This paper proposes a fully-differential folded cascode low noise amplifier (LNA) for 5.5 GHz receiver in 180 nm CMOS technology. By improving folded cascode with an additional inductance connected at the gate of CG stage to cancel parasitic capacitance and then employing capacitor cross-coupled technique as a negative feedback in the proposed LNA, the performance of the LNA can be improved significantly in terms of gain (S21) and noise figure (NF) compared with the conventional fold cascode LNA. Furthermore, the DC power consumption of the LNA is further reduced with forward body bias topology. The measurements show the proposed LNA achieves 16.5 dB power gain, a NF of 1.53 dB, good input/output matching with the S11 and S22 are less than \(-\) 15 dB. And the operating voltage is only 0.5 V with ultra-low power consumption of 0.89 mW.     

A 0.36 μW/channel recorder for external ambulatory ECG recorders

There is an increasing demand for long-term ECG monitoring applications which are very low power, small size and capable of wireless data transmission. This paper presents an analog front-end and also modulator for long-term ECG recording purpose. The fully integrated system features three independent channels and a modulator. The analog front-end includes a voltage-to-time conversion and a tunable modulator to achieve a very low power consumption for wireless transmission of the data without analog to digital converter. The proposed system is designed and simulated in a \(0.18\,\upmu \hbox {m}\) CMOS technology and occupies only \(0.245\,\mathrm{mm}^{2}\). It can record ECG signal with 9.2-bit resolution while consuming only \(0.36\,\upmu {\mathrm{W}}\) per channel from a 0.9 V supply. Also, it can transmit data consuming just \(0.72\,{\upmu }\mathrm{W}\) per channel from a 0.9 V supply. The input referred noise of the readout channel is \(2.01\,\upmu {\mathrm{V}}_{{{\rm rms}}}\).     

Triple cascaded current-reuse low noise amplifier

A triple cascaded current-reuse CMOS low noise amplifier for 3.5 GHz WiMAX application is presented. Three common-source amplifiers are stacked and reuse the same current. This triple cascaded topology is able to enhance power gain but needs two coupling networks which costs enormous chip size. In order to have reasonable chip size, two coupling methods are investigated. For obtaining simultaneous input and noise matching, an additional capacitor is employed to adjust quality factor and reduce the gate induced current noise. The measurement results show a maximum power gain of 21.7 dB and minimum noise figure of 3.11 dB. The chip size is 1.05 mm \(\times\) 0.93 mm including all pads and the power consumption is 5.16 mW with a supply voltage of 1.5 V. A figure-of-merit of 49.7 is reached.     

A 1 GS/s, 31 MHz BW, 76.3 dB dynamic range, 34 mW CT-\Updelta\Upsigma ADC with 1.5 cycle quantizer delay and improved STF

A 1 GS/s continuous-time delta-sigma modulator (CT- $\Updelta\Upsigma$ M) with 31 MHz bandwidth, 76.3 dB dynamic range and 72.5 dB peak-SNDR is reported in a 0.13 μm CMOS technology. The design employs an excess loop delay (ELD) of more than one clock cycle for achieving higher sampling rate. The ELD is compensated using a fast-loop formed around the last integrator by using a sample-and-hold. Further, the effect of this ELD compensation scheme on the signal transfer function (STF) of a feedforward CT- $\Updelta\Upsigma$ architecture has been analyzed and reported. In this work, an improved STF is achieved by using a combination of feed-forward, feed-back and feed-in paths and power consumption is reduced by eliminating the adder opamp. This CT- $\Updelta\Upsigma$ M has a conversion bandwidth of 31 MHz and consumes 34 mW from the 1.2 V power supply. The relevant design trade-offs have been investigated and presented along with simulation results.     

A 3–10 GHz Ultra Wideband Receiver LNA in 0.13 \mu m CMOS

A fully integrated low-power, low-complexity ultra wideband (UWB) 3–10 GHz receiver front-end in standard 130 nm CMOS technology is proposed for UWB radar sensing applications. The receiver front-end consists of a full UWB band low-noise amplifier and an on-chip diplexer. The on-chip diplexer has a 1 dB insertion loss and provides a \(-\) 30 dB isolation. The diplexer switch was co-designed with the receiver input matching network to optimize the power matching while simultaneously achieving good noise matching performance. The receiver low-noise amplifier provides a 3–10 GHz bandwidth input matching and a power gain of 17 dB. The overall receiver front-end consumes an average power of 13 mW. The core area of the transceiver circuit is 500 \(\mu \) m by 700 \(\mu \) m.