Analytical and Numerical Investigation of Noise in Nanoscale Ballistic Field Effect Transistors

The current of ballistic nanoscale MOSFETs is expected to exhibit shot noise, essentially because the electron distribution is very far from equilibrium. Here, we derive an analytical expression of shot noise in fully ballistic MOSFETs and show how it can be computed on the basis of numerical simulations of the DC electrical properties. We show that the power spectral density of shot noise of the drain current is strongly suppressed as an effect of both Pauli exclusion and electrostatic interaction. The amount of such suppression depends on the device structure, and in particular on the gate capacitance. Results on shot noise of the gate current are also shown, since such the leakage current might be significant in nanoscale MOSFETs, for small equivalent oxide thickness.     

Low-Frequency Noise-Based Degradation Prediction of$hboxAl_xhboxGa_1 - xhboxN/GaN$MODFETs

Degradation prediction of AlGaN/GaN MODFET is explored based on characterization of gate and drain low- frequency noise. Heterostructures grown by molecular beam epitaxy (MBE) and metal-organic chemical vapor deposition (MOCVD) are used for this purpose. Devices from the former category were unpassivated while those of the latter were passivated. Despite the highly variable gate noise current characteristics among unpassivated MBE devices and between MBE and MOCVD-based devices, it is demonstrated that the drain noise current characteristics of the two groups of devices have considerable resemblance. Moreover, it is shown that the drain noise current level can be used as a means for gate degradation prediction     

Microscopic simulation of RF noise in junctionless nanowire transistors

A deterministic solver for the analysis of microscopic noise and small-signal fluctuations in junctionless nanowire field-effect transistors is presented, which is based on a self-consistent and simultaneous solution of the Poisson/Schrödinger/Boltzmann equations. It is verified that the numerical framework fulfills the vital properties of reciprocity and passivity in the small-signal sense, and yields Johnson–Nyquist noise under equilibrium conditions. Key figures such as the cutoff frequency, drain excess noise factor, the Fano factor, and gate/drain correlation coefficient are presented at various bias conditions. In this work we show that similar to the inversion-mode MOSFETs, the gate and drain current noises mainly stem from the warm electrons at the source side, whereas the hot electrons do not have a significant contribution. Also, our results show that the device behaves similar to long-channel FETs in terms of its excess noise even for a channel length of 10 nm, due to the strong control of its electrostatics by the all-around gate.     

Monte Carlo analysis of dynamic characteristics and high‐frequency noise performances of nanoscale double‐gate MOSFETs

In this paper, a full‐band Monte Carlo simulator is employed to study the dynamic characteristics and high‐frequency noise performances of a double‐gate (DG) metal–oxide–semiconductor field‐effect transistor (MOSFET) with 30 nm gate length. Admittance parameters (Y parameters) are calculated to characterize the dynamic response of the device. The noise behaviors of the simulated structure are studied on the basis of the spectral densities of the instantaneous current fluctuations at the drain and gate terminals, together with their cross‐correlation. Then the normalized noise parameters (P, R, and C), minimum noise figure (NF_min), and so on are employed to evaluate the noise performances. To show the outstanding radio‐frequency performances of the DG MOSFET, a single‐gate silicon‐on‐insulator MOSFET with the same gate length is also studied for comparison. The results show that the DG structure provides better dynamic characteristics and superior high‐frequency noise performances, owing to its inherent short‐channel effect immunity, better gate control ability, and lower channel noise. Copyright © 2012 John Wiley & Sons, Ltd.     

Random Telegraph Noise in 30 nm FETs with Conventional and High-κ Dielectrics

The magnitude of fractional current variation in ultra-small (30 nm channel length) MOSFETs due to single charge trapping-detrapping events at any position within the gate dielectric is studied using numerical simulation. These random telegraph signals in the drain current indicate the amplitude of low frequency MOSFET noise. Simulations are performed for realistic devices with poly-silicon gates subject to poly-silicon depletion, and for both SiO₂ and HfO₂ as dielectric materials.     

Bipolar Charge Trapping Induced Anomalous Negative Bias-Temperature Instability in HfSiON Gate Dielectric pMOSFETs

Negative bias-temperature (NBT) stress-induced drain current instability in a pMOSFET with a gate stack is investigated by using a fast transient measurement technique. We find that in certain stress conditions, the NBT-induced current instability evolves from enhancement mode to degradation mode, giving rise to an anomalous turn-around characteristic with stress time and stress gate voltage. Persistent poststress drain current degradation is found in a pMOSFET, as opposed to drain current recovery in its n-type MOSFET counterpart. A bipolar charge trapping model along with trap generation in a HfSiON gate dielectric is proposed to account for the observed phenomena. Poststress single charge emissions from trap states in HfSiON are characterized. Charge pumping and carrier separation measurements are performed to support our model. The impact of NBT stress voltage, temperature, and time on drain current instability mode is evaluated.     

Thermal noise in nanometric DG-MOSFET

The noise performance of double-gated (DG) and single-gated (SG) MOSFETs is compared. We observe a significant improvement of the noise figure (NF) in the DG structure, which is explained in terms of a favorable increase of cross-correlation between the drain and gate currents. Finally, we showed that the presence of a residual P-type impurity in the channel of a DG structure induces noticeable changes in the spectral density of the gate current fluctuations that is reflected on the noise figure.     

1/f Noise: threshold voltage and ON-current fluctuations in 45 nm device technology due to charged random traps

Discrete impurity effects in terms of their statistical variations in number and position in the inversion and depletion region of a MOSFET, as the gate length is aggressively scaled, have recently been investigated as being a major cause of reliability degradation observed in intra-die and die-to-die threshold voltage variation on the same chip resulting in significant variation in saturation drive (on) current and transconductance degradation—two key metrics for benchmark performance of digital and analog integrated circuits. In this paper, in addition to random dopant fluctuations (RDF), the influence of random number and position of interface traps lying close to Si/SiO₂ interface has been examined as it poses additional concerns because it leads to enhanced experimentally observed fluctuations in drain current and threshold voltage. In this context, the authors of this article present novel EMC based simulation study on trap induced random telegraph noise (RTN) responsible for statistical fluctuation pattern observed in threshold voltage, its standard deviation and drive current in saturation for 45 nm gate length technology node MOSFET device. From the observed simulation results and their analysis, it can be projected that with continued scaling in gate length and width, RTN effect will eventually supersede as a major reliability bottleneck over the already present RDF phenomenon. The fluctuation patterns observed by EMC simulation outcomes for both drain current and threshold voltage have been analyzed for the cases of single trap and two traps closely adjacent to one another lying in the proximity of the Si/SiO₂ interface between source to drain region of the MOSFET and explained from analytical device physics perspectives.     

An analytic drain current model for long‐channel undoped gate stack surrounding‐gate MOSFETs including interface fixed charges

On the basis of the exact solution of Poisson's equation and Pao–Sah double integral for long‐channel bulk MOSFETs, a continuous and analytic drain current model for the undoped gate stack (GS) surrounding‐gate (SRG) metal–oxide–semiconductor field‐effect transistor (MOSFET) including positive or negative interface fixed charges near the drain junction is presented. Considering the effect of the interface fixed charges on the flat‐band voltage and the electron mobility, the model, which is expressed with the surface and body center potentials evaluated at the source and drain ends, describes the drain current from linear region to saturation region through a single continuous expression. It is found that the surface and body center potentials are increased/decreased in the case of positive/negative interface fixed charges, respectively, and the positive/negative interface fixed charges can decrease/increase the drain current. The model agrees well with the 3D numerical simulations and can be efficiently used to explore the effects of interface fixed charges on the drain current of the gate stack surrounding‐gate MOSFETs of the charge‐trapped memory device. Copyright © 2013 John Wiley & Sons, Ltd.     

Electronic model of a Ferroelectric Field Effect transistor

Abstract

A pair of electronic models has been developed of a Ferroelectric Field Effect transistor. These models can be used in standard electrical circuit simulation programs to simulate the main characteristics of the FFET. The models use the Schmitt trigger circuit as a basis for their design. One model uses bipolar junction transistors and one uses MOSFET's. Each model has the main characteristics of the FFET, which are the current hysterisis with different gate voltages and decay of the drain current when the gate voltage is off. The drain current from each model has similar values to an actual FFET that was measured experimentally. The input and output resistance in the models are also similar to that of the FFET. The models are valid for all frequencies below RF levels. Each model can be used to design circuits using FFET's with standard electrical simulation packages. These circuits can be used in designing non-volatile memory circuits and logic circuits and are compatible with all SPICE based circuit analysis programs. The models consist of only standard electrical components, such as BJT's, MOSFET's, diodes, resistors, and capacitors. Each model is compared to the experimental data measured from an actual FFET.     

Drain current multiplication in thin pillar vertical MOSFETs due to depletion isolation and charge coupling

Drain current multiplication in vertical MOSFETs due to body isolation by the drain depletion region and gate–gate charge coupling is investigated at pillar thicknesses in the range of 200–10 nm. For pillar thickness >120 nm depletion isolation does not occur and hence the body contact is found to be completely effective with no multiplication in drain current, whereas for pillar thicknesses <60 nm depletion isolation occurs for all drain biases and hence the body contact is ineffective. For intermediate pillar thicknesses of 60–120 nm, even though depletion isolation is apparent, the body contact is still effective in improving floating body effects and breakdown. At these intermediate pillar thicknesses, a kink is also observed in the output characteristics due to partial depletion isolation. The charging kink and the breakdown behavior are characterized as a function of pillar thickness, and a transition in the transistor behavior is seen at a pillar thickness of 60 nm. For pillar thickness greater than 60 nm, the voltage at which body charging occurs decreases (and the normalized breakdown current increases) with decreasing pillar thickness, whereas for pillar thickness less than 60 nm, the opposite trend is seen. The relative contributions to the drain current of depletion isolation and the inherent gate–gate charge coupling are quantified. For pillar thickness between 120 and 80 nm, the rise in the drain current is found to be mainly due to depletion isolation, whereas for pillar thicknesses <60 nm, the increase in the drain current is found to be governed by the inherent gate–gate charge coupling.     

Gate leakage behavior of source/drain-to-gate non-overlapped MOSFET structure

In this paper, novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time. The gate leakage behavior of novel MOSFET structure has been investigated with help of compact analytical model and Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended source/drain region. It is found that optimal source/drain-to-gate non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and drain induced barrier lowering characteristic with a slight degradation in source/drain series resistance and effective gate capacitance.     

Analysis and reduction of radiated EMI noise from converter systems

It is well known that high dv/dt rates on switching devices are the source of EMI noise. This paper describes a mechanism and reduction methods of radiated EMI noise on IGBTs. The radiated EMI noise is generated by oscillating current flowing through the IGBT's output capacity and the snubber circuit, which we call equivalent circuit of radiated EMI noise. The oscillating current of the equivalent circuit is forced to flow by high dv/dt rates of IGBT switching operation. Radiated EMI noise can be analyzed by frequency evolution of oscillating current. The results of this analysis show the relationship of high‐frequency impedance of the equivalent circuit to radiated EMI noise, as well as the behavior of the IGBT's switching voltage waveform. In addition, it is indicated that using a di/dt control gate drive circuit is effective as a means for reducing radiated EMI noise. It is clarified that the standard for industrial equipment of CISPR can be satisfied by using the proposed gate drive circuit. The effects of the method have been verified by experimental and simulational results. © 1999 Scripta Technica, Electr Eng Jpn, 130(1): 106–117, 2000     

Development of gate drive circuit for next‐generation ultrahigh‐speed switching devices

This paper describes a gate drive circuit which is capable of driving an ultrahigh‐speed switching device and of suppressing high‐frequency noise caused by its high dV/dt ratio of 104 V/μs order. SiC (silicon carbide)‐based power semiconductor devices are very promising as next‐generation ultrahigh‐speed switching devices. However, one of their application problems is how to drive them with less high‐frequency noise without sacrificing their ultrahigh‐speed operation capability. The paper proposes a new gate drive circuit specialized for such devices, which charges and discharges the input capacitance of the device by using an impulse voltage generated by inductors. This ultrahigh‐speed switching operation causes a high‐frequency common‐mode noise current in the gate drive circuit, which penetrates an isolated power‐supply transformer due to the parasitic capacitance between the primary and the secondary windings. In order to overcome this secondary problem, a toroidal multicore transformer is also proposed in the paper in order to reduce the parasitic capacitance drastically. By applying the former technique, the turn‐on time and turn‐off time of the power device were shortened by 50% and by 20%, compared with a conventional push‐pull gate drive circuit, respectively. In addition, the latter technique allows reduction of the peak common‐mode noise current to 25%, compared with the use of a conventional standard utility power‐supply transformer. © 2011 Wiley Periodicals, Inc. Electr Eng Jpn, 176(4): 52–60, 2011; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.21124     

Physics-based drain current modeling of gate-all-around junctionless nanowire twin-gate transistor (JN-TGT) for digital applications

Vertically stacked dielectric separated independently controlled gates can be used to realize dual-threshold voltage on a single silicon channel MOS device. This approach significantly reduces the effective layout area and is similar to merging two transistors in series. This multiple independent gate device enables the design of new class of compact logic gates with low power and reduced area. In this paper, we present the junctionless concept based twin gate transistor for digital applications. To analyse the appropriate behaviour of device, this paper presents the modeling, simulation and digital overview of novel gate-all-around junctionless nanowire twin-gate transistor for advanced ultra large scale integration technology. This low power single MOS device gives the full functionality of “AND” gate and can be extended to full functionality of 2-input digital “NAND” gate. To predict accurate behaviour, a physics based analytical drain current model has been developed which also includes the impact of gate depleted source/drain regions. The developed model is verified using ATLAS 3D device simulator. This single channel device can function as “NAND” gate even at low operating voltage.     

Active cancellation of the common-mode voltage produced by a voltage-source PWM inverter

This paper proposes an “active common-mode noise canceler” that is capable of eliminating the common-mode voltage produced by a voltage source PWM (pulsewidth modulated) inverter. It generates a compensating voltage which has the same amplitude as, but the opposite phase to, the common-mode voltage produced by the PWM inverter. The compensating voltage is superimposed on the inverter output by a common-mode transformer. As a result, the common-mode voltage applied to the load is canceled completely. The design method of the active common-mode noise canceler is also presented in detail. A prototype has been constructed and tested to verify the effectiveness for an induction motor drive system of 3.7 kW using an IGBT (insulated gate bipolar transistor) inverter. Some experimental results show that the proposed active common-mode noise canceler makes a significant contribution to eliminating the common-mode current or the ground current, and it prevents an electric shock from being received by anyone handling it.     

Physical investigation of trap-related effects in power HFETs and their reliability implications

This paper presents a detailed physical investigation of trapping effects in GaAs power HFETs. Two-dimensional numerical simulations, performed using a hydrodynamic model that includes impact ionization, are compared with experimental results of fresh as well as hot-carrier-stressed HFETs in order to gain insight of intertwined phenomena such as the kink in the dc output curves, the hot-carrier degradation of the drain current, and the impact-ionization-dominated reverse gate current. Thoroughly consistent results show that: 1) the kink effect is dominated by the traps at the source-gate recess surface; and 2) as far as the hot-carrier degradation is concerned, only a simultaneous increase of the trap density at the drain-gate recess surface and at the channel-buffer interface (again at the drain side of the channel) is able to account for the simultaneous decrease of the drain current and the increase of the impact-ionization-dominated reverse gate current.     

Investigation of transient responses of nanoscale transistors by deterministic solution of the time-dependent BTE

In this work, the transient characteristics of nanoscale field-effect transistors (FETs) have been investigated using a deterministic solver based on the time-dependent multi-subband Boltzmann transport equation (BTE). The response to a step signal superimposed on the gate or drain electrode is simulated. The transient process can be understood as a combination of electrostatic and transport relaxation. The extracted transient relaxation time for the drain current, which is unrelated to the direct-current (DC) shift, is important for transient device modeling.     

Collapse of MOSFET drain current after soft breakdown

Gate-oxide soft breakdown (SB) can have a severe impact on MOSFET performance even when not producing any large increase of the gate leakage current. The SB effect on the MOSFET characteristics strongly depends on the channel width W: drain saturation current and MOSFET transconductance dramatically drop in transistors with small W after SB. As W increases, the SB effect on the drain current fades. The drain saturation current and transconductance collapse is due to the formation of an oxide defective region around the SB spot, whose area is much larger than the SB conductive path. Similar degradation can be observed even in heavy ion irradiated MOSFETs where localized damaged oxide regions are generated by the impinging ions without producing any increase of gate leakage current.     

正激式变换器输入端共模噪声的研究

噪声源的研究对噪声控制是十分重要的，掌握噪声特征是噪声控制方法比较以及滤波器设计的基础，本文以电路理论为基础，建立了单端正激式变换器由功率MOSFET的漏极与接地散热器之间寄生电容所引起的输入端共模噪声分析模型，借助于PSPICE仿真工具，分析了硬开关和软开关情况下所产生的共模噪声，本文的工作将有助于开关电源电磁干扰诊断和滤波器的设计。