Direct evidence of gate oxide thickness increase in tungstenpolycide processes

The increase of the effective gate oxide thickness for W-polycide processes is studied. The samples with as-deposited and annealed W polycide were analyzed by secondary ion mass spectrometry, transmission electron microscopy (TEM), and high-frequency CV measurements. The TEM cross section shows that the gate oxide thicknesses are ~244 and ~285 Å for as-deposited and 1000°C annealed samples, respectively. The TEM results agree with those from CV measurements. The TEM analyses provide direct physical evidence of an additional oxide thickness (~41 Å) during the W-polycide annealing     

Anomalous C-V characteristics of implanted polyMOS structure in n+/p+ dual-gate CMOS technology

The C-V characteristics of arsenic-doped polysilicon show a gate-bias dependence of the inversion capacitance and a reduction in the expected value of the inversion capacitance. The characteristics have been investigated with quasistatic and high-frequency C-V as well as conductance measurements of various capacitors that have been subjected to annealing times and temperatures ranging from 900°C/30 min to rapid thermal annealing at 1050°C. The results can be explained by assuming that there is a depletion region forming in the polysilicon due to insufficient activation of the dopant at the polysilicon/oxide surface. The impact of this condition on the device characteristics is shown to be a 20-30% reduction in the G_m of NMOS transistors with 125-Å Gate oxide thickness     

A study on the physical mechanism in the recovery of gatecapacitance to Cox in implanted polysilicon MOSstructures

The anomalous CV characteristics of MOS capacitor structures with implanted n⁺ polysilicon gate and p-type silicon substrate are studied through physical device simulation and experimental characterization over a wide range of frequencies and temperatures ranging from 100 to 250 K. It is shown that this anomalous CV behavior can be fully explained by the depletion of electrons and the formation of a hole inversion layer in the polysilicon gate due to energy band bending. The use of transistor structures for characterizing the polysilicon gate electrode is proposed. The results suggest thermal generation rather than impact ionization to be the dominant physical mechanism in supplying holes required by the inversion layer at the polysilicon-SiO₂ interface. This result also implies that hot-hole injection from the polysilicon gate into the SiO ₂ gate dielectric should not present a serious problem in device reliability     

Ultradry annealing after polysilicon electrode formation forimproving the TDDB lifetime of ultrathin silicon oxide films in MOSdiodes

Effects of ultradry annealing on time-dependent dielectric breakdown (TDDB) lifetime (T_TDDB) were investigated for Si MOS diodes with 5-nm-thick silicon oxide and P-doped polysilicon gate electrode films. This annealing was performed at 800°C in ultradry N₂ of less than 1-ppm moisture concentration after the electrode formation. Under an accumulation-bias stress condition, T_TDDB for the ultradry-annealed n-type Si diodes was larger than that for the conventionally annealed ones, while such T _TDDB enhancement was not confirmed in the p-type ones. Since positive charges induced near anode-side oxide interfaces are closely related to T_TDDB, the T_TDDB enhancement for the ultradry-annealed n-type Si diodes probably reflects a qualitative improvement of the anode-side, i.e., gate-electrode-oxide, interfaces by ultradry annealing     

Novel hydrogen annealing for forming SiO2 film by rapidthermal processing

Hydrogen annealing at 700-1100°C for 0-300 s has been combined with SiO₂ formation by rapid thermal processing (RTP). The SiO₂ films formed with the above processes were evaluated by C-V and I-V measurements and by time-dependent dielectric breakdown (TDDB) tests. These films provide longer time to breakdown andless positive charge generation than SiO₂ films formed without H₂ annealing. In particular, the SiO₂ formation-H₂ annealing SiO ₂ formation process is quite effective in improving the dielectric strength of the thin RTP-SiO₂ film     

Time-dependent dielectric breakdown characteristics ofN2O oxide under dynamic stressing

Time-dependent dielectric breakdown (TDDB) characteristics of MOS capacitors with thin (120-Å) N₂O gate oxide under dynamic unipolar and bipolar stress have been studied and compared to those with control thermal gate oxide of identical thickness. Results show that N₂O oxide has significant improvement in t _BD (2×under-V_g unipolar stress, 20×under+V_g unipolar stress, and 10×under bipolar stress). The improvement of t_BD in N₂O oxide is attributed to the suppressed electron trapping and enhanced hole detrapping due to the nitrogen incorporation at the SiO₂/Si interface     

Reduction of oxide charge and interface-trap density in MOScapacitors with ITO gates

The electrical properties of MOS capacitors with an indium tin oxide (ITO) gate are studied in terms of the number density of the fixed oxide charge and of the interface traps N_f and N _it, respectively. Both depend on the deposition conditions of ITO and the subsequent annealing procedures. The fixed oxide charge and the interface-trap density are minimized by depositing at a substrate temperature of 240°C at low power conditions and in an oxygen-rich ambient. Under these conditions, as-deposited ITO films are electrically conductive. The most effective annealing procedure consists of a two-step anneal: a 45-s rapid thermal anneal at 950°C in N₂, followed by a 30 min anneal in N₂/20% H₂ at 450°C. Typical values obtained for N_it and N_f are 4.2×10¹⁰ cm^-2 and 2.8×10¹⁰ cm^-2, respectively. These values are further reduced to 1.9×10¹⁰ cm^-2 and ≲5×10⁹ cm^-2, respectively, by depositing approximately 25 nm polycrystalline silicon on the gate insulation prior to the deposition of ITO     

An empirical model and an inversion technique for radar scatteringfrom bare soil surfaces

Polarimetric radar measurements were conducted for bare soil surfaces under a variety of roughness and moisture conditions at L -, C-, and X-band frequencies at incidence angles ranging from 10° to 70°. Using a laser profiler and dielectric probes, a complete and accurate set of ground truth data was collected for each surface condition, from which accurate measurements were made of the rms height, correlation length, and dielectric constant. Based on knowledge of the scattering behavior in limiting cases and the experimental observations, an empirical model was developed for σ°_hh, σ°_vv, and σ° _hv in terms of ks (where k=2π/λ is the wave number and s is the rms height) and the relative dielectric constant of the soil surface. The model, which was found to yield very good agreement with the backscattering measurements of the present study as well as with measurements reported in other investigations, was used to develop an inversion technique for predicting the rms height of the surface and its moisture content from multipolarized radar observations     

Electrical characteristics of highly reliable ultrathin hafniumoxide gate dielectric

Electrical and reliability properties of ultrathin HfO₂ have been investigated. Pt electroded MOS capacitors with HfO₂ gate dielectric (physical thickness ~45-135 Å and equivalent oxide thickness ~13.5-25 Å) were fabricated. HfO₂ was deposited using reactive sputtering of a Hf target with O₂ modulation technique. The leakage current of the 45 Å HfO₂ sample was about 1×10^-4 A/cm ² at +1.0 V with a breakdown field ~8.5 MV/cm. Hysteresis was <100 mV after 500°C annealing in N₂ ambient and there was no significant frequency dispersion of capacitance (<1%/dec.). It was also found that HfO₂ exhibits negligible charge trapping and excellent TDDB characteristics with more than ten years lifetime even at V_DD=2.0 V     

Improved transconductance under high normal field MOSFETs withultrathin nitrided oxides

The gate-voltage dependence of electron mobility at 298 and 82 K in MOSFETs with nanometer-range thin (reoxidized) nitrided oxides prepared by rapid thermal processing (RTP) at 900-1150°C for 15-300 s is discussed. Rapid nitridation improves the mobility and current derivability under high normal field over thermally grown oxides at both temperatures: the transconductance g_m at a gate drive of 3.5 V is improved by half an order of magnitude, whereas the peak g_m remains comparable to that of an oxide. Nitridation also avoids the negative g_m observed at 82 K for an oxide MOSFET. These improvements are substantially unchanged by additional reoxidations     

Off-state gate current in n-channel MOSFETs with nitrided oxidegate dielectrics

The authors report on the off-state gate current (I_g ) characteristics of n-channel MOSFETs using thin nitrided oxide (NO) gate dielectrics prepared by rapid thermal nitridation at 1150°C for 10-300 s. New phenomena observed in NO devices are a significant I_g at drain voltages as low as 4 V and an I_g injection efficiency reaching 0.8, as compared to 8.5 V and 10^-7 in SiO₂ devices with gate dielectrics of the same thickness. Based on the drain bias and temperature dependence, it is proposed that I_g in MOSFETs with heavily nitrided oxide gate dielectrics arises from hot-hole injection, and the enhancement of gate current injection is due to the lowering of valence-band barrier height for hole emission at the NO/Si interface. The enhanced gate current injection may cause accelerated device degradation in MOSFETs. However, it also presents potential for device applications such as EPROM erasure     

High performance low-temperature poly-Si n-channel TFTs for LCD

High-performance poly-Si TFTs were fabricated by a low-temperature 600°C process utilizing hard glass substrates. To achieve low threshold voltage (V_TH) and high field-effect mobility (μ_FE), the conditions for low-pressure chemical vapor deposition of the active layer poly-Si were optimized. Effective hydrogenation was studied using a multigate (maximum ten divisions) and thin-poly-Si-gate TFTs. The crystallinity of poly-Si after thermal annealing at 600°C depended strongly on the poly-Si deposition temperature and was maximum at 550-560°C. The V_TH and μ_FE showed a minimum and a maximum, respectively, at that poly-Si deposition temperature. The TFTs with poly-Si deposited at 500°C and a 1000-Å gate had a V _TH of 6.2 V and μ_FE of 37 cm²/V-s. The high-speed operation of an enhancement-enhancement type ring oscillator showed its applicability to logic circuits. The TFTs were successfully applied to 3.3-in.-diagonal LCDs with integration of scan and data drive circuits     

Microwave shielding effectiveness of EC-coated dielectric slabs

Correct formulas for the microwave shielding effectiveness (SE ) of a thin metallic layer deposited on top of a dielectric slab are derived. For coatings much thinner than the skin depth, the following holds: (a) in a half-wave geometry, SE is a function of a sheet resistance only, SE (in dB)=20×log(1+188.5/R_s) if R_s is in ohms per square; (b) in a quarter-wave geometry, SE (in dB)=20×log[(1+ε_r)/(2√ε _r)+188.5/(√ε_rR_s)], where ε_r refers to the dielectric constant of the substrate. These formulas provide upper and lower limits for the effective shielding performance of an electroconductive coated dielectric slab     

A comprehensive study on p+ polysilicon-gate MOSFET'sinstability with fluorine incorporation

It is reported that fluorine can jeopardize p⁺-gate devices under moderate annealing temperatures. MOSFETs with BF₂ or boron-implanted polysilicon gates were processed identically except at gate implantation. Evidence of boron penetration through 12.5-nm oxide and a large quantity of negative charge penetration (10 ¹² cm^-2) by fluorine even at moderate annealing conditions is reported. The degree of degradation is aggravated as fluorine dose increases. A detailed examination of the I-V characteristics of PMOSFET with fluorine incorporated p⁺-gate revealed that the long gate-length device had abnormal abrupt turn-on I_d-V_g characteristics, while the submicrometer-gate-length devices appeared to be normal. The abnormal turn-on I_d-V_g characteristics associated with long-gate-length p⁺-gate devices vanished when the device was subjected to X-ray irradiation and/or to a high-voltage DC stressing at the source/drain. The C-V characteristics of MOS structures of various gate dopants, processing ambients, doping concentrations, and annealing conditions were studied. Based on all experimental results, the degradation model of p⁺-gate devices is presented. The incorporation of fluorine in the p⁺ gate enhances boron penetration through the thin gate oxide into the silicon substrate and creates negative-charge interface states. The addition of H/OH species into F-rich gate oxide will further aggravate the extent of F-enhanced boron penetration by annealing out the negative-charge interface states     

High performance damascene metal gate MOSFETs for 0.1 μm regime

A novel transistor formation process (damascene gate process) was developed in order to apply metal gates and high dielectric constant gate insulators to MOSFET fabrication and minimize plasma damage to gate insulators. In this process, the gate insulators and gate electrodes are formed after ion implantation and high temperature annealing (~1000°C) for source/drain formation, and the gate electrodes are fabricated by chemical mechanical polishing (CMP) of gate materials deposited in grooves. Metal gates and high dielectric constant gate insulators are applicable to the MOSFET, since the processing temperature after gate formation can be reduced to as low as 450°C. Furthermore, process-damages on gate insulators are minimized because there is no plasma damage caused by source/drain ion implantation and gate reactive ion etching (RIE). By using this process, fully planarized metal (W/TiN or Al/TiN) gate transistors with SiO₂ or Ta₂O₅ as gate insulators were uniformly fabricated on an 8-in wafer. Further, the damascene metal gate transistors exhibited low gate sheet resistivity, no gate depletion and drastic improvement in gate oxide integrity, resulting in high transistor performance     

Effects of post-deposition annealing on the electrical propertiesand reliability of ultrathin chemical vapor deposited Ta2O5 films

This paper reports the effects of post-deposition rapid thermal annealing on the electrical characteristics of chemical vapor deposited (CVD) Ta₂O₅ (~10 nm) on NH₃-nitrided polycrystalline silicon (poly-Si) storage electrodes for stacked DRAM applications. Three different post-deposition annealing conditions are compared: a) 800°C rapid thermal O₂ annealing (RTO) for 20 sec followed by rapid thermal N₂ annealing (RTA) for 40 sec, b) 800°C RTO for 60 sec and c) 900°C RTO for 60 see. Results show that an increase in RTO temperature and time decreases leakage current at the cost of capacitance. However, over-reoxidation induces thicker oxynitride formation at the Ta₂O₅/poly-Si interface, resulting in the worst time-dependent dielectric breakdown (TDDB) characteristics     

Annealing-temperature dependence of the thermal conductivity ofLPCVD silicon-dioxide layers

The authors point out that the reliability and performance of electronic circuits are influenced by heat conduction in low-pressure chemical-vapor-deposited (LPCVD) silicon dioxide layers. Here, the effective thermal conductivity k_eff for conduction normal to films of LPCVD silicon dioxide layers as a function of annealing temperature, as well as for films of thermal and SIMOX oxides, is measured. The LPCVD oxide thermal conductivity increases by 23% due to annealing at 1150°C. The conductivities k_eff of LPCVD layers of thicknesses between 0.03 and 0.7 μm are higher than those reported previously for CVD layers, and vary between 50% and 90% of the conductivities of bulk fused silicon dioxide. The values of SIMOX and thermal oxide layers are within the experimental error of the values for bulk fused silicon dioxide     

Rapid thermal anneal of gate oxides for low thermal budget TFT's

The performance and reliability of deposited gate oxides for thin film transistors (TFT's) has been studied as a function of rapid thermal annealing (RTA) conditions. The effect of temperature ranging from 700 to 950°C and the annealing ambients including oxygen (O₂), argon (Ar), and nitrous oxide (N₂O) is investigated. Improvement in charge to breakdown (Q_bd) is seen starting from 700°C, with marked increase at 900°C temperature and above. The N₂O and Ar ambients result in higher Q_bd compared to O₂ ambient and we attribute this to reduced interfacial stress. Fourier Transform Infrared spectroscopy (FTIR) is used to qualitatively measure the stress. The bias temperature instability is decreased by RTA. The TFT characteristics are significantly improved with RTA gate oxide. The RTA-Ar anneal at 950°C results in the lowest trap density in TFT's as measured from charge pumping technique     

Temperature sensitivity of phase-matched second-harmonic generationin LiIO3

Measurements were made of the temperature dependence (between 23 and 65°C) of the phase-matching angle &thetas;_pm for type I frequency doubling of 1064-nm laser light in lithium iodate (LiIO₃). The measured value of d&thetas;_pm/dT is -14.7±1 μrad/°C, which corresponds to a thermal sensitivity β_T =0.24±0.02 cm^-1/°C for this process. Also calculated is a value of d&thetas;_pm/dT using experimentally determined thermooptic data available in the literature. The calculated value of d&thetas;_pm/dT is -31±18 μrad/°C using literature values of n and dn/dT for LiIO₃. The extreme sensitivity of the calculated value of d&thetas;_pm/dT to small errors in the thermooptic coefficients may be the reason for this discrepancy     

Improvement in radiation hardness of reoxidized nitrided oxide(RNO) in the absence of post-oxidation anneal

A simple radiation-hard process for rapid thermal reoxidized nitrided oxide (RNO) structures is proposed. This process involves fast pulling (FP) of samples out of the furnace in a mixture of oxygen and nitrogen immediately after the oxidation has been completed. Samples with starting oxides prepared by conventional postoxidation annealing (POA) are also compared. It is found from CV curves that the initial interface property of an RNO structure with a fast pulled starting oxide (RNO_FP) is almost the same as that with a postoxidation annealed starting oxide (RNO_POA); however, after being exposed to Co-60 irradiation, the former becomes superior to the latter. Excess oxygen left at interface in the starting oxide during the fast pulling procedure might be the origin of the radiation-hard property for RNO_FP structures