Electrical and Reliability Studies of “Wet N2O” Tunnel Oxides Grown on Silicon for Flash Memory Applications

In this paper, we report the electrical characteristics and reliability studies on tunnel oxides fabricated by "wet N₂O" oxidation of silicon in an ambient of water vapor and N₂O at a furnace temperature of 800 degC. Tunnel oxides that have an equivalent oxide thickness of 67 A are subjected to a constant-current stress (CCS) amount of -100 mA/cm² using a MOS capacitor to obtain information on stress-induced leakage current (SILC), interface, and bulk trap generation. The obtained results clearly demonstrate the superior performance features of the present tunnel oxides with reduced SILC, lower trap generation, minimum change in gate voltage, and higher charge-to-breakdown during CCS studies. X-ray photoelectron spectroscopy depth profile studies of the tunnel oxide interfaces have shown that the improved performance characteristics and reliability can be attributed to the incorporation of about 8.5% nitrogen at the oxide-silicon interface of the samples formed by the "wet N₂O" process that involves low-temperature oxidation and annealing at 800 degC.     

Reliability of Low-Temperature-Processing Hafnium Oxide Gate Dielectrics Prepared by Cost-Effective Nitric Acid Oxidation Technique

In this paper, the physical and electrical characteristics of low-temperature-processing hafnium oxide (HfO₂) films are studied. A simple cost-effective room-temperature process was introduced to prepare high-k HfO₂ dielectrics. A novel technique of direct oxidation of an ultrathin Hf metal by nitric acid, followed by rapid thermal annealing in N₂ is demonstrated. The prepared HfO₂ gate dielectrics show good uniformity, low leakage currents, high breakdown field, and superior reliability under electrical stressing. The long-term ten-year lifetime was also evaluated by a time-dependent-dielectric-breakdown analysis to project the maximum operation voltage of -1.8 V for HfO₂ gate stacks. This low-temperature oxidation technology for preparing high-quality high-k HfO₂ dielectrics is promising for flat-panel-display applications.     

Enhancement in ultrathin oxide growth by thermal-induced tensile stress

Rapid-thermal oxide grown under the condition that a certain portion of the substrate wafer was covered by another wafer with special shape was studied. It is interesting to find that in the ultrathin oxide regime, the thickness of oxide with covered wafer is even larger than that without. Thermal-induced tensile stress is believed to be the origin of the above enhanced oxidation rate. A novel ultrathin oxide grown at a low temperature of 800/spl deg/C is demonstrated. The capacitance-voltage and current-voltage characteristics of MOS capacitors with oxides grown with and without cover wafers under the same oxide thickness were compared.     

Stacked dual-oxide MOS energy band diagram visual representation program (IRW student paper)

Energy band diagrams for MOS devices are essential for understanding device performance and reliability. Introduction of high-k gate stacks with a silicon dioxide (SiO/sub 2/) interfacial layer requires an even greater understanding of the energy band behavior. A program that quickly determines the band diagrams based on a simple analytical model was created. It is used to explore the behavior of various oxide stacks with the ability to easily vary important parameters like oxide material, electron affinity, bandgap, dielectric constant, and thickness. The usefulness of this program to predict potential reliability issues is also demonstrated.     

Scaling the modulation bandwidth and phase efficiency of a silicon optical modulator

We present an optimized design and detailed simulation of an all-silicon optical modulator based on a silicon waveguide phase shifter containing a metal-oxide-semiconductor (MOS) capacitor. Based on a fully vectorial Maxwell mode solver, we analyze the modal characteristics of the silicon waveguide. We show that shrinking the waveguide size and reducing gate oxide thickness significantly enhances the phase modulation efficiency because of the optical field enhancement in the voltage induced charge layers of the MOS capacitor, which, in turn, induce refractive index modulation in silicon due to free carrier dispersion effects. We also analyze the device speed by transient semiconductor device modeling. As both optical absorption and modulation bandwidth increase with increasing doping concentration, we show that, with a nonuniform doping profile in the waveguide, balance between the device operation speed and optical loss can be realized. Our simulation suggests that a TE-polarized optical phase modulator with a bandwidth of 10 GHz and an on-chip optical loss less than 2 dB is achievable in silicon.     

"Ramp Differentiation" C(V) Measurement of MOS Structures for Thermally Grown Oxide Quality Analysis

A new simplified and economical technique, suitable for instructional use, to obtain experimental C(V) plots for MOS structures is described. Comparison of theoretical and experimental C(V) characteristics allows determining the number of excess charges in the thermally grown oxide, serving as an economical quality gauge for the oxide-growing process.     

SILC effects on E2PROM memory cell reliability

In this paper, we will investigate SILC effects on the reliability of E²PROM memories. Particularly, we will analyze the influence on the retention properties of E²PROM memory devices of program/erase number of cycles and bias conditions, oxide thickness scaling and quality, and storage field. To accomplish this task, we will use a recently proposed compact E²PROM model, which has been extended to include the stress-induced leakage current (SILC), thus bridging the gap between the oxide quality characterization activity performed on MOS transistors and capacitors, and the actual impact of SILC on the functioning of E²PROM memories     

一种高氧化物含量AgCdO触点在GMC交流接触器中的应用

介绍了一种高氧化物含量AgCdO材料的试制,进行了不同内氧化工艺条件下触点材料力学物理性能的比较和分析,选取最佳方案产品在GMC-50三极交流接触器中进行AC-4电性能试验,结果表明,触点在56 000次电寿命内性能可靠,温升满足要求。所研究材料可以达到良好的节银效果。     

Y2O3/La2O3/Al2O3/Cu复合材料的制备与性能

采用含氧氮气(N2/O2)雾化喷射沉积技术制备Y-La-Al-Cu系多元系合金,通过化学反应原位生成(内氧化法)Y2O3/La2O3/Al2O3/Cu多相氧化物颗粒增强铜基复合材料,并对材料的显微组织、力学物理性能和电学性能进行研究。结果表明,通过喷射沉积技术并结合内氧化工艺,可制得具有较好微观组织、形成的增强相弥散分布于基体、组织致密的Y2O3/La2O3/Al2O3/Cu多相氧化颗粒增强铜基复合材料;随着冷加工变形量的增加,Y2O3/La2O3/Al2O3/Cu多相氧化颗粒增强铜基复合材料的抗拉强度和硬度提高,而材料的延伸率与导电率逐渐降低。     

Crosstalk overshoot/undershoot analysis and its impact on gate oxide reliability in multi-wall carbon nanotube interconnects

The work in this paper analyzes the crosstalk effects in Multi-wall Carbon Nanotube (MWCNT) based interconnect systems, and its impact on the reliability of the gate oxide of MOS devices. The electrical circuit parameters for interconnect are calculated using the existing models of MWCNT and the equivalent circuit has been developed to perform the crosstalk analysis. The crosstalk induced overshoot/undershoots have been estimated and the effect of the overshoot/undershoots on the gate oxide reliability is calculated in terms of failure-in-time (FIT) rate of the MOS devices. Single, double, and bundle of MWCNTs are considered for the analysis. The results are compared with that of traditional Cu based interconnects. It has been found that the average failure rate due to crosstalk overshoot/undershoots is ??10 to 100 times less in MWCNT based interconnect of length between 10 ??m to 50 ??m as compared to the copper based interconnects. Our analysis shows the applicability of MWCNTs in future VLSI circuits from the perspective of gate oxide reliability. The results also reveal that single or double MWCNT of large diameter is better than bundle of MWCNTs of smaller diameter.     

Effect of metal contaminants in pre-gate oxide cleans for sub-100-nm devices

Metal contaminants at trace levels in the pre-gate oxide clean solutions have always been a concern with scaling down trends in CMOS-based devices. The effect of multielement contamination (alkali, transition, and noble metals up to 200 ppb levels) in dilute hydrofluoric acid (DHF), standard clean one (SC1), and standard clean two (SC2) solutions is investigated for an Intel Pentium-based sub-100-nm microprocessor technology. The main significance of this work is to achieve a rational specification for process chemical purity. Results from surface analyses of monitor wafers and device level electrical measurements of production scale wafers along with yield and reliability analyses are presented in this paper. Deposition of metallic contaminants from clean solutions has been explained qualitatively based on electrochemical theory of reduction potentials. Among the 35 elements investigated in this study, only platinum at very low parts-per-billion levels in the HF-based cleans has been found to affect the gate oxide integrity producing zero yield. An increase in the surface roughness (2-8/spl times/) was also observed with silicon monitor wafers for 100-ppb-platinum-contaminated DHF solutions and could play an important role in degrading the gate oxide performance. Other alkali and transition metals including copper up to 200 ppb levels in the HF-based cleans studied here did not show any deleterious effects in the gate oxide integrity and product reliability measurements. The effect of contamination in the SC1 and SC2 cleans was negligible even for 100 ppb platinum. Significant cost reduction can be realized by safely relaxing the process chemical contamination disposition limits for alkali and transition elements.     

A new polyimide film for VLSI and its electrical characterization

Multilevel structures consisting of alternating metal and dielectric layers are necessary to achieve interconnection in high density or VLSI (very large scale integration) circuits using either MOS or bipolar technology. Polyimide is one of the excellent high temperature heat-resistant polymers in organic materials and has good planarization capability and electrical insulating properties. In this work, following the synthesis of DAPDS (4,4'-bis (3-aminophenoxy)diphenyl sulfone), by nucleophilic aromatic substitution of 4,4'-dichlorodiphenyl sulfone with m-aminophenol, DAPDS/pyromellitic dianhydride based soluble and processable fully imidized polyimide was synthesized successfully by using solution imidization technique. Using this specific polyimide, a metal-polyimide-silicon MIS (metal polyimide silicon) structure was manufactured. Electrical properties of the MIS capacitance have been examined. The planarizing and patterning characteristics and electrical characteristics such as current vs. voltage, breakdown field strength, permittivity and capacitance vs. voltage for quasi-static and high frequency measurements are discussed. The results are compared with conventional dielectric films used in integrated circuit fabrication     

高压大功率器件用高温栅偏测试装置研制

为准确评估硅IGBT和碳化硅MOSFET等高压大功率器件不同电应力及热应力条件下的栅极可靠性,研制了实时测量皮安级栅极漏电流的高温栅偏（high temperature gate bias,HTGB）测试装置。此外,该测试装置具备阈值电压在线监测功能,可以更好地监测被测器件的状态以进行可靠性评估和失效分析。为初步验证测试装置的各项功能和可靠性,运用该测试装置对商用IGBT器件在相同温度应力不同电应力条件下进行分组测试。初步测试结果表明老化初期漏电流逐渐降低,最终漏电流大小与电压应力有良好的正相关性,栅偏电压越大,漏电流越大。该测试装置实现了碳化硅MOSFET器件和硅IGBT器件对高温栅偏的测试需求且适用于各种类型的封装。     

Effects of internal postoxidation on the oxygen deficiency and dielectric strength of buried oxide formed by the separation‐by‐implanted‐oxygen (SIMOX) process

Effects of internal postoxidation on buried silicon dioxide have been studied. The dioxide examined was the buried insulator in a silicon‐on‐insulator (SOI) structure fabricated by implantation of oxygen ions into Si, or the SIMOX process. Internal postoxidation is an oxidation process applied to the SOI structure after its fabrication. It was observed that the photoluminescence intensity due to neutral oxygen vacancies (O₃≡Si–Si≡O₃, “≡” denotes three separate bonds to oxygens) increased after the internal oxidation. The oxide thickness and the number of E centers (O₃≡Si·, “·” denotes an unpaired electron) were also found to increase similarly. The measurements repeatedly done by changing the oxide thickness revealed that the increased part of oxide by the internal oxidation contains the vacancies with a similar density to the original part. It is concluded that the internal oxidation scarcely affects the oxygen deficiency of the oxide. It was also observed that the number of breakdowns at low electric fields remarkably decreased after the internal oxidation, indicating that electrically weak spots such as silicon pipes were effectively reduced. © 1999 Scripta Technica, Electr Eng Jpn, 130(1): 15–20, 2000     

The application of porous silicon to optical waveguiding technology

The porosification of silicon can be achieved by the partial electrochemical dissolution (anodization) of the surface of a silicon wafer. The degree of porosity is dependent on the anodization parameters and can generally be controlled within the constraints imposed by substrate dopant type and concentration. Control of porosity leads to control of refractive index, and therein lies the concept of using porous silicon as an optical waveguide. We discuss porous silicon wavegides, for the visible to the infrared, produced by a number of approaches: 1) epitaxial growth onto porous silicon (where the porous layer acts as a substrate for a higher refractive index waveguide epilayer); 2) ion implantation (where either selective areas of high electrical resistivity can be produced, which act as a barrier against porosification, or where the surface of a porosified layer is amorphised to form a waveguide; 3) porous silicon multilayers (where the anodization parameters are periodically varied to produce alternate layers of different porosity and thus refractive index); and 4) oxidation of porous silicon (where a porosified layer is oxidized to form a graded-index, dense or porous, oxide waveguide)     

Charge storage in double layers of thermally grown silicon dioxideand APCVD silicon nitride

Experimental results on charge storage and discharge in double layers of silicon dioxide and silicon nitride will be reported and discussed. SiO₂ with a thickness of 300 nm was thermally grown on silicon wafers, while cover layers of Si₃N₄ with thicknesses of 50, 100, and 150 nm were deposited chemically at atmospheric pressure. The samples were charged by the point-to-grid corona method. At room temperature, the measured surface potential V was stable during a period of almost three years. Isothermal measurements under different environmental conditions showed an improved charge retention compared to a single layer grown silicon dioxide. After ~3 h at 300°C, the observed voltage drop was <10% for the double layers and ~60% for bare SiO₂. Similar results were obtained under a humid condition of 95%RH and 60°C. Besides, thermally stimulated current (TSC) was measured in setup with a temperature ramp of 200°C/h. For the double layers, a current peak with a maximum temperature at ~500°C was observed. The measured current in the range of 300 to 400°C, the location of current maxima observed in thermally grown silicon dioxide or APCVD silicon nitride, was negligible. In addition to improved electret properties the internal stress in the investigated double layers can be adjusted by a proper thickness ratio of oxide layer to nitride layer. Therefore double layers of silicon dioxide and nitride seem to be promising materials for integrated sensors and actuators based on the electret effect     

Application of HfO2 high-k gate insulator for excimer laser annealed poly-Si TFT

The electrical characteristics of polycrystalline silicon (poly-Si) thin film transistor (TFT) crystallized by excimer laser annealing (ELA) method with high-k gate dielectrics were evaluated. Because a high thermal budget is inevitable for conventional fabricating process of poly-Si TFTs, an amorphous silicon film on a buried oxide was crystallized by annealing with a KrF excimer laser (248) to fabricate a poly-Si film at low temperature. Furthermore, the high permittivity HfO₂ film with a thickness of 20 nm as the gate-insulator was deposited by atomic layer deposition (ALD) to low temperature process. In addition, the solid phase crystallization (SPC) was compared to the ELA method as a crystallization technique of amorphous-silicon film. As a result, the crystallinity and surface roughness of poly-Si crystallized by ELA method was superior to the SPC method. Also, we obtained excellent device characteristics from the poly-Si TFT fabricated by the ELA crystallization method.     

Enhanced SiO/sub 2/ reliability on deuterium-implanted silicon

Stress-induced leakage current and time-dependent dielectric breakdown were investigated to examine the reliability of gate oxides grown on hydrogen- and deuterium-implanted silicon substrates. An order of magnitude improvement in charge-to-breakdown was observed for the deuterium-implanted devices as compared with the hydrogen-implanted ones. Such reliability improvement may be explained by the reduction of defects in the SiO/sub 2/ and Si/SiO/sub 2/ interface, such as Si dangling bonds, weak Si-Si bonds, and strained Si-O bonds due to the retention of implanted deuterium at the interface and in the bulk oxide as confirmed by secondary ion mass spectroscopy.     

Buffer layer dependence of memory effects for SrBi2Ta2O9 on Si

Abstract

The ability to form a high-quality buffer layer between the ferroelectric layer and the underlying silicon substrate is of critical importance. A suitable buffer layer must provide an acceptable electronic interface with the silicon substrate, and also must be able to prevent intermixing between the ferroelectric material and the underlying silicon, as well as prevent oxidation of the latter during device processing. This paper reports the properties of jet-vapor deposited silicon nitride and thermally grown silicon oxide as the buffer. Results from TEM, EDS, XRD and AFM micrographs will be presented, along with some electrical data taken from corresponding memory capacitor structures.