Source/drain contact resistance of silicided thin-film SOI MOSFET's

We developed a source/drain contact (S/D) resistance model for silicided thin-film SOI MOSFET's, and analyzed its dependence on device parameters considering the variation in the thickness of the silicide and residual SOI layers due to silicidation. The S/D resistance is insensitive to the silicide thickness over a wide range of thicknesses; however, it increases significantly when the silicide thickness is less than one hundredth of initial SOI thickness, and when almost all the SOI layer is silicided. To obtain a low S/D resistance, the specific contact resistance must be reduced, that is, the doping concentration at the silicide-SOI interface must be more than 10²⁰ cm^-3     

An analytical drain current model for submicrometer and deepsubmicrometer MOSFET's

In this paper, we present a new, analytical, and physics-based drain current model for both submicrometer and deep submicrometer MOSFET's. The model was developed by starting from a two-dimensional (2D) Poisson equation and using the energy balance equation. Using the present model, we can clearly see that the drain current increases with decreasing channel length due to a larger average channel mobility at shorter channel length. The formulas for the saturation drain voltage and the drain current can be reduced to their corresponding well-known formulas in the submicrometer range. The accuracy of the presented model has been verified with the experimental data of metal-oxide-semiconductor (MOS) devices with various geometries     

A modified lightly doped drain structure for VLSI MOSFET's

A new n-MOS LDD-like device structure (the J-MOS transistor) is proposed. Its design, simulation, and fabrication are studied in this paper, n-channel MOSFET's with Leffbelow 2 µm suffer from high-field effects that must be overcome to secure reliable 5-V operation. LDD structures alleviate these effects, but their reliability is better than that of conventional MOSFET's only if the n^-regions have a peak doping density above 1 × 10¹⁸cm^-3. To overcome this limitation and to allow constant voltage scaling for devices into the submicrometer regime, the J-MOS structure uses a series drain JFET to drop part of the supply voltage. Both 2-D device simulations and experimental results are presented to demonstrate the operation of this device and its potential for applications requiring reliable submicrometer device operation under maximum supply voltage. The major experimental findings are that the J-MOS structure can sustain 5-V operation even for submicrometer effective channel lengths. As has been the case with all LDD-like structures, improved device reliability has been achieved at the expense of some performance. However, the advantages of keeping 5-V operation in micrometer-sized devices may outweigh this performance loss.     

Comparison of drain structures in n-channel MOSFET's

Practical limitations in channel lengths for n-channel MOSFET'S under 5-V operation are discussed for conventional arsenic-drain, phosphorus-drain, phosphorus-arsenic double diffused drain (DDD), and lightly doped drain (LDD) structures. Process parameter dependence of device characteristics and optimal process conditions are also evaluated for each drain structure. It is clarified that the minimum usable channel length is about 0.7-µm, which is realized by the DDD and LDD devices. In these devices, the hot-carrier-induced device degradation is no longer a major restriction on minimum channel length, but the short-channel effect and the parasitic bipolar breakdown are dominant restrictions. The phosphorus drain with a shallow junction formed by rapid thermal annealing can expand the arsenic drain limitation.     

Gate-oxide breakdown accelerated by large drain current inn-channel MOSFET's

A study of the time-dependent dielectric breakdown (TDDB) of thin gate oxides in small n-channel MOSFETs operated beyond punchthrough is discussed. Catastrophic gate-oxide breakdown is accelerated when holes generated by the large drain current are injected into the gate oxide. More specifically, the gate-oxide breakdown in a MOSFET (gate length=1.0 μm, gate width-15 μm) occurs in ~100 s at an applied gate oxide field of ~5.2 MV/cm during the high drain current stress, while it occurs in ~100 s at an applied gate oxide field of ~10.7 MV/cm during a conventional time-dependent dielectric breakdown (TDDB) test. The results indicate that the gate oxide lifetime is much shorter in MOSFETs when there is hot-hole injection than that expected using the conventional TDDB method     

Effects of interfacial Oxide layer on short-channel polycrystalline source and drain MOSFET's

Using a novel self-alignment approach, the characteristics of polycrystalline source and drain MOSFET's with and without a deliberately grown oxide under the polycrystalline regions are compared. The interfacial oxide is shown to suppress short-channel effects in the shortest channel devices studied, but this improvement is at the expense of increased source-to-drain contact resistance in the present devices. The devices without the interfacial oxide are also expected to have superior hot-carrier performance.     

Degradation of short-channel MOSFET's under constant current stress across gate and drain

We have employed a technique of constant current stress between the gate and drain of a MOS transistor to study the degradation of the threshold voltage, transconductance, and substrate current characteristics of the transistor. From the transistor characteristics, we propose that the degradation mechanism is a combined effect of trapping of holes in the gate oxide created by impact ionization due to the high electric field (> 8 MV/cm) across the oxide, and electron trapping phenomena. The degradation characteristics of the transistor under this constant current stress are quite similar to that observed normally due to the injection of hot electrons in the gate oxide when the transistor is biased in "ON" condition and the gate and drain voltages are selected to produce maximum substrate current.     

Comparison of channel current and drain avalanche current-induced hot-carrier effects in MOSFET's

Hot-carrier effects induced by the channel current and the drain avalanche current in short-channel MOSFET's are investigated and compared by characterizing the substrate current at different stages of stress. Not only does the drain avalanche stress (DAS) degrade devices much faster than the triode region stress (TCS) does, but the substrate current versus the stress time shows a characteristic difference between the DAS mode and the TCS mode. The difference is that the DAS mode involves localized interface trap generation near the drain and more widely distributed hole trapping in the oxide, while in the TCS mode the mechanism is mainly localized electron trapping in the oxide.     

Spreading resistance in submicron MOSFET's

The spreading resistance due to current crowding at the end-points of an FET channel is investigated. An analytic expression is derived giving this resistance as function of a few parameters. Two-dimensional numerical simulations, using finite-element techniques, confirm the accuracy of the simple analytical approach. For short channel devices the current crowding effect is found to give a nonnegligible contribution to the total source resistance. In order to optimize the FET performance, the geometry and conductivity of the source/drain regions must be carefully designed, trading off short channel effect and transconductance degradation.     

Source to drain resistance beyond pinch-off in metal-oxide-semiconductor transistors (MOST)

A detailed analysis is performed yielding source to drain resistance of MOS transistors in the saturation region. The analysis is based on a depletion model of the pinched-off region of the channel. Good agreement is found between theory and experimental results obtained onN-channel silicon MOS transistors (channel length ∼5 µ).     

The spreading resistance of MOSFET's

A simple mathematical expression for source and drain spreading resistance near the channel end of MOSFET's has been derived by calculating the capacitance of the same geometry, using the analogy between the resistivity of conductors and the permittivity of dielectrics (R = ρε/C). Furthermore, it is shown qualitatively and experimentally that the value of the resistivity, which is the most influential parameter in the equation derived, should be determined by a doping concentration equal to the inversion channel carrier concentration, rather than by the source and drain bulk properties.     

Physically-based threshold voltage determination for MOSFET's ofall gate lengths

A reliable method to determine the threshold voltage V_th for MOSFETs with gate length down to the sub-0.1 μm region is proposed. The method determines V_th by linear extrapolation of the transconductance g_m to zero and is therefore named “GMLE method”. To understand the physical meaning of the method and to prove its reliability for different technologies 2-D simulation was applied. The results reveal that determined V_th values always meet the threshold condition, i.e., the onset of inversion layer buildup     

Source-and-drain series resistance of LDD MOSFET's

The introduction of n- regions makes an LDD MOSFET behave differently from a conventional MOSFET. The source-and-drain series resistance, which consists of the n+-and-n-regions, shows a strong dependence on the gate bias. Also, the apparent effective length can vary with gate bias. These special features cause the traditional method to determine effective channel length and series resistance inapplicable. In this letter, we propose a method to determine the "intrinsic" channel length and gate-voltage-dependent source-and-drain series resistance of an LDD MOSFET and a modal for the LDD device current at small drain-source voltage.     

Measurement of intrinsic capacitance of lightly doped drain (LDD) MOSFET's

Intrinsic capacitance of lightly doped drain (LDD) MOSFET's is measured by means of a four-terminal method without using any on-chip measurement circuits. The gate-to-drain capacitance Cgdof LDD MOSFET's is smaller than that of conventional MOSFET's in the saturation region. The technique is applied to determine the effective channel length.     

Source?drain follower for monolithically integrated sensor array

A source-drain follower has been designed and implemented in 1.2 mum standard CMOS technology. The circuit acts as a voltage follower, in which a sensing transistor is operated at fixed gate-source and gate-drain voltages, and operates at 10 nW with 10 mV accuracy in a 24 times 65 mum active area.     

MOSFET's with PolySilicon gates self-aligned to the field isolation and to the source and drain regions

The fabrication procedure and device characteristics of MOSFET's having a unique gate electrode structure are described. The polysilicon gate electrode of the structure is self-aligned on its ends with respect to the conductive source and drain regions, and is also self-aligned on its sides with respect to the nonconductive field oxide isolation regions. This double self-alignment feature results in a polysilicon gate electrode area that matches the channel region of the FET. Another novel feature of this "recessed-gate" device is a self-registering electrical connection between the gate and the metallic interconnection pattern. Compared to MOSFET's fabricated using more conventional methods, smaller FET's with increased packing density result from this misregistration-tolerant contacting technique and the doubly self-aligned gate electrode structure. The new FET structure may be applied to various integrated circuits such as ROM's, PLA's, and dynamic RAM's. The use of a second layer of polysilicon and the addition of a fifth masking operation yields a dynamic RAM cell of small area with a diffused storage region.     

Analysis of the gate-voltage-dependent series resistance of MOSFET's

The intrinsic parasitic series resistance that occurs near the channel end of a MOSFET is analyzed. This new model includes the effects due to the unavoidable doping gradient near the metallurgical junction. It is assumed that current first conducts through the accumulation layer before spreading into the bulk region, and thus the spreading (injection) resistance and the accumulation layer resistance have to be considered in series and both are gate-voltage dependent. More importantly, they are shown to be a strong function of the steepness of the doping profile. The model quantitatively predicts these resistance components for a given process, and it emphasizes the necessity for a steep junction profile in order to minimize the series resistance of MOSFET's.     

Gate-voltage-dependent effective channel length and series resistance of LDD MOSFET's

A measurement algorithm to extract the effective channel length and source-drain series resistance of MOSFET's is presented. This extraction algorithm is applicable to both conventional and LDD MOSFET's. It is shown that the effective channel length and the source-drain series resistance of an LDD device are gate-voltage dependent. The effective channel length of an LDD device is not necessarily the metallurgical junction separation between the source and drain as it is commonly seen in a conventional device. A more generalized interpretation of effective channel length is introduced to understand the physical meaning of this gate-voltage dependence. The result also indicates that the effective channel length and source-drain resistance are two inseparable device parameters regardless of LDD or conventional FET's.     

Nonscaling of MOSFET's linear resistance in the deep submicrometerregime

This paper investigates the scaling properties of deep submicron MOSFET's and shows that, while in a wide range of channel lengths they can be represented as composed by a scaling intrinsic and a nonscaling parasitic part, this picture does no longer hold for shorter transistors. A nonscaling of the total resistance R_TOT=[V_DS/I_DS] of short devices is observed, and its impact on parasitic resistances and effective channel length extraction is discussed. A possible explanation is suggested in relation to the two-dimensional substrate doping redistribution linked to reverse-short-channel effects     

Parasitic source and drain resistance in high-electron-mobility transistors

The parasitic source and drain resistances of a high-electron-mobility transistor were analyzed in terms of a two layer transmission line model. The analysis showed that a highly conductive cap layer can function as an extension of the alloyed contact provided that tunneling between the cap layer and the channel is significant. The tunneling between the cap layer and the channel was analyzed in terms of a thermionic-field emission model in which a one dimensional time-dependent WKB transmission probability for the barrier was considered as well as Maxwell-Boltzman statistics for the tunneling carrier distribution. The GaAs cap, GaAlAs layer and 2-DEG channel can then be treated as a distributed resistance element with a characteristic coupling length. A reduction of the parasitic resistance can be obtained for a device structure with a short characteristic coupling length even if there exists an ideal alloyed contact to the 2-DEG channel. A multilayer cap consisting of an undoped GaAs layer inserted between the n-type GaAs and n-type GaAlAs is also proposed to reduce the barrier height for tunneling between the cap layer and the channel. The multilayer cap structure is predicted to appreciably reduce the parasitic resistance at room temperature and still be effective at 77 K.