Statistics of soft and hard breakdown in thin SiO2 gate oxides

Assuming that there are circuit applications which can tolerate one or several soft breakdown events before failure, we study the implications of soft/hard breakdown prevalence ratios on the device failure statistics. Our results demonstrate that these two breakdown modes are triggered by the same type of defect-related path, showing identical statistics if considered as independent breakdown mechanisms. An energy dissipation model for the breakdown current runaway transient is presented as a possible way to model soft and hard breakdown prevalence ratios as a function of stress conditions and sample characteristics.     

Low voltage stress induced leakage current and time to breakdown in ultra-thin (1.2–2.3 nm) oxides

Ultra-thin gate-oxide reliability is an essential factor in CMOS technologies. The low voltage gate current in ultra-thin oxide of metal–oxide–semiconductor devices is very sensitive to electrical stresses. It can be used as a reliability monitor when the oxide thickness becomes too small for traditional electrical measurements. In this paper, the low voltage stress induced leakage current (LVSILC) for various oxide thicknesses ranging from 1.2 to 2.3 nm is investigated during constant voltage stress (CVS). From the LVSILC measurements, we shown that time to breakdown can be deduced as a function of the stress voltage. We also study the effect of elevated stress temperature on the time to breakdown. We show that temperature dependence of the time to breakdown is non-Arrhenius and decreases in a drastic way with a slope of 0.036 decade/°C.     

Transients during pre-breakdown and hard breakdown of thin gate oxides in metal–SiO2–Si capacitors

Time–resolved electrical measurements show transient phenomena occurring during degradation and intrinsic dielectric breakdown of gate oxide layers under constant voltage Fowler–Nordheim stress. We have studied such transients in metal/oxide/semiconductor (MOS) capacitors with an n⁺ poly-crystalline Si/SiO₂/n-type Si stack and with oxide thickness between 35 and 5.6 nm. The data adds new information concerning the intrinsic breakdown mechanism and these are shown and discussed together with the adopted measurement techniques.     

Monitoring the degradation that causes the breakdown of ultrathin(<5 nm) SiO2 gate oxides

The degradation of ultrathin oxides subjected to constant-current stresses is analyzed using two independent procedures. First, the injected charge to breakdown is estimated from the stress-induced leakage current (SILC) evolution during the stress. Second, the degradation that leads to the breakdown is directly measured using a two-step stress test. The evolution of the SILC during constant-current stresses proceeds at a rate that decreases with time. Moreover, under low current density stress conditions the normalized SILC at breakdown is no longer constant. However, our two-step test methodology shows that the degradation of the oxide evolves roughly linearly until the breakdown. These apparently contradictory results can be reconciled assuming that the degradation at breakdown is independent of the stress conditions and using the initial SILC generation rate to calculate the charge-to-breakdown by linear extrapolation. The implications for the use of SILC data as a degradation monitor are discussed     

Thermal Ta2O5––alternative to SiO2 for storage capacitor application

Tantalum pentoxide thin layers (10–100 nm) obtained by thermal oxidation of rf sputtered Ta films on Si have been investigated with respect of their dielectric, structural and electric properties. It is established that stoichiometric Ta₂O₅ detected at the surface of the layers is reduced to tantalum suboxides in their depth. The oxide parameters are discussed in terms of a presence of an unavoidable ultrathin SiO₂ between Si and Ta₂O₅ and bond defects in both the oxide and the interface transition region. Conditions which guarantee obtaining high quality tantalum oxide with a dielectric constant of 32–35 and a leakage current less than 10⁻⁷–10⁻⁸ A/cm² at 1.5 V (SiO₂ equivalent thickness of 2.5–3 nm) are established. These specifications make the layers obtained suitable alternative to SiO₂ for high density DRAMs application.     

Characterization of the hot-electron-induced degradation in thin SiO2 gate oxides

With decreasing oxide thickness, some of the established methods to characterize oxide degradation become inapplicable because of limited sensitivity and because of direct tunneling which gives rise to large leakage currents through the oxide. However, new techniques are emerging which could not previously be used on thicker oxides, such as stress-induced leakage current measurements, current noise measurements, hot-electron emission microscopy, ballistic electron emission microscopy and hot-carrier luminescence. Some of these techniques provide unprecedented information on the local current densities with high spatial resolution and can be used to study inhomogeneous degradation in thin oxides at low voltages where homogeneous hot-carrier degradation becomes energetically unfavorable. In Si/SiO₂/poly-Si structures, three different, homogeneous, hot-electron induced degradation processes have been identified, with threshold voltages at 12 V, 7.5 V and about 4 V. These are the generation of holes by impact ionization in the oxide, the injection of holes from the anode, and the release of hydrogen mostly from near the anode, respectively. The released hydrogen is very reactive and is responsible for the generation of many stress-induced defects. The existence of energy thresholds for homogeneous defect generation may limit the use of voltage acceleration for reliability evaluations.     

A new empirical extrapolation method for time-dependent dielectric breakdown reliability projections of thin SiO2 and nitride–oxide dielectrics

The results of an investigation of time-dependent dielectric breakdown (TDDB) of thin gate oxide and nitride–oxide (N–O) films are presented for a wide range of fields and temperatures. It was found that TDDB of both gate oxide and N–O films followed a power-law dependence of mean value of average leakage current (I_avg). An empirical extrapolation model using average leakage current as a major parameter was proposed based on experimental results. This proposed lifetime model has been successful to predict dielectric reliability. It could continuously fit the entire breakdown data from both wafer level and module level stress. The extrapolation from wafer level data to module data was excellent. The power of current versus TDDB showed exponential dependence on oxide thickness. This proposed TDDB projection methodology also worked for N–O films with an abrupt current increase in the I–V curve at a certain voltage well below the breakdown voltage, while the conventional models clearly failed to fit all data from this region. The observation of TDDB dependence of the current may open a new window for oxide lifetime projections and provide some insights into the nature of oxide breakdown and its implications for reliability studies.     

Low electric field breakdown of thin SiO2 films understatic and dynamic stress

A comprehensive study of Time-Dependent Dielectric Breakdown (TDDB) of 6.5-, 9-, 15-, and 22-nm SiO₂ films under dc and pulsed bias has been conducted over a wide range of electric fields and temperatures. Very high temperatures were used at the wafer level to accelerate breakdown so tests could be conducted at electric fields as low as 4.5 MV/cm. New observations are reported for TDDB that suggest a consistent electric field and temperature dependence for intrinsic breakdown and a changing breakdown mechanism as a function of electric field. The results show that the logarithm of the median-test-time-to failure, log (t₅₀), is described by a linear electric field dependence with a field acceleration parameter that is not dependent on temperature. It has a value of approximately 1 decade/MV/cm for the range of oxide thicknesses studied and shows a slight decreasing trend with decreasing oxide thickness. The thermal activation E_a ranged between 0.7 and 0.95 eV for electric fields below 9.0 MV/cm for all oxide thicknesses. TDDB tests conducted under pulsed bias indicate that increased dielectric lifetime is observed under unipolar and bipolar pulsed stress conditions, but diminishes as the stress electric field and oxide thickness are reduced. This observation provides new evidence that low electric field aging and breakdown is not dominated by charge generation and trapping     

A detailed study of current–voltage characteristics in Au/SiO2/n-GaAs in wide temperature range

The forward and reverse-bias current–voltage (I–V) characteristics of Au/SiO₂/n-GaAs (MIS) type Schottky barrier diode (SBDs) have been investigated in the wide temperature range of 80–400 K. The zero-bias barrier height (_Bo) and ideality factor (n) assuming the thermionic emission (TE) mechanism show strong temperature dependence. While n decreases, _Bo increases with increasing temperature. Such temperature dependence of _Bo is an obvious disagreement with the reported negative temperature coefficient (α_temp) of barrier height. Therefore, we have reported a modification which includes the n and electron-tunneling parameter (αχ^1/2δ) in the expression of reverse-saturation current (I₀). After this modification, the value of α_temp obtained as −4 × 10⁻⁴ eV/K which is very close to α_temp of GaAs band-gap (−5.4 × 10⁻⁴ eV/K). Richardson plot of the ln(I₀/T²) versus 1/T has two linear region; the first region is (200–400 K) and the second region (80–150 K). The values of the activation energy (E_a) and Richardson constant were obtained from this plot and the values of E_a and Richardson constants (A^*) are much lower than the known values. These behaviors of the Au/SiO₂/n-GaAs (MIS) type (SBDs) have been interpreted by the assumption of a double-Gaussian distribution of barrier heights (BHs) at the metal–semiconductor interface giving a mean BHs () of 1.20 and 0.68 eV and standard deviation (σ_s) of 0.1503 and 0.0755 V, respectively. Thus the modified ln versus q/kT for two different temperature ranges (200–400 K and 80–150 K) plot then gives mean barrier heights and A^*, 1.18 and 0.66 eV and 7.08 and 3.81 A/cm² K², respectively. This value of the A^* 7.08 A/cm² K² is very close to the theoretical value of 8.16 A/cm² K² for n-type GaAs. Hence, all these behaviours of the forward-bias I–V characteristics of the Au/SiO₂/n-GaAs (MIS) type SBDs can be successfully explained on the basis of a TE mechanism with a double-Gaussian distribution of the BHs.     

The self-formatting barrier characteristics of Cu–Mg/SiO2 and Cu–Ru/SiO2 films for Cu interconnects

To substitute or to supplement diffusion barrier as reducing lateral dimension of interconnects, the alloying Mg and Ru to Cu was investigated as a self-formatting barrier in terms of their resistivity, adhesion, and barrier characteristics After annealing at 400 °C for 30 min, the resistivities of the Cu–0.7 at%Mg alloy and Cu–2.2 at%Ru alloy were 2.0 μΩ cm and 2.5 μΩ cm, respectively, which are comparable to that of Cu films. The adhesion was investigated by means of a sandwiched structure using the four point bending test. The interfacial debonding energy, which represents the adhesion, of Cu–Mg/SiO₂ was over 5.0 J/m², while those of the Cu–Ru/SiO₂ and Cu/SiO₂ interfaces were 2.2 J/m² and 2.4 J/m², respectively. The barrier characteristics of the alloy films were also investigated by the time-dependent dielectric breakdown test, using a metal–oxide–semiconductor structure, under bias-temperature stress. It was shown that the alloying of Mg made the lifetime seven times longer, as opposed to the alloying of Ru which made it shorter.     

A new soft breakdown model for thin thermal SiO2 filmsunder constant current stress

Soft breakdown properties of thin gate oxide films are investigated using a constant current stress measurement. The soft breakdown can be classified into two different modes from the current conduction characteristics of post breakdown oxides: one of the modes shows a telegraph switching pattern and the other random noise. The generation probabilities of two soft breakdown modes and hard breakdown strongly depend on the stress current. Time-to-breakdown is well characterized by a universal function of stress conditions regardless of the breakdown modes. These experimental findings imply that all types of breakdown originate from the same precursor and the magnitude of the following local heating due to the transient current in a conductive micro spot determines the charge conduction properties after a breakdown event     

Photo-CVD process for ultra thin SiO2 films

In this paper we first report the use of very low deposition rate photo-induced chemical vapor deposition process, (below 0.05 nm/min). This photo-CVD process is adequate to grow very thin and ultra thin layers of SiO₂. Details on the design of the reaction chamber, reactive gases and process parameters to obtain the desired deposition regime are presented. Dependence of deposition rate on pressure in the chamber and gas flow ratio is discussed. Deposited layers were characterized using I–V and C–V techniques.     

Trapped charge distributions in thin (10 nm) SiO2 filmssubjected to static and dynamic stresses

Thin (10 nm) gate oxide MOS capacitors have been subjected to static and dynamic stress conditions. The evolution of the trapped charge distributions (characterized by average density and centroid) has been measured as a function of the stress time. The evolution of the average charge density for DC stresses shows that both polarities have identical trap generation rates and a constant average density of traps at breakdown. However, the final density of traps is much smaller for injection from the gate, so that the time-to-breakdown is also much shorter for this stress polarity. The evolution of the centroid shows that traps are always mainly generated near the cathodic interface. Unipolar dynamic stresses give results which are qualitatively very similar to those obtained under DC conditions and without a relevant frequency dependence. In contrast, bipolar stress experiments show significant qualitative differences, the frequency dependence being very important. In general, the trap generation and trapping rates are reduced in comparison to the DC and unipolar cases, this reduction being more important at high frequencies. In addition, the average density of trapped electrons at the breakdown is larger than that obtained in DC experiments. Both observations explain the tremendous increase in the mean-time-to-breakdown obtained under high-frequency stress conditions. The presented results are qualitatively explained in terms of microscopic degradation models     

Pre-breakdown noise in electrically stressed thin SiO2 layers of MOS devices observed with C-AFM

A conductive atomic force microscope (C-AFM) has been used to analyse the degradation stage (before breakdown, BD) of ultrathin (<6 nm) films of SiO₂ at a nanometer scale. Working on bare gate oxides, the conductive tip of the C-AFM allows the electrical characterization of nanometric areas. Due to the extremely small size of the analysed areas, several features, which can be masked by the current that flows through the overall test structure during standard electrical tests, are observed. In particular, switching between different conduction states and sudden changes of conductivity have been measured during ramped voltage tests, which have been related to the trapping and detrapping of single electronic charges in the defects generated during the electrical stress. This phenomenon, which has been observed during constant voltage stresses in the form of random telegraph signals, has been associated to the pre-breakdown noise measured in poly-gated structures. The C-AFM has also allowed to directly measure the I–V characteristics of the fluctuating spot.     

Atomic-layer-deposited silicon-nitride/SiO2 stack––a highly potential gate dielectrics for advanced CMOS technology

An extremely thin (2 monolayers) silicon nitride layer has been deposited on thermally grown SiO₂ by an atomic-layer-deposition (ALD) technique and used as gate dielectrics in metal–oxide–semiconductor (MOS) devices. The stack dielectrics having equivalent oxide thickness (T_eq=2.2 nm) efficiently reduce the boron diffusion from p⁺ poly-Si gate without the pile up of nitrogen atoms at the SiO₂/Si interface. The ALD silicon nitride is thermally stable and has very flat surface on SiO₂ especially in the thin (<0.5 nm) thickness region.An improvement has been obtained in the reliability of the ALD silicon-nitride/SiO₂ stack gate dielectrics compared with those of conventional SiO₂ dielectrics of identical thickness. An interesting feature of soft breakdown free phenomena has been observed only in the proposed stack gate dielectrics. Possible breakdown mechanisms are discussed and a model has been proposed based on the concept of localized physical damages which induce the formation of conductive filaments near both the poly-Si/SiO₂ and SiO₂/Si-substrate interfaces for the SiO₂ gate dielectrics and only near the SiO₂/Si-substrate interface for the stack gate dielectrics.Employing annealing in NH₃ at a moderate temperature of 550 °C after the ALD of silicon nitride on SiO₂, further reliability improvement has been achieved, which exhibits low bulk trap density and low trap generation rate in comparison with the stack dielectrics without NH₃ annealing.Because of the excellent thickness controllability and good electronic properties, the ALD silicon nitride on a thin gate oxide will fulfill the severe requirements for the ultrathin stack gate dielectrics for sub-0.1 μm complementary MOS (CMOS) transistors.     

超薄SiO2/HfO2双层栅介质的时变击穿特性和击穿机制的研究

The characteristics of TDDB （time-dependent dielectric breakdown） and SILC （stress-induced leakage current） for an ultra-thin SiO2/HfO2 gate dielectric stack are studied. The EOT （equivalent-oxide-thickness） of the gate stack （Si/SiO2/HfOz/TiN/TiA1/TiN/W） is 0.91 am. The field acceleration factor extracted in TDDB experi- ments is 1.59 s.cm/MV, and the maximum voltage is 1.06 V when the devices operate at 125 ℃ for ten years. A detailed study on the defect generation mechanism induced by SILC is presented to deeply understand the break- down behavior. The trap energy levels can be calculated by the SILC peaks： one S1LC peak is most likely to be caused by the neutral oxygen vacancy in the HfO2 bulk layer at 0.51 eV below the Si conduction band minimum; another SILC peak is induced by the interface traps, which are aligned with the silicon conduction band edge. Fur- thermore, the great difference between the two SILC peaks demonstrates that the degeneration of the high-k layer dominates the breakdown behavior of the extremely thin gate dielectric.     

Hole injection SiO2 breakdown model for very low voltagelifetime extrapolation

In this paper, we present a model for silicon dioxide breakdown characterization, valid for a thickness range between 25 Å and 130 Å, which provides a method for predicting dielectric lifetime for reduced power supply voltages and aggressively scaled oxide thicknesses. This model, based on hole injection from the anode, accurately predicts Q_BD and t_BD behavior including a fluence in excess of 10⁷ C/cm² at an oxide voltage of 2.4 V for a 25 Å oxide. Moreover, this model is a refinement of and fully complementary with the well known 1/E model, while offering the ability to predict oxide reliability for low voltages     

Charge storage peculiarities in poly-Si–SiO2–Si memory devices with Si nanocrystals rich SiO2

The paper focuses on the study of charge trapping processes in non-volatile memory metal-oxide-silicon (MOS) structures with Si nanocrystal floating gate formed by Si ion implantation. Careful electrical studies of the MOS structures based on the analysis of the capacitance–voltage (C–V) characteristics during pulse charge injection in the oxide enabled the distinguishing of the electron emission from the nanoclusters and the charge trapping in structural defects of the dioxide matrix. The trapping model is discussed.     

Reactor characterization for a process to etchSi3N4 formed on thin SiO2

A plasma etching process for patterning LPCVD (low-pressure chemical vapor deposition) Si₃N₄ which has been formed on thin thermally grown SiO₂ has been developed and characterized with an Applied Materials 8110 batch system using 100-mm-diameter silicon wafers. To fulfill the primary process objectives of minimal critical dimension (CD) loss (~0.08 μm), vertical profiles after etch, retention of some of the underlying thermal SiO₂, and batch etch uniformity, the reactor has been characterized by evaluating the effects of variation of reactor pressure (15 to 65 mTorr), O₂ concentration by flow rate (30 to 70%) of an O₂/CHF₂ mixture, and DC bias voltage (-200 to -550 V). Analysis of the resulting etch rate, etch uniformity, dimensional, and profile data suggests that satisfactory processing may be achieved at low reactor pressure (~25 mTorr), 50-60% O₂ by flow rate in O₂/CHF₃, and low DC bias (-200 to -250 V)     

SiON and SiO2/HfSiON gate oxides time dependent dielectric breakdown measurements at nanoscale in ultra high vacuum

Time dependent dielectric breakdown (TDDB) measurements on a nano-scale using an AFM tip under ultra high vacuum as upper electrode are systematically compared to device measurements in this paper. Both studies were performed on the same SiON or SiO₂/HfSiON gate oxides. The shape factor of the TDDB distribution and the acceleration factor are compared at both scales.