Interface effect in pentacene field-effect transistors from high energy proton beam irradiation

We report the effect of irradiation using 10 MeV high energy proton beams on pentacene organic field-effect transistors (OFETs). The electrical characteristics of the pentacene OFETs were measured before and after proton beam irradiation with fluence (dose) conditions of 10¹², 10¹³, and 10¹⁴ cm⁻². After proton beam irradiation with fluences of 10¹² or 10¹³ cm⁻², the threshold voltage of the OFET devices shifted to the positive gate voltage direction with an increase in the current level and mobility. In contrast, for a high proton beam fluence condition of 10¹⁴ cm⁻², the threshold voltage shifted to the negative gate voltage direction with a decrease in the current level and mobility. It is evident from the electrical characteristics of the pentacene OFETs treated with a self-assembled monolayer that these experimental observations can be attributed to the trapped charges in the dielectric layer and pentacene/SiO₂ interface. Our study will enhance the understanding of the influence of high energy particles on organic field-effect transistors.     

电子束辐照下的石墨烯上的原子层沉积Al2O3介质层

为了研究石墨烯与高k介质的结合,使用原子层沉积氧化铝在石墨衬底上。沉积前使用电子束辐照,观测到了氧化铝明显改善的形貌。归因于电子束辐照过程中的石墨层的无定形变化过程。     

Physical and electrical characterization of polysilicon vs. TiN gate electrodes for HfO2 transistors

The effects of pre-deposition substrate treatments and gate electrode materials on the properties and performance of high-k gate dielectric transistors were investigated. The performance of O₃ vs. HF-last/NH₃ pre-deposition treatments followed by either polysilicon (poly-Si) or TiN gate electrodes was systematically studied in devices consisting of HfO₂ gate dielectric produced by atomic layer deposition (ALD). High-angle annular dark field scanning transmission electron microscopy (HAADF-STEM) using X-ray spectra and Electron Energy Loss Spectra (EELS) were used to produce elemental profiles of nitrogen, oxygen, silicon, titanium, and hafnium to provide interfacial chemical information and to convey their changes in concentration across these high-k transistor gate-stacks of 1.0–1.8 nm equivalent oxide thickness (EOT). For the TiN electrode case, EELS spectra illustrate interfacial elemental overlap on a scale comparable to the HfO₂ microroughness. For the poly-Si electrode, an amorphous reaction region exists at the HfO₂/poly-Si interface. Using fast transient single pulse (SP) electrical measurements, electron trapping was found to be greater with poly-Si electrode devices, as compared to TiN. This may be rationalized as a result of a higher density of trap centers induced by the high-k/poly-Si material interactions and may be related to increased physical thickness of the dielectric film, as illustrated by HAADF-STEM images, and may also derive from the approximately 0.5 nm larger EOT associated with polysilicon electrodes on otherwise identical gate stacks.     

Role of Gate Oxide in AlGaN/GaN High-Electron-Mobility Transistor pH Sensors

We report on a comparison of different gate oxides for AlGaN/GaN high-electron-mobility transistor (HEMT) pH sensors. The HEMTs show a linear increase in drain-source current as the pH of the electrolyte solutions introduced to the gate region is decreased. Three different gate oxides were examined, namely the native oxide on the AlGaN surface, a UV-ozone-induced oxide and an Sc₂O₃ gate deposited by molecular beam epitaxy. The Sc₂O₃ produced superior results in terms of resolution in measuring small changes in pH. The devices with Sc₂O₃ in the gate region exhibited a linear change in current between pH 3 and 10 of 37 μA/pH with a resolution of <0.1 pH over the entire pH range. In contrast, the native oxide devices showed a larger change in current, ∼70 μA/pH, but with a degraded resolution of ∼0.4 pH. Results for the UV-ozone oxide were intermediate in resolution, 0.2 pH. These HEMTs have promise for detecting pH changes in biological samples and can be readily integrated into a standard package for wireless data transmission.     

Evolution of oxide charge trapping under bias temperature stressing

Transient oxide-charge trapping and detrapping, commonly regarded as a parasitic effect in the interpretation of dynamic bias-temperature stress (BTS) data, may play an important role on the long term reliability of the gate oxide as revealed by recent studies on the SiON and HfO₂ gate dielectrics. Specifically, it is found that transient charge trapping (one which relaxes upon removal of the applied electrical stress) is transformed into more permanent trapped charge when the applied electrical cum thermal stress exceeds a certain threshold. Below the threshold, cyclical transient charge trapping and detrapping behavior is observed. The observations imply that the oxide structure may be modified by the applied stress, making it susceptible to permanent defect generation. In addition, it is found that when the transformation of hole trapping occurs under negative-bias temperature stress, a correlated increase of the gate current is always observed, which points to the transformation process being the origin for bulk oxide trap generation. However, when the transformation of electron trapping occurs under positive-bias temperature stress, an increase of the gate current is not always observed. From ab initio simulation, we show that an intrinsic oxide defect – the oxygen vacancy-interstitial (V_O − O_i) – could consistently explain the experimental observations. An interesting feature of the V_O − O_i defect is that it can exists in various metastable configurations with the interstitial oxygen O_i in different positions around the vacancy V_O, corresponding to different trap energy states in the oxide bandgap. This characteristic is able to account for the BTS induced generation of deep-level trapped charges as well as transformation of transient (or shallow) to permanent (or deep) charge trapping.     

Gate metal interdiffusion induced degradation in space-qualified GaAs PHEMTs

While gate metal sinking has been traditionally identified as the primary degradation mechanism in GaAs pseudomorphic high electron mobility transistors (PHEMTs), there is no physical demonstration of gate metal interdiffusion or understanding of the gate metal interdiffusion effect on reliability performance. This paper reviews our results on gate metal interdiffusion in 0.15-μm GaAs PHEMTs subjected to accelerated temperature lifetest. We used the techniques of focused ion beam (FIB), high-resolution energy-dispersive analysis with X-ray (EDX), and scanning transmission electron microscope (STEM). These results substantiate the observed d.c. and RF parametric evolution with respect to reverse gate leakage current (I_g), ideality factor, Schottky barrier height (Φ_BN), transconductance (G_m), I_dss, pinchoff voltage (V_po), S21, and provide insights into the effect of gate metal interdiffusion on reliability performance. The comprehensive understanding of gate metal interdiffusion induced degradation is essential for GaAs PHEMTs due to their widespread military/space applications.     

Modelling negative bias temperature instabilities in advanced p-MOSFETs

The decrease of the threshold voltage V_th of p-channel metal-oxide semiconductor field effect transistors (p-MOSFET) with ultrathin gate dielectric layers under negative bias temperature stress is studied. A degradation model is developed, that accounts for the generation of Si₃Si^√ (P_b0) centers and bulk oxide defects, induced by the tunnelling of electrons or holes through the gate dielectric layer during the electrical stress. The model predicts that V_th shifts are mainly due to the tunnelling of holes at low gate bias |V_G|, typically below 1.5 V, while electrons are mainly responsible for these shifts at higher |V_G|. Consequently, device lifetime at operating voltage, based on V_th shifts, should not be extrapolated from measurements performed at high gate bias. The impact of nitrogen incorporated at the Si/dielectric interface on V_th shifts is next investigated. The acceleration of device degradation when the amount of nitrogen increases is attributed to the increase in local interfacial strain, induced by the increase in bonding constraints, as well as to the increase in the density of Si---N---Si strained bonds, that act as trapping centers of hydrogen species released during the electrical stress. Finally, V_th shifts in p-MOSFET with Hf_ySiO_x gate layers and SiO₂/Hf_ySiO_x gate stacks are simulated, taking into account the generation of P_b0 centers induced by the injection of electrons through the structure. It is found that the transistor lifetime, based on threshold voltage shifts, is improved in SiO₂/Hf_ySiO_x gate stacks as compared to single Hf_ySiO_x layers. This finding is attributed to the beneficial presence of the SiO₂ interfacial layer, which allows the relaxation of strain at the Si/dielectric interface.     

In Situ Study of Nanostructure and Electrical Resistance of Nanocluster Films Irradiated with Ion Beams

An in situ study is reported on the structural evolution in nanocluster films under He⁺ ion irradiation using an advanced helium ion microscope. The films consist of loosely interconnected nanoclusters of magnetite or iron‐magnetite (Fe‐Fe₃O₄) core‐shells. The nanostructure is observed to undergo dramatic changes under ion‐beam irradiation, featuring grain growth, phase transition, particle aggregation, and formation of nanowire‐like network and nanopores. Studies based on ion irradiation, thermal annealing and electron irradiation have indicated that the major structural evolution is activated by elastic nuclear collisions, while both electronic and thermal processes can play a significant role once the evolution starts. The electrical resistance of the Fe‐Fe₃O₄ films measured in situ exhibits a super‐exponential decay with dose. The behavior suggests that the nanocluster films possess an intrinsic merit for development of an advanced online monitor for fast neutron radiation with both high detection sensitivity and long‐term applicability, which can enhance safety measures in many nuclear operations.     

Pseudomorphic AlGaAs/InGaAs/GaAs High Electron Mobility Transistors with Super Low Noise Performances of 0.41 dB at 18 GHz

Fully passivated low noise AlGaAs/InGaAs/GaAs pseudomorphic (PM) HEMT with wide head T-shaped gates were fabricated by dose split electron beam lithography (DSL). The dimensions of gate head and footprint were optimized by controlling the splitted pattern size, dose, and spaces of each pattern. We obtained stable T-shaped gate of 0.15 μm gate length with 1.35 μm-wide head. The maximum extrinsic transconductance was 560 mS/mm. The minimum noise figure measured at 18 GHz at V_ds = 2 V and I_ds = 17 mA was 0.41 dB with associated gain of 8.19 dB. At 12 GHz, the minimum noise figure and an associated gain were 0.26 and 10.25 dB, respectively. These noise figures are the lowest values ever reported for GaAs-based HEMTs. These results are attributed to the extremely low gate resistance of wide head T-shaped gate having a ratio of the head to footprint dimensions larger than 9.     

调整VO2薄膜相变特性和TCR的制备及辐照方法

采用不同的真空还原时间、真空退火温度和衬底制备出了VO2薄膜,并对制备出的薄膜进行电子辐照.通过测试辐照前后的VO2薄膜相变电学性能及低温半导体相电阻温度系数(TCR),表明不同的制备工艺和不同注量的电子辐照可明显改变VO2薄膜相变过程中电学性能,提高薄膜的电阻温度系数.对影响VO2热致相变薄膜电学性能及电阻温度系数的因素进行了讨论.     

On-state and off-state stress-induced degradation in unhydrogenated solid phase crystallized polysilicon thin film transistors

The effects of DC bias gate and drain on-state and off-state stresses on unhydrogenated solid phase crystallized polysilicon thin film transistors were investigated. The observed, under gate bias stress, threshold voltage turnaround from an initial negative shift due to hole trapping to positive shift with logarithmic time dependence attributed to electron trapping was suppressed when a drain bias was added for a combined gate–drain on-state stress; this suppression was more effective for larger gate bias. The subthreshold swing, the midgap trap state density and the transconductance exhibited logarithmic degradation, in line with the positive V_th shift. The stressing time needed for V_th turnaround decreased, indicating increase of electron trapping, and the midgap trap state density increased in correlation with increasing stressing current I_DS as stressing V_DS increased, for a given on-state stressing V_GS. Off-state gate–drain stressing resulted in logarithmic positive V_th shift, after a small initial negative shift, and in reduction of the leakage current due to stress-induced shielding of the gate field. An applied inverse stress resulted in less severe V_th degradation due to stress-induced effects being more concentrated near the source rather than the drain in that case.     

半开态直流应力作用下AlGaN/GaN高电子迁移率晶体管的失效机制分析

本文研究了半开态直流应力条件下,AlGaN/GaN高电子迁移率晶体管的退化机制。应力实验后,器件的阈值电压电压正漂,栅漏串联电阻增大。利用数据拟合发现,沟道电流的退化量与阈值电压及栅漏串联电阻的变化量之间有密切的关系。分析表明,阈值电压的退化是引起饱和区沟道电流下降的主要因素,对于线性区电流,在应力开始的初始阶段,栅漏串联电阻的增大导致线性区电流的退化,随后沟道电流退化主要由阈值电压的退化引起。分析表明,在半开态应力作用下,栅泄露电流及热电子效应使得电子进入AlGaN层,被缺陷俘获,进而导致沟道电流退化。其中反向栅泄露电流中的电子被栅电极下AlGaN层内的缺陷俘获,导致阈值电压正漂;而热电子效应则使得栅漏串联区电阻增大。     

Hole trapping in E-beam irradiated SiO2 films

Low energy (25 kV) electron beam irradiation of MOS capacitors is shown to produce neutral hole traps in thin ‘radiation hardened’ SiO₂ films. These traps are found in an uncharged state after irradiation and are populated by passing a small hole current, generated by avalanche breakdown of then-type silicon substrate, through the oxide. From the time dependence of the observed trapping, a capture cross-section between 1 × 10∼⁻¹³ and 1 × 10⁻¹⁴ cm² is deduced. The trap density is found to depend on the annealing conditions and incident electron beam dosage. The density of traps increases with incident electron beam exposure. Once introduced into the oxide by the radiation the traps can be removed by thermal anneals at temperatures above 500° C. Parallels between electron and hole trapping on these neutral centers are strong evidence for an amphoteric uncharged trap generated by ionizing radiation.     

Investigation of the Interfaces in Ni-FUSI/Hf-Based/Si and Ni-FUSI/SiO<Subscript>2</Subscript>/Si Stacks by Physical and Electrical Characterization Techniques

The combination of full Ni silicidation (Ni-FUSI) gate electrodes and hafnium-based high-k gate dielectrics is one of the most promising replacements for poly-Si/SiO₂/Si gate stacks for the future complementary metal–oxide–semiconductor (CMOS) sub-45-nm technology node. The key challenges to successfully adopting the Ni-FUSI/high-k dielectric/Si gate stack for advanced CMOS technology are mostly due to the interfacial properties. The origins of the electrical and physical characteristics of the Ni-FUSI/dielectric oxide interface and dielectric oxide/bulk interface were studied in detail. We found that Ni-FUSI undergoes a phase transformation during silicide formation, which depends more on annealing temperature than on the underlying gate dielectric material. The correlations of Ni–Si phase transformations with their electrical and physical changes were established by sheet resistance measurements, x-ray diffraction (XRD), atomic force microscopy (AFM), and x-ray photoelectron spectroscopy (XPS) analyses. The leakage current density–voltage (J–V) and capacitance–voltage (C–V) measurement techniques were employed to study the dielectric oxide/Si interface. The effects of the postdeposition annealing (PDA) treatment on the interface charges of dielectric oxides were studied. We found that the PDA can effectively reduce the trapping density and leakage current and eliminate hysteresis in the C–V curves. In addition, the changes in chemical bonding features at HfO₂/Si and HfSiO/Si interfaces due to PDA treatment were evaluated by XPS measurements. XPS analysis provides a better interpretation of the electrical outcomes. As a result, HfSiO films exhibited superior performance in terms of thermal stability and electrical characteristics.     

Impact on the back gate degradation in partially depleted SOI n-MOSFETs by 2-MeV electron irradiation

Degradation of the electrical performance in partially depleted SOI MOSFETs by 2-MeV electrons is presented. The degradation behavior of the 2^nd transconductance (g_mf) peak and its dependence on the back gate voltage is discussed taking into account the degradation of the back gate. The drain current in the subthreshold region is increased by irradiation. This is caused by the turn-on of the parasitic edge transistor. The 2^nd peak in the transconductance (g_mf) tends to decrease after irradiation, while less degradation is observed in the 1^st g_mf peak. The decrease of the 2^nd g_mf peak enhances by the application of a negative V_BG and the result can be explained by the degradation of the Si/buried oxide interface and the increase of the sidewall leakage, which gives rise to a lowering of the body potential.     

The electron irradiation effects on silicon gate dioxide used for power MOS devices

The work provides experimental results of high energy electron irradiation effects on silicon dioxide used for power MOS devices. A systematic increase of the threshold voltage has been observed in irradiated IGBT and VDMOS devices processed on Si1 0 0 and Si1 1 1, respectively. The threshold voltage shift has been interpreted as a result of the accumulated charge in the gate oxide. Single event gate rupture has been observed and attributed to the recoil ion interaction with the gate SiO₂. The result has been corroborated by reliability stress tests. After electron irradiation, an increase in breakdown voltage appeared on all devices which was attributed to a change in the surface impact ionisation coefficient. The change is most notable in devices processed on Si substrate with 1 1 1 orientation.     

Characteristics of metal-oxide-semiconductor (MOS) device with Er metal gate on SiO2 film

We have investigated the structural and electrical properties of metal-oxide-semiconductor (MOS) devices with Er metal gate on SiO₂ film. Rapid thermal annealing (RTA) process leads to the formation of a high-k Er-silicate gate dielectric. The in situ high-voltage electron microscopy (HVEM) results show that thermally driven Er diffusion is responsible for the decrease in equivalent oxide thickness (EOT) with an increase in annealing temperature. The effective work function (Φ_m,eff) of Er metal gate, extracted from the relations of EOT versus flat-band voltage (V_FB), is calculated to be ∼2.86 eV.     

Damage to insulated gate FETs by electron beam metrology and X-ray exposure

A comparison of the damage induced by X-rays and electron-beam radiation on IGFETs has been made. It is observed that the ratio of the threshold voltage shift due to fixed positive charge (ΔV _FPC) to the total threshold voltage shift (due to both fixed positive charge and neutral electron traps) does not show any dependence on the radiation dose in the case of an E-beam irradiation, and shows a negative slope for X-ray irradiated samples. This suggests that the amount of neutral electron traps (NETs) and fixed negative charge (FNC) produced by the ionizing radiation is higher in the case of X-ray irradiation and saturates at much higher doses compared to E-beam irradiation. A study of electron beam damage at various energies shows that E-beam energy of 7 keV does not damage the oxides at all whereas at lOkeV maximum damage is observed. For devices exposed to X-rays, the threshold voltage shift ratios due to the fixed positive charge for different gate oxide thicknesses (12·6nm-50·0nm) indicate a shift of the effective charge centre-id which also depends on the filling of neutral electron traps to form fixed negative charges that partially compensate the fixed positive charges. The threshold voltage shift ratios also indicate a shift in the charge centroid which is pronounced in the thinner oxides. A model for the change in effective centroid of charge and also its dose dependence for different oxide thicknesses has been suggested.     

Pressure‐Tunable Ambipolar Conduction and Hysteresis in Thin Palladium Diselenide Field Effect Transistors

Few‐layer palladium diselenide (PdSe₂) field effect transistors are studied under external stimuli such as electrical and optical fields, electron irradiation, and gas pressure. The ambipolar conduction and hysteresis are observed in the transfer curves of the as‐exfoliated and unprotected PdSe₂ material. The ambipolar conduction and its hysteretic behavior in the air and pure nitrogen environments are tuned. The prevailing p‐type transport observed at atmospheric pressure is reversibly turned into a dominant n‐type conduction by reducing the pressure, which can simultaneously suppress the hysteresis. The pressure control can be exploited to symmetrize and stabilize the transfer characteristics of the device as required in high‐performance logic circuits. The transistors are affected by trap states with characteristic times in the order of minutes. The channel conductance, dramatically reduced by the electron irradiation during scanning electron microscope imaging, is restored after an annealing of several minutes at room temperature. The work paves the way toward the exploitation of PdSe₂ in electronic devices by providing an experiment‐based and deep understanding of charge transport in PdSe₂ transistors subjected to electrical stress and other external agents.     

Defect centroid,patial distribution,and areal density in process-induced radiation-damaged IGFETs with gate insulators grown at 1000 and 800° C

IGFET devices were fabricated with “dry” gate oxides grown at 1000 and 800° C in the thickness range 5–50 nm. They were then exposed in an electrically unbiased state to Al K_α x-ray (1.49 keV) radiation to simulate process-induced ionizing radiation exposure. Gate oxide defects were measured before and after irradiation using optically assisted electron injection. Following irradiation and injection, the measured voltage shifts indicate that radiation-induced “extrinsic” defects are localized near, but not exactly at, the Si/SiO₂ interface.ΔV _T is found to be linear int _ox for oxide thicknesses where the top electrode resides above the defect region, and quadratic int _ox for thicknesses where the top electrode encroaches upon the defect region. For very thin oxides,ΔV _T is observed to approach zero. Application of a defect distribution model based on this behavior reveals that the oxidation temperature does not influence the distribution of radiation-induced defects, but does influence their concentration; with the 800° C oxides always containing more defects than the 1000° C oxides. A gate oxide thickness regime of less than 5-6 nm is identified in which radiation-induced threshold voltage shifts are observed to approach zero.