Failure mechanisms of Schottky gate contact degradation and deep traps creation in AlGaAs/InGaAs PM-HEMTs submitted to accelerated life tests

In this work we analyze degradation phenomena observed inpseudomorphic AlGaAs/InGaAs HEMTs with Al/Ti gate metallization, which have been submitted to accelerated tests at high drain-source voltage V_Ds and high power dissipation P_D. After these tests, we observe permanent degradation effects, consisting in electron trapping in the gate-drain access region, with consequent decrease in the longitudinal electric field and “breakdown walkout”, and in thermally-activated interdiffusion of the AI/Ti gate with decrease in the gate Schottky barrier height and increase in drain saturation current I_D. Rather than causing a degradation of therf characteristics of the device, these phenomena induce an increase in the associatedrf gain at 12 GHz, the other rf characteristics being almost unchanged. Overall, the most relevant failure mode observed is an increase of low-frequency transconductance.     

An investigation of electrical and structural properties of Ni-germanosilicided Schottky diode

Ni-germanosilicided Schottky barrier diode has been fabricated by annealing the deposited Ni film on strained-Si and characterized electrically in the temperature range of 125 K–300 K. The chemical phases and morphology of the germanosilicided films were studied by using scanning electron microscopy (SEM), cross-sectional transmission electron microscopy (TEM) and energy dispersive spectroscopy (EDS). The Schottky barrier height (_b), ideality factor (n) and interface state density (D_it) have been determined from the current–voltage (I–V) and capacitance–voltage (C–V) characteristics. The current–voltage characteristics have also been simulated using SEMICAD device simulator to model the Schottky junction. An interfacial layer and a series resistance were included in the diode model to achieve a better agreement with the experimental data. It has been found that the barrier height values extracted from the I–V and C–V characteristics are different, indicating the existence of an in-homogeneous Schottky interface. Results are also compared with bulk-Si Schottky diode processed in the same run. The variation of electrical properties between the strained- and bulk-Si Schottky diodes has been attributed to the presence of out-diffused Ge at the interface.     

Simulation of InGaAs subchannel DG-HEMTs for analogue/RF applications

The paper reports on the influence of a barrier thickness and gate length on the various device parameters of double gate high electron mobility transistors (DG-HEMTs). The DC and RF performance of the device have been studied by varying the barrier thickness from 1 to 5 nm and gate length from 10 to 150 nm, respectively. As the gate length is reduced below 50 nm regime, the barrier thickness plays an important role in device performance. Scaling the gate length leads to higher transconductance and high frequency operations with the expense of poor short channel effects. The authors claim that the 30-nm gate length, mole fractions tuned In_0.53Ga_0.47As/In_0.7Ga_0.3As/In_0.53Ga_0.47As subchannel DG-HEMT with optimised device structure of 2 nm In_0.48Al_0.52As barrier layer show a peak g_m of 3.09 mS/µm, V_T of 0.29 V, I_ON/I_OFF ratio of 2.24 × 10⁵, subthreshold slope ~73 mV/decade and drain induced barrier lowering ~68 mV/V with f_T and f_max of 776 and 905 GHz at V_ds = 0.5 V is achieved. These superior performances are achieved by using double-gate architecture with reduced gate to channel distance.     

Gate metal interdiffusion induced degradation in space-qualified GaAs PHEMTs

While gate metal sinking has been traditionally identified as the primary degradation mechanism in GaAs pseudomorphic high electron mobility transistors (PHEMTs), there is no physical demonstration of gate metal interdiffusion or understanding of the gate metal interdiffusion effect on reliability performance. This paper reviews our results on gate metal interdiffusion in 0.15-μm GaAs PHEMTs subjected to accelerated temperature lifetest. We used the techniques of focused ion beam (FIB), high-resolution energy-dispersive analysis with X-ray (EDX), and scanning transmission electron microscope (STEM). These results substantiate the observed d.c. and RF parametric evolution with respect to reverse gate leakage current (I_g), ideality factor, Schottky barrier height (Φ_BN), transconductance (G_m), I_dss, pinchoff voltage (V_po), S21, and provide insights into the effect of gate metal interdiffusion on reliability performance. The comprehensive understanding of gate metal interdiffusion induced degradation is essential for GaAs PHEMTs due to their widespread military/space applications.     

Cylindrical gate all around Schottky barrier MOSFET with insulated shallow extensions at source/drain for removal of ambipolarity: a novel approach

In this paper TCAD-based simulation of a novel insulated shallow extension (ISE) cylindrical gate all around (CGAA) Schottky barrier (SB) MOSFET has been reported,to eliminate the suicidal ambipolar behavior (bias-dependent OFF state leakage current) of conventional SB-CGAA MOSFET by blocking the metal-induced gap states as well as unwanted charge sharing between source/channel and drain/channel regions.This novel structure offers low barrier height at the source and offers high ON-state current.The ION/IoFF of ISE-CGAA-SB-MOS-FET increases by 1177 times and offers steeper subthreshold slope (～60 mV/decade).However a little reduction in peak cut off frequency is observed and to further improve the cut-off frequency dual metal gate architecture has been employed and a comparative assessment of single metal gate,dual metal gate,single metal gate with ISE,and dual metal gate with ISE has been presented.The improved performance of Schottky barrier CGAA MOSFET by the incorporation of ISE makes it an attractive candidate for CMOS digital circuit design.The numerical simulation is performed using the ATLAS-3D device simulator.     

Modeling and simulation of enhancement mode p-GaN Gate AlGaN/GaN HEMT for RF circuit switch applications

An enhancement mode p-GaN gate AlGaN/GaN HEMT is proposed and a physics based virtual source charge model with Landauer approach for electron transport has been developed using Verilog-A and simulated using Cadence Spectre, in order to predict device characteristics such as threshold voltage, drain current and gate capacitance. The drain current model incorporates important physical effects such as velocity saturation, short channel effects like DIBL (drain induced barrier lowering), channel length modulation (CLM), and mobility degradation due to self-heating. The predicted I_d-V_ds, I_d-V_gs, and C-V characteristics show an excellent agreement with the experimental data for both drain current and capacitance which validate the model. The developed model was then utilized to design and simulate a single-pole single-throw (SPST) RF switch.     

Characterization of current-voltage (I-V) and capacitance-voltage-frequency (C-V-f) features of Al/SiO2/p-Si (MIS) Schottky diodes

The current-voltage (I-V) characteristics of metal-insulator-semiconductor Al/SiO₂/p-Si (MIS) Schottky diodes were measured at room temperature (300 K). In addition, capacitance-voltage-frequency (C-V-f) characteristics are investigated by considering the interface states (N_ss) at frequency range 100 kHz to 1 MHz. The MIS Schottky diode having interfacial insulator layer thickness of 33 Å, calculated from the measurement of the insulator capacitance in the strong accumulation region. At each frequency, the measured capacitance decreases with increasing frequency due to a continuous distribution of the interface states. From the I-V characteristics of the MIS Schottky diode, ideality factor (n) and barrier height (Φ_b) values of 1.766 and 0.786 eV, respectively, were obtained from a forward bias I-V plot. In addition, the interface states distribution profile as a function of (E_ss − E_v) was extracted from the forward bias I-V measurements by taking into account the bias dependence of the effective barrier height (Φ_e) for the Schottky diode. The diode shows non-ideal I-V behaviour with ideality factor greater than unity. This behaviour is attributed to the interfacial insulator layer, the interface states and barrier inhomogeneity of the device. As expected, the C-V curves gave a barrier height value higher than those obtained from I-V measurements. This discrepancy is due to the different nature of the I-V and C-V measurement techniques.     

Passivation of Surface and Interface States in AlGaN/GaN HEMT Structures by Annealing

The Ni/AlGaN interfaces in AlGaN/GaN Schottky diodes were investigated to explore the physical origin of post-annealing effects using electron beam induced current (EBIC), current–voltage (I–V) characteristics, and X-ray photoelectron spectroscopy (XPS). The EBIC images of the annealed diodes showed that the post-annealing process reduces electrically active states at the Schottky metal/AlGaN interfaces, leading to improvement of diode performance, for example a decrease in reverse leakage current and an increase in Schottky barrier heights. Pulsed I–V characteristics indicate the Fermi level is up-shifted after annealing, resulting in a larger sheet carrier density at the AlGaN/GaN interface. Unintentional oxidation of the free AlGaN surface during the post-annealing process, revealed by XPS analysis, may prevent electron trapping near the drain-side of the gate edges. We suggest that the post-annealing process under an optimized conditions can be an effective way of passivating AlGaN/GaN heterojunction field-effect transistors.     

High thermal stability AlGaAs/InGaAs enhancement-mode pHEMT using palladium-gate technology

The dc, flicker noise, power, and temperature dependence of AlGaAs/InGaAs enhancement-mode pseudomorphic high electron mobility transistors (E-pHEMTs) were investigated using palladium (Pd)-gate technology. Although the conventional platinum (Pt)-buried gate has a high metal work function, which is beneficial for increasing the Schottky barrier height of the E-pHEMT, the high rate of intermixing of the Pt-GaAs interface owing to the effect of the continuous production of PtAs₂ on the device influenced the threshold voltage (V_th) and transconductance (g_m) at high temperatures or over the long-term operation. Variations in these parameters make Pt-gate E-pHEMT-related circuits impractical. Furthermore, a PtAs₂ interlayer caused a serious gate leakage current and unstable Schottky barrier height. This study presents the Pd-GaAs Schottky contact because Pd, an inert material with high work function of 5.12 eV. Stable Pd inhibited the less diffusion at high temperatures and simultaneously suppressed device flicker noise. The V_th of Pd/Ti/Au Schottky gate E-pHEMT was 0.183 V and this value shifted to 0.296 V after annealing at 200 °C. However, the V_th shifted from 0.084 to 0.231 V after annealing of the Pt/Ti/Au Schottky gate E-pHEMT because the Pt sunk into a deeper channel. The slope of the curve of power gain cutoff frequency (f_max) as a function of temperature was −5.76 × 10⁻² GHz/°C for a Pd/Ti/Au-gate E-pHEMT; it was −9.17 × 10⁻² GHz/°C for a Pt/Ti/Au-gate E-pHEMT. The slight variation in the dc and radio-frequency characteristics of the Pd/Ti/Au-gate E-pHEMT at temperatures from 0 to 100 °C revealed that the Pd-GaAs interface has great potential for high power transistors.     

Probing stress effects in HfO2 gate stacks with time dependent measurements

Effects of constant voltage stress (CVS) on gate stacks consisting of an ALD HfO₂ dielectric with various interfacial layers were studied with time dependent sensing measurements: DC I–V, pulse I–V, and charge pumping (CP) at different frequencies. The process of injected electron trapping/de-trapping on pre-existing defects in the bulk of the high-κ film was found to constitute the major contribution to the time dependence of the threshold voltage (V_t) shift during stress. The trap generation observed with the low frequency CP measurements is suggested to occur within the interfacial oxide layer or the interfacial layer/high-κ interface, with only a minor effect on V_t.     

Defect Analysis of Barrier Height Inhomogeneity in Titanium 4H-SiC Schottky Barrier Diodes

Over 350 4H-SiC Schottky barrier diodes (SBDs) of varying size are characterized using current–voltage (I–V) measurements, with some also measured as a function of temperature. Devices display either a characteristic single-barrier height or atypical dual-barrier heights. Device yields are shown to decrease as device area increases. Molten KOH etching is used to highlight defects for analysis by optical microscopy and atomic force microscopy. The I–V characteristics are compared against the defect density. A positive correlation between effective barrier height and effective electrically active area of the SBDs is found. No correlation is found between threading dislocations and ideality factor or barrier height.     

Performance analysis of 20 nm gate-length In0.2Al0.8N/GaN HEMT with Cu-gate having a remarkable high ION/IOFF ratio

Abstract： We propose a new structure of InxAll-xN/GaN high electron mobility transistor （HEMT） with gate length of 20 nm. The threshold voltage of this HEMT is achieved as -0.472 V. In this device the InA1N barrier layer is intentionally n-doped to boost the ION/IOFF ratio. The InAlN layer acts as donor barrier layer for this HEMT which exhibits an ION = 10-4.3 A and a very low IOFF = 10-14.4 A resulting in an ION/IoFF ratio of 1010.1. We compared our obtained results with the conventional InAlN/GaN HEMT device having undoped barrier and found that the proposed device has almost l0s times better ION/IOFF ratio. Further, the mobility analysis in GaN channel of this proposed HEMT structure along with DC analysis, C-V and conductance characteristics by using small-signal analysis are also presented in this paper. Moreover, the shifts in threshold voltage by DIBL effect and gate leakage current in the proposed HEMT are also discussed. InAlN was chosen as the most preferred barrier layer as a replacement of AlGaN for its excellent thermal conductivity and very good scalability.     

An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications

A fully analytical MOS transistor model dedicated to the design and analysis of low-voltage, low-current analog circuits is presented. All the large- and small-signal variables, namely the currents, the transconductances, the intrinsic capacitances, the non-quasi-static transadmittances and the thermal noise are continuous in all regions of operation, including weak inversion, moderate inversion, strong inversion, conduction and saturation. The same approach is used to derive all the equations of the model: the weak and strong inversion asymptotes are first derived, then the variables of interest are normalized and linked using an appropriate interpolation function. The model exploits the inherent symmetry of the device by referring all the voltages to the local substrate. It is shown that the inversion chargeQ _inv is controlled by the voltage differenceV _P – V_ch, whereV _ch is the channel voltage, defined as the difference between the quasi-Fermi potentials of the carriers. The pinch-off voltageV _P is defined as the particular value ofV _ch such that the inversion charge is zero for a given gate voltage. It depends only on the gate voltage and can be interpreted as the equivalent effect of the gate voltage referred to the channel. The various modes of operation of the transistor are then presented in terms of voltagesV _P – V_S andV _P – V_D. Using the charge sheet model with the assumption of constant doping in the channel, the drain currentI _D is derived and expressed as the difference between a forward componentI _F and a reverse componentI _R. Each of these is proportional to a function ofV _P – V_S, respectivelyV _P – V_D, through a specific currentI _S. This function is exponential in weak inversion and quadratic in strong inversion. The current in the moderate inversion region is then modelled by using an appropriate interpolation function resulting in a continuous expression valid from weak to strong inversion. A quasi-static small-signal model including the transconductances and the intrinsic capacitances is obtained from an accurate evaluation of the total charges stored on the gate and in the channel. The transconductances and the intrinsic capacitances are modelled in moderate inversion using the same interpolation function and without any additional parameters. This small-signal model is then extended to higher frequencies by replacing the transconductances by first order transadmittances obtained from a non-quasi-static calculation. All these transadmittances have the same characteristic time constant which depends on the bias condition in a continuous manner. To complete the model, a general expression for the thermal noise valid in all regions of operation is derived. This model has been successfully implemented in several computer simulation programs and has only 9 physical parameters, 3 fine tuning fitting coefficients and 2 additional temperature parameters.     

Physical identification of gate metal interdiffusion in GaAs PHEMTs

The Ti metal interdiffusion of Ti/Pt/Au gate metal stacks in 0.15-/spl mu/m GaAs PHEMTs subjected to high-temperature accelerated lifetest has been physically identified using scanning transmission electron microscopy. Further energy dispersive analysis with X-ray (EDX) analysis confirms the Ti diffusion into the AlGaAs Schottky barrier layer and the decrease of Schottky barrier height suggests the Ti-AlGaAs intermetallic formation, which is consistent with previous Rutherford backscattering spectroscopy/X-ray photoelectron spectroscopy studies. The Ti metal interdiffusion reduces the separation of the gate metal and InGaAs channel, thus leading to a slight Gm increase, positive shift in pinchoff voltage, and S21 increase during the preliminary portion of the lifetest. Accordingly, the Ti interdiffusion effect implies that the lifetime of GaAs PHEMTs subjected to high-temperature accelerated lifetest could be dependent upon the initial thickness of the Schottky layer underneath the gate metal.     

Analysis of contact effects in fully printed p-channel organic thin film transistors

Contact effects have been analyzed in fully printed p-channel OTFTs based on a pentacene derivative as organic semiconductor and with Au source–drain contacts. In these devices, contact effects lead to an apparent decrease of the field effect mobility with decreasing L and to a failure of the gradual channel approximation (GCA) in reproducing the output characteristics. Experimental data have been reproduced by two-dimensional numerical simulations that included a Schottky barrier (Φ_b = 0.46 eV) at both source and drain contacts and the effects of field-induced barrier lowering. The barrier lowering was found to be controlled by the Schottky effect for an electric field E < 10⁵ V/cm, while for higher electric fields we found a stronger barrier lowering presumably due to other field-enhanced mechanisms. The analysis of numerical simulation results showed that three different operating regimes of the device can be identified: (1) low |V_ds|, where the channel and the Schottky diodes at both source and drain behave as gate voltage dependent resistors and the partition between channel resistance and contact resistance depends upon the gate bias; (2) intermediate V_ds, where the device characteristics are dominated by the reverse biased diode at the source contact, and (3) high |V_ds|, where pinch-off of the channel occurs at the drain end and the transistor takes control of the current. We show that these three regimes are a general feature of the device characteristics when Schottky source and drain contacts are present, and therefore the same analysis could be extended to TFTs with different semiconductor active layers.     

Modelling negative bias temperature instabilities in advanced p-MOSFETs

The decrease of the threshold voltage V_th of p-channel metal-oxide semiconductor field effect transistors (p-MOSFET) with ultrathin gate dielectric layers under negative bias temperature stress is studied. A degradation model is developed, that accounts for the generation of Si₃Si^√ (P_b0) centers and bulk oxide defects, induced by the tunnelling of electrons or holes through the gate dielectric layer during the electrical stress. The model predicts that V_th shifts are mainly due to the tunnelling of holes at low gate bias |V_G|, typically below 1.5 V, while electrons are mainly responsible for these shifts at higher |V_G|. Consequently, device lifetime at operating voltage, based on V_th shifts, should not be extrapolated from measurements performed at high gate bias. The impact of nitrogen incorporated at the Si/dielectric interface on V_th shifts is next investigated. The acceleration of device degradation when the amount of nitrogen increases is attributed to the increase in local interfacial strain, induced by the increase in bonding constraints, as well as to the increase in the density of Si---N---Si strained bonds, that act as trapping centers of hydrogen species released during the electrical stress. Finally, V_th shifts in p-MOSFET with Hf_ySiO_x gate layers and SiO₂/Hf_ySiO_x gate stacks are simulated, taking into account the generation of P_b0 centers induced by the injection of electrons through the structure. It is found that the transistor lifetime, based on threshold voltage shifts, is improved in SiO₂/Hf_ySiO_x gate stacks as compared to single Hf_ySiO_x layers. This finding is attributed to the beneficial presence of the SiO₂ interfacial layer, which allows the relaxation of strain at the Si/dielectric interface.     

Effect of underlap and gate length on device performance of an AlInN/GaN underlap MOSFET

We investigate the performance of an 18 nm gate length AlInN/GaN heterostructure underlap double gate MOSFET, using 2D Sentaurus TCAD simulation. The device uses lattice-matched wideband Al_0.83In_0.17N and narrowband GaN layers, along with high-k Al₂O₃ as the gate dielectric. The device has an ultrathin body and is designed according to the ITRS specifications. The simulation is done using the hydrodynamic model and interface traps are also considered. Due to the large two-dimensional electron gas (2DEG) density and high velocity, the maximal drain current density achieved is very high. Extensive device simulation of the major device performance metrics such as drain induced barrier lowering (DIBL), subthreshold slope (SS), delay, threshold voltage (V_t), I_on/I_off ratio and energy delay product have been done for a wide range of gate and underlap lengths. Encouraging results for delay, I_on, DIBL and energy delay product are obtained. The results indicate that there is a need to optimize the I_off and SS values for specific logic design. The proposed AlInN/GaN heterostructure underlap DG MOSFET shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.     

Characterization by Internal Photoemission Spectroscopy of Single-Crystal CVD Diamond Schottky Barrier Diodes

Internal photoemission spectroscopy measurements have been performed to study the electrical characteristics of Schottky diodes on boron-doped single-crystalline chemical vapor deposited (SC-CVD) diamond. These measurements were compared with current–voltage (I–V) and current–temperature (I–T) measurements. Schottky contact barrier heights and ideality factors have been measured on Schottky contacts formed on four samples with Au, Ni, and Al contact metallizations. I–V and I–T measurements were performed in the temperature range from 300 K to 500 K. The internal photoemission method, which is less influenced by local variations in the Schottky barrier height than the other two methods, yielded the highest values of Schottky barrier heights to p-type material: Φ_B = 1.78 eV to 2.10 eV, depending on the choice of contact metal and sample boron concentration.     

Extraction of electronic parameters of Schottky diode based on an organic Orcein

An Au/Orcein/p-Si/Al device was fabricated and the current-voltage measurements of the devices showed diode characteristics. Then the current-voltage (I-V), capacitance-voltage (C-V) and capacitance-frequency (C-f) characteristics of the device were investigated at room temperature. Some junction parameters of the device such as ideality factor, barrier height, and series resistance were determined from I-V and C-V characteristics. The ideality factor of 2.48 and barrier height of 0.70 eV were calculated using I-V characteristics. It has been seen that the Orcein layer increases the effective barrier height of the structure since this layer creates the physical barrier between the Au and the p-Si. The interface state density N_ss were determined from the I-V plots. The capacitance measurements were determined as a function of voltage and frequency. It was seen that the values of capacitance have modified with bias and frequency.     

On the current-voltage characteristics of epitaxial Schottky barrier diodes

The J-V characteristics of epitaxial Schottky barrier diodes are analyzed. Based on the assumption of negligible recombination in the epitaxial layer, formal solution from which the J-V characteristics can be calculated is derived. The solution is valid for all injection levels and reduces to the form I = I_s[exp (q(V?IR)/kT) ? 1], where R is the series resistance of the epitaxial layer, under C12 C12V low-injection conditions. The analysis is justified by very close correspondence with exact numerical calculations using the Finite Element Device Analysis Program (FIELDAY) in which thermionic emission boundary conditions are implemented for both electrons and holes. It is shown that for low barrier Schottky diodes the minority carrier injection is negligible and the expression I = I_s[exp (q(V?IR)/kT) ? 1] describes the I-V characteristics over large bias range. For high barrier C12 C12 V Schottky diodes the exact solution must be used as minority carriers are injected and the series resistance is decreased due to conductivity modulation effect.