Improvement of breakdown voltage in SOI n-MOSFETs using thegate-recessed (GR) structure

A gate-recessed structure is introduced to SOI MOSFETs in order to increase the source-to-drain breakdown voltage. A significant increase in the breakdown voltage can be seen compared with that of a planar single source/drain SOI MOSFET without inducing the appreciable reduction of the current drivability. We have analyzed the origin of the breakdown voltage improvement by the substrate current measurements and 2-D device simulations, and shown that the breakdown voltage improvement is caused by the reductions in the impact ionization rate and the parasitic bipolar current gain     

Measurement of substrate current in SOI MOSFETs

A new “Quasi-SOI” MOSFET structure is shown to allow direct measurement of substrate current in a fully-depleted SOI device. The holes generated by impact ionization near the drain are collected at the substrate terminal after they have traversed the source-body barrier and caused bipolar multiplication. By monitoring this hole current, direct characterization of the impact-ionization multiplication factor, M, and the parasitic bipolar gain, β, was performed. It was found that M-1 increases exponentially with V_DS and decreases with V_GS, exhibiting a drain field dependence. The bipolar gain β was found to be as high as 1000 for V_GS-V_T=0 V and V_DS=-2.5 V, but decreases exponentially as V_DS increases. Finally, it was found that β also decreases as V_GS increases     

Hot carrier induced degradation in mesa-isolated n-channel SOIMOSFETs operating in a Bi-MOS mode

A thorough investigation of hot carrier effects is made in mesa-isolated SOI nMOSFETs operating in the Bi-MOS mode (abbreviated as Bi-nMOSFETs). As a result of its unique hybrid operation mechanism, significant reduction of hot carrier induced maximum transconductance degradation and threshold voltage shift in the Bi-nMOSFET is observed in comparison with that in the conventional SOI nMOSFETs. Device lifetime of SOI Bi-nMOSFETs and conventional SOI nMOSFETs was roughly estimated for comparison. In view of the analysis of the degradation mechanism, the devices were stressed under different conditions. The post-stress body current and stress body current in Bi-nMOSFETs as a function of the stress time and stress drain voltage were evaluated as further proofs of the aging reasons. The hot electron injection is found to be the dominant degradation process in the SOI Bi-nMOSFETs. Compared with SOI nMOSFETs, SOI Bi-nMOSFETs show better immunity to the parasitic bipolar transistor action due to the body contact. In addition, the positive body bias can result in lowered hot hole injection into the gate oxide due to the provision of the generated hole leakage path, and thus decreased interface traps     

0.5μm部分耗尽SOI MOSFET中的寄生双极效应

0.5μm部分耗尽SOI MOSFET的寄生双极效应严重影响了SOI器件和电路的抗单粒子和抗瞬态γ辐射能力。文中显示,影响0.5μm部分耗尽SOI NMOSFET寄生的双极器件特性的因素很多,包括NMOSFET的栅上电压、漏端电压和体接触等,尤其以体接触最为关键。在器件处于浮体状态时,0.5μm SOI NMOSFET的寄生双极器件很容易被触发,导致单管闭锁。因此,在设计抗辐射SOI电路时,需要尽量降低SOI NMOSFET寄生双极效应,以提高电路的抗单粒子和抗瞬态γ辐射能力。     

Analysis of drain breakdown voltage in SOI n-channel MOSFETs

The reduction of drain breakdown voltage in SOI nMOSFETs with floating substrate is related to the presence of a parasitic n-p-n bipolar structure, the base of which is the floating body of the device. reduction of breakdown voltage (compared to the case where a body contact is used) is shown to be dependent on both channel length and minority carrier lifetime in the SOI material. Conversely, it is shown that mere measurement of MOSFET breakdown voltages can be used to extract the minority carrier lifetime in the SOI material.<>     

Substrate current measurements in thin SOI MOSFET's at 300 and 77 K

Measurements of impact-ionized hole current in fully depleted SOI (silicon-on-insulator) MOSFETs at room temperature and liquid nitrogen temperature are reported. The measured current exhibits properties similar to those of the substrate current in bulk transistors, except for higher drain biases when the parasitic bipolar in the device is significant. Since the body contact is effective in collecting only a small fraction of the total generated hole current, the body contact cannot be used to eliminate the bipolar action in thin SOI, at least for channel widths on the order of 10 μm     

A silicon/indium arsenide source structure to suppress the parasitic bipolar-induced breakdown effect in SOI MOSFETs

We introduce Silicon/indium arsenide (Si/InAs) source submicron-device structure in order to minimize the impact of floating body effect on both the drain breakdown voltage and single transistor latch in ultra thin SOI MOSFETs. The potential barrier of valence band between source and body reduces by applying the Indium Arsenide (InAs) layer at the source region. Therefore, we can improve the drain breakdown by suppressing the parasitic NPN bipolar device and the hole accumulation in the body. As confirmed by 2D simulation results, the proposed structure provides the excellent performance compared with a conventional SOI MOSFET thus improving the reliability of this structure in VLSI applications.     

Source-to-drain breakdown voltage improvement in ultrathin-film SOIMOSFET's using a gate-overlapped LDD structure

A gate-overlapped LDD structure was introduced to ultra-thin SOI MOSFET's in order to overcome the degradation in source-to-drain breakdown voltage (BVds) due to a parasitic bipolar action. By reductions in drain electric field and parasitic resistance at a source n^- region, the BVds was improved with almost the same current drivability as that in single drain structure. The behavior of the BVds on LDD n^- concentration was investigated by use of a numerical device simulator, and it was found that the electric field at a lower portion of the n^- region, which forms the current path, was relaxed effectively at an optimum n^- doping condition     

The use of body ties in partially depleted SOI MOSTs operating at cryogenic temperatures

In this paper, the use of a body tie in partially depleted SOI MOSTs operating at 4.2 K is critically discussed. It is shown that there is a considerable improvement in the threshold voltage metastability and the related hysteresis and transient behavior of the drain current. However, the typical floating body effects, like the kink and the parasitic bipolar action are hardly suppressed. This is mainly due to the high series resistance of the body contact, similar as in bulk MOSTs operated at liquid helium temperatures.     

Abnormal drain current (ADC) effect and its mechanism in FD SOI MOSFETs

A new type of abnormal drain current (ADC) effect in fully depleted (FD) silicon-on-insulator (SOI) MOSFETs is reported. It is found that the drain current becomes abnormally large for specific front- and back-gate voltages. The drain current exhibits a transient effect due to the floating body behavior and no longer follows the conventional interface coupling theory for these specific front- and back-gate bias conditions. It is shown that the ADC can be generated by the combination of gate-induced drain leakage, transient effects, and parasitic bipolar transistor action in FD SOI MOSFETs.     

Degradation in thin-film SOI MOSFET's caused by single-transistorlatch

The measurement of anomalous hot-carrier damage in thin-film n-channel SOI MOSFETs is reported. Due to the presence of a parasitic bipolar transistor between the source and drain, the minimum drain voltage for breakdown in these devices occurs when the device is biased in subthreshold. Using charge-pumping measurements, it is shown that if the device is biased in this regime, where single-transistor latch occurs, hot holes are injected into the gate oxide near the drain. Consequently, the maximum allowable drain voltage for these devices is governed by the parasitic bipolar properties of the SOI MOSFET     

Hot-carrier effects on gate-induced-drain-leakage (GIDL) current inthin-film SOI/NMOSFET's

The gate-induced-drain-leakage (GIDL) currents in thin-film SOI/NMOSFET's have been studied before and after front-channel hot-carrier stress. Both the normal-mode stress (with the front gate biased beyond the threshold voltage and the drain biased at a high positive voltage, while the source is grounded with the back gate) and the reverse-mode stress (with the source and drain interchanged) have been investigated. The following significant changes have been observed: i) an increase of the off-state drain GIDL current after the normal-mode stress, especially in the low gate field region, and ii) a decrease of the off-state GIDL current after the reverse-mode stress, especially in the high gate field region. These changes can be attributed to the hot-carrier induced interface traps and their effects on the parasitic bipolar transistor gain in the thin-film SOI/NMOSFET     

Scaling constraints imposed by self-heating in submicron SOIMOSFET's

The presence of a buried oxide layer in silicon causes enhanced self-heating in Silicon-On-Insulator (SOI) n-channel MOSFETs. The self-heating becomes more pronounced as device dimensions are reduced into the submicron regime because of increased electric field density and reduced silicon volume available for heat removal. Two-dimensional numerical simulations are used to show that self-heating manifests itself in the form of degraded drive current due to mobility reduction and premature breakdown. The heat flow equation was consistently solved with the classical semiconductor equations to study the effect of power dissipation on carrier transport. The simulated temperature increases in the channel region are shown to be in close agreement with recently measured data. Numerical simulation results also demonstrated accelerated turn-on of the parasitic bipolar transistor due to self-heating. Simulation results were used to identify scaling constraints caused by the parasitic bipolar transistor turn-on effect in SOI CMOS ULSI. For a quarter-micron n-channel SOI MOSFET, results suggest a maximum power supply of 1.8 V. In the deep submicron regime, SOI devices exhibited a negative differential resistance due to increased self-heating with drain bias voltage. Detailed comparison with bulk devices suggested significant reduction in the drain-source avalanche breakdown voltage due to increased carrier injection at the source-body junction     

Parasitic bipolar gain reduction and the optimization of 0.25-μmpartially depleted SOI MOSFETs

An in-depth analysis of the role of parasitic bipolar gain reduction in 0.25-μm partially depleted SOI MOSFETs is presented, considering both dc characteristics as well as circuit operation. The effect of channel doping, silicide proximity, and germanium implantation on the lateral bipolar gain are characterized for optimal performance and manufacturability. Channel doping has the expected impact on bipolar gain. Silicide proximity is shown also to have a large impact. Germanium implantation into the source/drain regions reduces the lateral bipolar gain due to the introduction of defects that act as recombination centers in the source, reducing emitter efficiency. Further, germanium implantation serves to finely control the silicidation process, leading to good manufacturing control of the lateral silicide encroachment. Analysis of MOSFET dc I-V characteristics shows that threshold voltages for SOI have to be set only 30-50 mV higher for comparable dc off current to bulk CMOS. Finally, the impact of bipolar gain on floating-body-induced hysteretic effects and on alpha-particle-induced SRAM soft error rates are described     

Analysis of temperature-induced saturation threshold voltage degradation in deep-submicrometer ultrathin SOI MOSFETs

This paper presents a systematic study of the temperature lowering influence on the saturation threshold voltage degradation in ultrathin deep-submicrometer fully depleted silicon-on-insulator (SOI) MOSFETs. It is observed that the difference between the threshold voltage obtained with low and high drain bias, increases at lower temperatures for nMOSFETs, whereas it is weakly temperature-dependent for pMOSFETs. Experimental results and two-dimensional numerical simulations are used to support the analysis. The influence of applied back gate bias on threshold voltage variation is also studied. It is demonstrated that the higher doping level into the body region provided by the halo ion implantation associated to the floating-body increases both the multiplication factor and the parasitic bipolar gain as the temperature is lowered contributing to the threshold voltage degradation. The absence of halo implantation efficiently improves this degradation. The use of double gate structure, even with high body doping level, suppress the saturation threshold voltage degradation in cryogenic operation.     

New hot-carrier-degradation mode in thin-film SOI nMOSFET's

A new hot-carrier degradation mode peculiar to MOSFET's fabricated on thin-film SOI is described. This degradation mode, which occurs in nMOSFET's more easily than in pMOSFET's, is due to suppression of parasitic bipolar action caused by recombination of excess carriers through hot-carrier-induced front interface-traps. Threshold voltage is significantly shifted by this phenomenon. The reliability lifetime defined by threshold voltage shift and drain current degradation is also discussed, considering the new degradation mode     

A physical model of floating body thin film silicon-on-insulatornMOSFET with parasitic bipolar transistor

An analytical model for SOI nMOSFET with a floating body is developed to describe the I_ds-V_ds characteristics. Considering all current components in MOSFET as well as parasitic BJT, this study evaluates body potential, investigates the correlations among many device parameters, and characterizes the various phenomena in floating body: threshold voltage reduction, kink effect, output conductance increment, and breakdown voltage reduction. This study also provides a good physical insight on the role of the parasitic current components in the overall device operation. Our model explains the dependence of the channel length on the I_ds-V_ds characteristics with parasitic BJT current gain. Results obtained from this model are in good agreement with the experimental I_ds-V _ds curves for various bias and geometry conditions     

Suppression of the floating-body effect in partially-depleted SOIMOSFETs with SiGe source structure and its mechanism

SiGe layers were formed in source regions of partially-depleted 0.25-μm SOI MOSFETs by Ge implantation, and the floating-body effect was investigated for this SiGe source structure. It is found that the increase of the Ge implantation dosage suppresses kinks in I_d-V_d characteristics and that the kinks disappear for devices with a Ge dose of 3×10¹⁶ cm^-2. The lowering of the drain breakdown voltage and the anomalous decrease of the subthreshold swing are also suppressed with this structure. It is confirmed that this suppression effect originates from the decrease of the current gain for source/channel/drain lateral bipolar transistors (LBJTs) with the SiGe source structure. The temperature dependence of the base current indicates that the decrease of the current gain is ascribed to the bandgap narrowing of the source region     

Suppression of parasitic bipolar effects in thin-film SOItransistors

In order to correctly estimate the bipolar holding voltage of thin-film SOI transistors with submicrometer gate lengths, it is necessary to obtain the correct balance between the bipolar current gain and impact ionization. The bipolar current gain was found to be strongly dependent upon bandgap narrowing in the heavily doped source, while impact ionization may be most accurately modeled with a nonlocal ballistic model employing a composite electron mean-free path of 9.2 nm. Simulation with the improved models suggests that a reduction in the lateral electric field of the n^- drain region, and hence an increased bipolar holding voltage, may be achieved by using ultrathin highly doped SOI films. For a 0.5-μm gate length, a maximum holding voltage in excess of 6 V has been simulated     

Properties of ESFI MOS transistors due to the floating substrate and the finite volume

The specific current-voltage characteristics of epitaxial silicon films on insulator (ESFI®) SOS MOS transistors are shown, discussed in comparison to bulk silicon MOST's, and explained by the differences in geometrical considerations, charge distribution, and operation mode, The ESFI MOST's are produced on silicon islands, in most applications, the electrical substrate is at floating potential. This results in two effects. At first a threshold voltage change occurs with increasing drain voltage, producing a kink in the current curve; if the drain voltage further increases, a parasitic bipolar transistor begins to work and effects another kink or bend in the curve. On the other hand, the finite vo|ume effects a strong dependence of the base width of the parasitic bipolar transistor on the drain voltage and causes a rise of the current amplification with the drain voltage. The finite volume below the gate oxide also limits the bulk-charge magnitudes with subsequent increase in mobile carrier charge, thereby increasing the transconductance. All these effects are also described theoretically; the ID-VDcharacteristics could be simulated by computer model based on the physical effects.