Gate oxide leakage due to temperature accelerated degradation under plasma charging conditions

Plasma-induced gate charging and resulting damage to the gate oxide during fabrication of submicron devices becomes a serious yield and reliability concern, especially when oxide thickness and device dimensions shrink to the nanoscale region. In this paper experimental results from plasma damaged submicron MOS transistors, namely low-level gate leakage and degraded charge-to-breakdown characteristics, are analyzed with respect to conditions of electrical stress. It is demonstrated that wafer temperature is a crucial parameter for charging-induced oxide degradation due to plasma processing. Laboratory experiments simulating plasma charging showed that low-level oxide leakage is the result of oxide breakdown after electrical wear-out under low-level injection conditions. High field stress, performed at 150°C, confirmed that elevated temperature during plasma processing strongly accelerates oxide degradation and even at low-level stress leads to the effects observed in plasma damaged devices.     

Hole trap generation in the gate oxide due to plasma-inducedcharging

The paper presents results of hole trapping studies in-thin gate oxide of plasma damaged MOS transistors. Process-induced damage was investigated with antenna test structures to enhance the effect of plasma charging. In addition to neutral electron traps and passivated interface damage, which are commonly observed plasma charging latent damage, we observed and identified hole traps, generated by plasma stress. The amount of hole traps increases with increasing antenna ratio, indicating that the mechanism of hole trap generation is based on electrical stress and current flow, forced through the oxide during plasma etching. The density of hole traps in the most damaged devices was found to be larger than that in reference, undamaged devices by about 100%     

Threshold voltage degradation in plasma-damaged CMOS transistors — Role of electron and hole traps related to charging damage

The paper presents results of study of threshold voltage (V_T) degradation in CMOS transistors damaged by high-field charging. Fowler-Nordheim stress induced V_T degradation in devices with latent charging damage due to plasma processing was found to be strongly dependent on device type and diagnostic stress conditions. “Direct” and “reverse” antenna effect for NMOS, and anomalous behavior of PMOS devices are explained with polarity dependent trapping and the model includes generation of hole traps, an effect not considered previously.     

Monitoring plasma-process induced damage in thin oxide

Plasma etching and resist ashing processes cause current to flow through the thin oxide and the resultant plasma-induced damage can be simulated and modeled as damage produced by constant current electrical stress. The oxide charging current produced by plasma processing increases with the `antenna' size of the device structure. Oxide charge measurement such as CV or threshold voltage is a more sensitive technique for characterizing plasma-processing induced damage than oxide breakdown. The oxide charging current is collected only through the aluminum surfaces not covered by the photoresist during plasma processes. Although forming gas anneal can passivate the traps generated during plasma etching, subsequent Fowler-Nordheim stressing causes more traps to be generated in these devices than in devices that have not been through plasma etching. Using the measured charging current, the breakdown voltage distribution of oxides after plasma processes can be predicted accurately. Oxide shorts density of a single large test capacitor is found to be higher than that in a multiple of separated small capacitors having the same total oxide area. This would lead to overly pessimistic oxide defect data unless care is taken     

Recovery and stress dynamics in bipolar transistors and MOS devices

Stress and recovery dynamics of bipolar transistors and ultra thin oxide MOS devices have been investigated. We have found that these devices can exhibit similarities in the stress dynamics. The recovery during heat treatment was also investigated and it was found that both the dynamics and the temperature dependence of the recovery were very similar for both bipolar and MOS devices. These findings indicate that the defects might be similar where bipolar current gain degradation and MOS gate oxide charging are concerned.     

Nondestructive DCIV method to evaluate plasma charging damage inultrathin gate oxides

Understanding and minimizing plasma charging damage to ultrathin gate oxides became a growing concern during the fabrication of deep submicron MOS devices. Reliable detecting techniques are essential to understand its impact on device reliability. As the gate oxide thickness of MOSTs rapidly scales down, the conventional nondestructive methods such as capacitor C-V and threshold voltage and subthreshold swing of MOSTs are no longer effective for evaluating this damage in gate oxide. In this paper, the newly developed direct-current current-voltage (DCIV) technique is reported as an effective monitor for plasma charging damage in ultrathin oxide. The DCIV measurements for p-MOSTs with both 50- and 37-Å gate oxides clearly show the plasma charging damage region on the wafers and are consistent with the results of charge-to-breakdown measurements. In comparing with charge-to-breakdown measurement and other conventional methods, the DCIV technique hits the advantages of nondestructiveness, high sensitivity and rapid evaluation     

The prospect of process-induced charging damage in future thin gate oxides

Gate oxide scaling effect on plasma charging damage is discussed for various IC fabrication processes such as metal etching, contact oxide etching, high current ion implantation, and via contact sputtering. Capacitance distortion, stress-induced leakage current, MOSFET characteristics, and circuit performance are used for evaluating the charging damage. We observed that very thin gate oxides are less susceptible to the charging damage because of their lower rate of interface damage, larger charge-to-breakdown, and less device determined stress voltage in the plasma system. We also discuss the diode protection scheme and design techniques for minimizing the charging damage. Latent damage exists after thermal annealing and can be revealed during the subsequent device operation causing circuit performance degradation. High density plasma etching is a trend of the etching technology as it provides better anisotropy, selectivity, and uniformity. Its effects on oxide charging damage is compared with low-density plasma etching. The resistance to process-induced charging damage of future devices appears to be high. This is counter-intuitive and is a good tiding for the future of IC manufacturing. The emergence of alternative gate dielectric raises questions about charging damage that requires further studies.     

Effects of wafer temperature on plasma charging induced damage toMOS gate oxide

The effect of wafer temperature on damage to thin MOS gate oxide from plasma has been investigated for the first time. As the wafer surface temperature during an O₂ plasma exposure increases from 145°C to 340°C, the damage measured from charge-to-breakdown (Q_bd) increases dramatically. This result agrees with Fowler-Nordheim tunneling current mechanism for plasma charging and the temperature activated damage model. The increase of damage at higher wafer processing temperature indicates that elevated temperature plasma processes, such as plasma enhanced CVD and Cu etching, can be expected to be more susceptible to charging damage than low temperature plasma processes     

Hot-carrier-induced degradation in ultra-thin-film fully-depleted SOI MOSFETs

The charge-pumping measurement technique was successfully applied to submicron (L_eff = 0.35 μm) n-MOSFETs on ultra-thin (50 nm) SOI film. The hot-carrier-induced degradation is studied by examining the damages to both gate-oxide and buried-oxide (BOX) interfaces. We found that when stressed at maximum substrate current, interface-trap generation is still the primary cause for hot-carrier-induced degradation. Even for ultra-thin-film SOI devices, the hot-carrier-induced damage is locally confined to the gate-oxide interface and only minor damage is observed at the buried-oxide interface. The buried-oxide interface charging contributes less than 5% of the overall drain current degradation.     

Study of the growth temperature dependence of performance andreliability of thin MOS gate oxides

An in-depth and systematic investigation is carried out to find the role of oxide growth temperature in determining the quality of the resulting gate oxide in MOS devices. Performance of fresh devices as well as degradation under hot-carrier stress and radiation exposure are studied using MOS capacitors and MOSFETs. Experimental results indicated that better charge trapping properties and interface endurance to both hot carrier-stress and ionizing radiation can be realized by elevating the gate oxidation temperature. Substantial experimental evidence is provided to establish that interface state generation during stress is mainly responsible for the degradation of various MOSFET parameters. These findings point out that rapid thermal processing may be the technique for the growth of ultrathin gate oxides for deep-submicrometer MOS technology, at least from the quality and reliability point of view     

Plasma charging damage during contact hole etch in high-density plasma etcher

Plasma process induced damage from high-density plasma dielectric etcher was studied comprehensively. It was observed that PMOS devices were damaged more readily than NMOS devices. Low field gate current is the most sensitive parameter to reflect the permanent damages. Some permanent damages become hidden defects after backend of line processes. These latent damages in the form of gate oxide traps result in poor oxide integrity during Fowler–Nordheim stress or hot carrier stress. The damage shows good correlation with the total exposed contact area. The safe antenna ratio is much lower than that at the conductor etch, although no electron shading effect was observed. Thus, plasma damage during contact or via hole etch in high-density plasma system must be considered carefully.     

Degradation of submicron N-channel MOSFET hot electron reliabilitydue to edge damage from polysilicon gate plasma etching

The impact of poly-Si gate plasma etching on the hot electron reliability of submicron NMOS transistors has been explored. The results show that the gate oxide and SiO₂-Si interface near the drain junction have a susceptibility to hot electron injection that increases with overetch time. We show for the first time that this degradation of hot electron reliability is attributable to the edge type of gate oxide damage resulting from direct plasma exposure during overetch processing. We demonstrate that this type of damage does not scale with channel length and becomes even more important in shorter channel transistors     

Resist-related damage on ultrathin gate oxide during plasma ashing

This paper presents an important observation of plasma-induced damage on ultrathin oxides during O₂ plasma ashing by metal “antenna” structures with photoresist on top of the electrodes. It is found that for MOS capacitors without overlying photoresist during plasma ashing, only minor damage occurs on thin oxides, even for oxide thickness down to 4.2 nm and an area ratio as large as 10⁴. In contrast, oxides thinner than 6 nm with resist overlayer suffer significant degradation from plasma charging. This phenomenon is contrary to most previous reports. It suggests that the presence of photoresist will substantially affect the plasma charging during ashing process, especially for devices with ultrathin gate oxides     

PECVD淀积介质层对MOSFET性能的影响

通过对nMOS器件随天线比增加的阈值电压漂移、跨导变化,MOS电容在TDDB测试后的QBD退化分析来评估在RIE（Reactive Ion Etching）金属前PECVD-TEOS预淀积保护介质层的保护作用,实验结果表明此介质层没有起到足够的保护作用,反而会由于更长的等离子体工艺时间产生更严重的损伤问题。传统的电荷在硅片表面积累理论不足以解释此现象,本文从高能电子隧穿作用来分析此性能退化的原因。     

Hot-carrier degradation mechanism in narrow- and wide-channeln-MOSFETs with recessed LOCOS isolation structure

Narrow-channel n-MOSFETs with recessed LOCOS (R-LOCOS) isolation structure exhibit less hot carrier-induced degradation than wide-channel n-MOSFETs, but the degradation mechanism of both devices is the same. This new finding Is explained by the fact that in deep submicron MOSFETs with ultra-thin gate oxide, the dominant factor deciding the degradation behavior in narrow- and wide-channel devices is the vertical electric field effect rather than the mechanical stress effect     

Modeling oxide thickness dependence of charging damage by plasmaprocessing

Develops a quantitative model for thin oxide plasma charging damage by examining the oxide thickness dependence of charging current. The current is deduced from capacitance-voltage (CV) curves of metal-oxide-semiconductor (MOS) capacitors after plasma etch. The model predicts the oxide thickness dependence of plasma charging successfully. It is shown that plasma acting on a very thin oxide during processing may be modeled as essentially a current source. Thus the damage will not be greatly exacerbated as oxide thickness is further reduced in the future. Gate oxide breakdown voltage distribution of MOS capacitors after plasma processing can be predicted accurately from that of a control wafer by using a defect-induced breakdown model     

Plasma damage in thin gate MOS dielectrics and its effect on device characteristics and reliability

Plasma process-induced damage continues to be a great threat and concern in the modern CMOS technologies. This article concentrates on NMOS vs. PMOS device sensitivity to plasma charging originating from the various processing steps. This dependence is studied with respect to the gate oxide thickness, and large antenna devices are used to evaluate device yield, latent damage, and residual effect of charging on device performance and reliability. Specific studies are performed to explore the resistance to the charging damage in CMOS devices with a 50 Å gate oxide grown with various oxidation processes.     

LOCOS-induced stress effects on thin-film SOI devices

LOCOS-induced stress effects on thin-film SOI devices are investigated. We show that as the field oxide thickness increases, degradation (enhancement) of nMOSFET's (pMOSFET's) I-V characteristics becomes increasingly pronounced. The total degradation or enhancement of I-V characteristics can reach ~40% of drive current for devices under certain processing conditions. Estimated stress results using four-point bending measurement show that the stress level on the silicon film is of order 1200 MPa for devices with ~40% of I-V degradation/enhancement. We attribute the stress phenomenon to the volumetric expansion of field oxide during the LOCOS process     

The charging and discharging of high-voltage stress-generated trapsin thin silicon oxide

Excess high-voltage stress-generated low-level leakage currents through 10 nm silicon oxides, previously described as DC currents, are shown to decay to the limit of detection given adequate observation time and, thus, have no discernible component. A physical model is presented which describes the majority of the excess low-level leakage currents in terms of the charging and discharging of traps previously generated by the high voltage stress. Excess low-level leakage currents measured with voltage pulses with polarity opposite to that of the stress voltage are found to contain an additional current component, which is explained by the transient charging and discharging of certain traps inside the oxide. Evidence is presented which suggests that an oxide trap generated by the high-voltage stress can contain either a positive or a negative charge, in addition to being neutral and that the traps are located near both oxide interfaces. All of the trap charging and discharging currents can be explained by the flow of electrons into and out of traps generated by the high voltage stress, without resorting to the flow of holes in the oxide     

Oxide thickness dependence of plasma charging damage

Charging damage induced in oxides with thickness ranging from 8.7 to 2.5 nm is investigated. Results of charge-to-breakdown (Q_bd) measurements performed on control devices indicate that the polarity dependence increases with decreasing oxide thickness at both room and elevated temperature (180°C) conditions. As the oxide thickness is thinned down below 3 nm, the Q_bd becomes very sensitive to the stressing current density and temperature. Experimental results show that severe antenna effect would occur during plasma ashing treatment in devices with gate oxides as thin as 2.6 nm. It is concluded that high stressing current level, negative plasma charging, and high process temperature are key factors responsible for the damage.