Multilevel charge storage in Si nanocrystals arranged in double-dot-layers within SiO2

We investigated charging/discharging characteristics of a MOS structure with two layers of Si-nanocrystals (NCs) embedded in the SiO₂ dielectric. The two-dimensional (2D) arrays of nanocrystals, of sizes 3 and 5 nm in the lower and upper NCs layer, respectively, were fabricated by low pressure chemical vapor deposition (LPCVD) of amorphous Si (a-Si), followed by oxidation/annealing. The tunnel oxide was 3.5 nm thick. Successive charging of the NCs layers by both electrons and holes injected from the substrate was clearly demonstrated by the observed steps in the flatband voltage shift (ΔV_FB) as a function of the applied positive (electrons) or negative (holes) pulses on the gate, thus opening the potential for multiple bit operation of the memory. Discharging of the structure by pulses of opposite sign was consistently obtained. The current-voltage (I-V) curves exhibited two transient peaks at voltages corresponding to the two steps in ΔV_FB vs. V_gate that were attributed to a displacement current from the substrate to the nanocrystal layers. Clear improvement of charge retention in the double-nanocrystal layer structure compared to the single one was obtained, opening the possibility for lowering the gate oxide thickness of the NC memory without compromising device reliability.     

Thermal Ta2O5––alternative to SiO2 for storage capacitor application

Tantalum pentoxide thin layers (10–100 nm) obtained by thermal oxidation of rf sputtered Ta films on Si have been investigated with respect of their dielectric, structural and electric properties. It is established that stoichiometric Ta₂O₅ detected at the surface of the layers is reduced to tantalum suboxides in their depth. The oxide parameters are discussed in terms of a presence of an unavoidable ultrathin SiO₂ between Si and Ta₂O₅ and bond defects in both the oxide and the interface transition region. Conditions which guarantee obtaining high quality tantalum oxide with a dielectric constant of 32–35 and a leakage current less than 10⁻⁷–10⁻⁸ A/cm² at 1.5 V (SiO₂ equivalent thickness of 2.5–3 nm) are established. These specifications make the layers obtained suitable alternative to SiO₂ for high density DRAMs application.     

Charge trapping memory devices employing multi-layered Ge/Si nanocrystals for storage fabricated with ALD and PLD methods

The Ge/Si nanocrystals on ultra thin high-k tunnel oxide Al2O3 were fabricated to form the charge trapping memory prototype with asymmetric tunnel barriers through combining the advanced atomic layer deposition (ALD) and pulse laser deposition (PLD)techniques. Charge storage characteristics in such memory structure have been investigated using capacitance-voltage (C-V) and capacitance-time (C-t) measurements. The results prove that both the two-layered and three-layered memory structures behave relatively qualified for the multi-level cell storage. The results also demonstrate that compared to electrons, holes reach a longer retention time even with an ultra thin tunnel oxide owing to the high band offset at the valence band between Ge and Si.     

Charge trapping and interface states in hydrogen annealed HfO2–Si structures

Metal–oxide–semiconductor (MOS) capacitors based on HfO₂ gate stacks with Al and TiN gates are compared to study the effect of the gate electrode material to the properties of insulator–semiconductor interface. The structures under study were shown to contain interface trap densities of around 2 × 10¹¹ cm⁻² eV⁻¹ for Al gate and up to 5.5 × 10¹² cm⁻² eV⁻¹ for TiN gate. The peak in the surface state distribution was found at 0.19 eV above the valence band edge for Al electrode. The respective capture cross-section is 6 × 10⁻¹⁷ cm² at 200 K.The charge injection experiments have revealed the presence of hole traps inside the dielectric layer. The Al-gate structure contains traps with effective capture cross-section of 1 × 10⁻²⁰ cm², and there are two types of traps in the TiN-gate structure with cross-sections of 3.5 × 10⁻¹⁹ and 1 × 10⁻²⁰ cm². Trap concentration in the structure with Al electrode was considerably lower than in the structure with TiN electrode.     

A systematic investigation of work function in advanced metal gate–HfO2–SiO2 structures with bevel oxide

This paper presents for the first time the work function extraction for chemical vapor deposition (CVD)-TiN and poly-Si work functions on atomic layer deposition (ALD)-HfO₂ and high temperature SiO₂ (HTO) for a wide range of EOT values. The measurements were performed on bevel oxide structures with various SiO₂ thicknesses from 0 to 12 nm. Our results reveal that the work functions of both TiN and poly-Si gates highly depend on the underlying dielectrics especially in the case of TiN on HTO films. It is found that the leakage current also depends on the dielectric stacks. When TiN is formed on the HTO film, its work function has two distinct values depending on the HTO thickness; this indicates that TiSi bonds strongly affect the work function variation. Both TiN on HTO and poly-Si on HfO₂ show the work function shifts to about 4.3 eV, suggesting a pinning level in both structures.     

Transients during pre-breakdown and hard breakdown of thin gate oxides in metal–SiO2–Si capacitors

Time–resolved electrical measurements show transient phenomena occurring during degradation and intrinsic dielectric breakdown of gate oxide layers under constant voltage Fowler–Nordheim stress. We have studied such transients in metal/oxide/semiconductor (MOS) capacitors with an n⁺ poly-crystalline Si/SiO₂/n-type Si stack and with oxide thickness between 35 and 5.6 nm. The data adds new information concerning the intrinsic breakdown mechanism and these are shown and discussed together with the adopted measurement techniques.     

Flat-field spectrograph in SiO2/Si

The operation of a flat-field spectrograph in silica glass on silicon (SiO₂/Si) as a demultiplexer with 4-nm channel spacing in the 1.5-μm waveguide length region is demonstrated. The concept allows fabrication tolerances to be compensated simultaneously with the adjustment of fan-out. Fiber-to-fiber insertion loss of 10.1 dB and crosstalk attenuation >15 dB have been achieved     

Transport process in thin SiO2 films with an embedded 2-D array of Si nanocrystals

This work deals with the electrical characteristics and physical properties of novel dielectric systems based on silicon nanocrystals embedded in SiO₂ matrices. In particular, the transport phenomena of 10 nm thick SiO₂ capacitors with an embedded thin layer (5 nm) of LPCVD Si nanocrystals, located at different tunneling distances from the oxide–substrate interface, are studied. An original model based on an elastic tunneling phenomenon, which allows an efficient evaluation of the main structural characteristics of Si dots, is proposed.     

The doped Si/SiO2 interface

A study is reported of the influence of dopant atoms on the SiSiO₂ interface states of thermally oxidized silicon. It was found that acceptor or donor atoms induce interface states and oxide charges. The effect is largest in the case of acceptor dopants and is independent of the doping process. The influence of the dopant atoms on oxide charge is probably related to the different segregation coefficients of acceptors and donors.     

RTA effects on the formation process of embedded luminescent Si nanocrystals in SiO2

It is well known that Si ion implantation into SiO₂ and subsequent high temperature anneals induce the formation of embedded luminescent Si nanocrystals. In this work, the potentialities of rapid thermal annealing to enhance the photoluminescence as well as those to induce low temperature formation of luminescent Si nanocrystals have been investigated. Ion implantation was used to synthesize specimens of SiO₂ containing supersaturated Si with different concentrations. The implanted samples were rapidly annealed only for a few minutes. After that, in some cases before that, the samples were annealed for a few hours using a conventional tube furnace to induce Si precipitation. Photoluminescence spectra were measured at various stages of anneal processes. The luminescence intensity is strongly enhanced with a rapid thermal annealing prior to a conventional furnace anneal. The luminescence intensity, however, decreases when rapid thermal annealing follows conventional furnace annealing. It is found that the order of heat treatment is an important factor in intensities of the luminescence. Enhancement is found to be typical for low dose samples. Moreover, the visible photoluminescence is found to be observed even after conventional furnace anneal below 1000 °C, only for rapidly thermal annealed samples. Based on our experimental results, we discuss the mechanism for the enhancement of the photoluminescence, together with the mechanism for the initial formation process of Si nanocrystals.     

Improving low-temperature APCVD SiO2 passivation byrapid thermal annealing for Si devices

The quality of low-temperature (≈400°C) atmospheric pressure chemical vapor deposited (APCVD) silicon dioxide (SiO₂ ) films has been improved by a short time rapid thermal annealing (RTA) step. The RTA step followed by a low temperature (400°C) forming gas anneal (FGA) results in a well-passivated Si-SiO₂ interface, comparable to thermally grown conventional oxides. Efficient and stable surface passivation is obtained by this technique on virgin silicon as well as on photovoltaic devices with diffused (n⁺p) emitter surface while maintaining a very low thermal budget. Device parameters are improved by this APCVD/RTA/FGA passivation process     

Improved characteristics for Pd nanocrystal memory with stacked HfAlO–SiO2 tunnel layer

Stacked HfAlO-SiO₂ tunnel layers are designed for Pd nanocrystal nonvolatile memories. For the sample with 1.5 nm-HfAlO/3.5 nm-SiO₂ tunnel layer, a smaller initial memory window is obtained compared to the sample with 3.5 nm-HfAlO/1.5 nm-SiO₂ tunnel layer. Owing to the thermally induced traps in HfAlO-SiO₂ films are located at a farther distance from the Si substrate and more effective blocking of charge leakage by asymmetric tunnel barrier, a larger final memory window and better retention characteristic can be obtained for Al/blocking oxide SiO₂/Pd NCs/1.5 nm-HfAlO/3.5 nm-SiO₂/Si structure. A N₂ plasma treatment can further improve the memory characteristics. Better memory characteristics can be obtained for Pd-nanocrystal-based nonvolatile memory with an adequate thickness ratio of HfAlO to SiO₂.     

Visible light emitting Si/SiO2 superlattices

Six-period superlattices of Si/SiO₂ have been grown at room temperature using molecular beam epitaxy. With this mature technology, the ultra-thin (1–3 nm) Si layers were grown to atomic layer precision. These layers were separated by 1 nm thick SiO₂ layers whose thickness was also well controlled by using a rate-limited oxidation process. The chemical and physical structures of the multilayers were characterized by cross-sectional TEM, X-ray diffraction, Raman spectroscopy, Auger sputter-profile, and X-ray photoelectron spectroscopy. The analysis showed that the Si layer is free of impurities and is amorphous, and that the SiO₂/Si interface is sharp (0.5 nm). Photoluminescence (PL) measurements were made at room temperature using 457.9 nm excitation. The PL peak occurred at wavelengths across the visible range for these multilayers. The peak energy position E was found to be related to the Si layer thickness d by E (eV) = 1.60+0.72d⁻² in accordance with a quantum confinement mechanism and the bulk amorphous-Si band gap.     

An epitaxial Si/SiO2 superlattice barrier

An epitaxial strain layer Si/SiO₂ superlattice barrier (SLSB) for silicon formed by monolayers of adsorbed oxygen, sandwiched between adjacent thin silicon layers deposited with molecular beam, showed good epitaxy with an effective barrier height of 1.7 eV. Such a barrier should be important for future quantum devices in silicon, as well as new applications in conventional MOS technology.     

在SiO2中掺A1对Au／纳米（SiO2／Si／SiO2）／p—Si结构电致发光的影响

利用射频磁控溅射方法,制成纳米SiO2层厚度一定而纳米Si层厚度不同的纳米（SiO2/Si/SiO2）/p-Si结构和纳米（SiO2:A1/Si/SiO2:A1)/p-Si结构,用磁控溅射制备纳米SiO2:A1时所用的SiO2/A1复合靶中的A1的面积百分比为1%。上述两种结构中Si层厚度均为1-3nm,间隔为0.2nm。为了对比研究,还制备了Si层厚度为零的样品。这两种结构在900℃氮气下退火30min,正面蒸半透明Au膜,背面蒸A1作欧姆接触后,都在正向偏置下观察到电致发光（EL）。在一定的正向偏置下,EL强度和峰位以及电流都随Si层厚度的增加而同步振荡,位相相同。但掺A1结构的发光强度普遍比不掺A1结构强。另外,这两种结构的EL具体振荡特性有明显不同,对这两种结构的电致发光的物理机制和SiO2中掺A1的作用进行了分析和讨论。     

Interface states in SiSiO2 interfaces

Interface state parameters were studied in MOS capacitors over a wide range of energy by conductance and capacitance measurements at various temperatures from room temperature to liquid nitrogen temperature. A new technique was developed for analysis of the data which allows to obtain the density of states, the capture cross section, the surface potential and the dispersion parameter from the conductance and capacitance vs. frequency curves. The density of interface states as well as the electron capture cross section were found to be a function of energy only and to be independent of temperature. Maxima in the density of states have not been found.     

Silicon nano-particles in SiO2 sol–gel film for nano-crystal memory device applications

A novel 2-bit nano-silicon based non-volatile memory is proposed to double memory density. The thin film structure exhibits two conduction states (ON and OFF) at different voltages and has a cost-effective structure. The structure utilizes the good electrical properties of fluorinated SiO₂ thin films, together with the bi-stable properties conferred by the nano-silicon particles therein embedded. A polymeric layer of 8-hydroxyquinoline aluminum salt (Alq3) further deposited on the top of the nano-particle layer through chemical evaporation and a silver paste contact determines the final structure. The positive 0–15 V scan reveals two discontinuities with an ON/OFF ratio of 10⁴–10⁵ (2–4 V) and OFF/ON of 10³ (12.5–13.0 V). The reverse scan displays again two distinct thresholds, range of 10.5–11.0 V (ON/OFF ratio 10⁻³), respectively, 0.5 V (OFF/ON ratio 10⁻⁵–10⁻⁴).     

Fabrication of Microcavity Light-Emitting Diodes Using Highly Reflective AlN–GaN and Ta2O 5–SiO2 Distributed Bragg Mirrors

We report the fabrication of microcavity light-emitting diodes (MCLEDs) with high reflectivity and crack-free AlN-GaN distributed Bragg reflector (DBR). The 5lambda microcavity structure consists of an n-type GaN, ten pairs InGaN-GaN multiple quantum wells and p-type GaN sandwiched between the hybrid cavity mode of an AlN-GaN and a Ta₂O₅-SiO₂ DBR. The AlN-GaN DBR has 29 periods with insertion of six AlN-GaN superlattice layers showing a crack-free surface morphology and a high peak reflectivity of 99.4% with a stopband of 21 nm. The output power of MCLED is about 11 W at an injection current of 7 mA. The electroluminescence has a polarization property with a degree of polarization of about 51%.     

The self-formatting barrier characteristics of Cu–Mg/SiO2 and Cu–Ru/SiO2 films for Cu interconnects

To substitute or to supplement diffusion barrier as reducing lateral dimension of interconnects, the alloying Mg and Ru to Cu was investigated as a self-formatting barrier in terms of their resistivity, adhesion, and barrier characteristics After annealing at 400 °C for 30 min, the resistivities of the Cu–0.7 at%Mg alloy and Cu–2.2 at%Ru alloy were 2.0 μΩ cm and 2.5 μΩ cm, respectively, which are comparable to that of Cu films. The adhesion was investigated by means of a sandwiched structure using the four point bending test. The interfacial debonding energy, which represents the adhesion, of Cu–Mg/SiO₂ was over 5.0 J/m², while those of the Cu–Ru/SiO₂ and Cu/SiO₂ interfaces were 2.2 J/m² and 2.4 J/m², respectively. The barrier characteristics of the alloy films were also investigated by the time-dependent dielectric breakdown test, using a metal–oxide–semiconductor structure, under bias-temperature stress. It was shown that the alloying of Mg made the lifetime seven times longer, as opposed to the alloying of Ru which made it shorter.     

CMOS-compatible silicon devices on thin SiO2 membranes

A novel method of fabricating low power silicon-based devices on thermally insulating membranes for use in sensing applications is presented. The devices can be operated at temperatures of ~250°C with power consumption not exceeding 25mW