Gate current and oxide reliability in p+ poly MOScapacitors with poly-Si and poly-Ge0.3Si0.7 gatematerial

Fowler-Nordheim (FN) tunnel current and oxide reliability of PRiLOS capacitors with a p⁺ polycrystalline silicon (poly-Si) and polycrystalline germanium-silicon (poly-Ge_0.3Si_0.7 ) gate on 5.6-nm thick gate oxides have been compared. It is shown that the FN current depends on the gate material and the bias polarity. The tunneling barrier heights, φ_B, have been determined from FN-plots. The larger barrier height for negative bias, compared to positive bias, suggests that electron injection takes place from the valence band of the gate. This barrier height for the GeSi gate is 0.4 eV lower than for the Si gate due to the higher valence band edge position. Charge-to-breakdown (Q_bd) measurements show improved oxide reliability of the GeSi gate on of PMOS capacitors with 5.6 nm thick gate oxide. We confirm that workfunction engineering in deep submicron MOS technologies using poly-GeSi gates is possible without limiting effects of the gate currents and oxide reliability     

Post-polysilicon gate-proces-induced degradation on thin gate oxide

The post-polysilicon gate-process-induced degradation on the underlying gate oxide is studied. The degradation includes an increase in the electron trapping rate and a decrease in the charge-to-breakdown, Q_bd, of the gate oxide. It is found that N₂O nitrided gate oxide is more robust than O₂ gate oxide in resisting the degradation. Also, to grow a thin polyoxide on the polysilicon-gate in N₂O rather than in O₂ lessens the degradation on the underlying gate oxide. It is nitrogen, which diffuses through the polysilicon gate and piles up at both polysilicon/oxide and oxide/silicon-substrate interfaces, that improves the oxide quality for the N₂O process     

Characteristics of Self-Aligned Gate-First Ge p- and n-Channel MOSFETs Using CVD HfO2 Gate Dielectric and Si Surface Passivation

The electrical properties of p- and n-MOS devices fabricated on germanium with metal-organic chemical-vapor-deposition HfO₂ as gate dielectric and silicon passivation (SP) as surface treatment are extensively investigated. Surface treatment prior to high-K deposition is critical to achieve small gate leakage currents as well as small equivalent oxide thicknesses. The SP provides improved interface quality compared to the treatment of surface nitridation, particularly for the gate stacks on p-type substrate. Both Ge p- and n-MOSFETs with HfO₂ gate dielectrics are demonstrated with SP. The measured hole mobility is 82% higher than that of the universal SiO₂/Si system at high electric field (~0.6 MV/cm), and about 61% improvement in peak electron mobility of Ge n-channel MOSFET over the CVD HfO₂ /Si system was achieved. Finally, bias temperature-instability (BTI) degradation of Ge MOSFETs is characterized in comparison with the silicon control devices. Less negative BTI degradation is observed in the Ge SP p-MOSFET than the silicon control devices due to the larger valence-band offset, while larger positive BTI degradation in the Ge SP n-MOSFET than the silicon control is characterized probably due to the low-processing temperature during the device fabrication     

Dependence of Fermi level positions at gate and substrate on thereliability of ultrathin MOS gate oxides

In this work, we demonstrate that the reliability of ultrathin (<10 nm) gate oxide in MOS devices depends on the Fermi level position at the gate, and not on its position at the substrate for constant current gate injection (υ_g^-). The oxide breakdown strength (Q_bd) is less for p⁺ poly-Si gate than for n⁺ poly-Si gate, but, it is independent of the substrate doping type. The degradation of an oxide is closely related to the electric field across it, which is influenced by the cathode Fermi level for constant current injection. P⁺ poly-Si gate has higher barrier height for tunneled electrons, therefore, the cathode electric field is higher to give the same injection current density. A higher electric field gives more high-energy electrons at the anode, and therefore the damage is more at the substrate interface. We have also shown that oxide degradation is independent of the testing methodology, i.e., constant current or constant voltage stress. It depends mainly on the electric field in the oxide     

Correlation between two time-dependent dielectric breakdownmeasurements for the gate oxides damaged by plasma processing

The relationship between two time-dependent dielectric breakdown (TDDB), the charge-to-breakdown under constant-current injection (Q_bd), and the time-to-breakdown under constant-voltage stress (t_bd) is derived from a defect generation model and investigated for the gate oxide damaged by plasma processing such as the antenna effect. It is found that although the Q_bd of the damaged oxide monotonously decreases with antenna ratio (r=exposed antenna surface area/gate area), the t_bd does not apparently decrease in a certain antenna ratio region. The difference between the degradation rate of Q_bd and t_bd along r is explained by taking into account the r- and time dependence of gate current density under constant-voltage stress J and the rand J-dependence of Q_bd     

SiO2 degradation with charge injection polarity

We have investigated gate oxide degradation in metal-oxide-semiconductor (MOS) devices as a function of high-field constant-current stress for charge injection from both gate and substrate. The two polarities are asymmetric: gate injection, where the substrate Si-SiO₂ interface is the collecting electrode for the energetic electrons, shows a higher rate of interface-state generation (ΔD_it) and lower charge-to-breakdown Q_bd. Thus the collecting electrode interface, which suffers primary damage, emerges as a critical degradation site in addition to the injecting electrode interface, which has been the traditional focus. Consistent with a physical-damage model of breakdown, we demonstrate that interfacial degradation is an important precursor of breakdown, and that the nature of breakdown-related damage is physical, such as trap-generation by broken bonds     

Reliable fluorinated thin gate oxides prepared by liquid phasedeposition following rapid thermal process

A reliable fluorinated thin gate oxide prepared by liquid phase deposition (LPD) following rapid thermal oxidation (RTO) in O₂ or nitridation (RTN) in N₂O ambient was reported. Fluorine (F) atoms incorporated into the oxides during LPD process are found to be helpful to the improvement of oxide quality. It is observed that these fluorinated gate oxides show good properties in radiation hardness, charge to breakdown (Q_bd), and oxide breakdown field (E_ox) endurances. Interestingly, the Q_bd 's for the fluorinated gate oxides are 10 times larger than those for the gate oxides prepared by RTO in O₂ or RTN in N₂ O directly. Some of the E_ox's are even higher than 17 MV/cm for the samples investigated in this work     

Dielectric breakdown mechanism of thin-SiO2 studied bythe post-breakdown resistance statistics

The dielectric breakdown mechanism of SiO₂ has been discussed on the basis of the experimental results of the post-breakdown resistance (R_bd) distribution. We have noticed for the first time that R_bd of SiO₂ in MOS devices is strongly related to the SiO₂ breakdown characteristics such as the polarity dependence or the oxide field dependence of Q_bd. In this paper, we discuss the dielectric breakdown mechanism of SiO₂ from the viewpoint of the statistical correlation between the R _bd distribution, the Q_bd. distribution, and the emission energy just at the SiO₂ breakdown, by changing the stress polarity, stress field, and the oxide thickness. For complete dielectric breakdown, it has been clarified that the R_bd distribution under the substrate electron injection is clearly different from that under the gate electron injection. We have also found that, irrespective of the stress current density, the gate oxide thickness and the stressing polarity, R_bd can be uniquely expressed by the energy dissipation at the occurrence of dielectric breakdown of SiO₂ for the complete breakdown. Furthermore, it has been clarified that R_bd does not depend on the energy dissipation at the occurrence of quasidielectric breakdown     

Rapid thermal anneal of gate oxides for low thermal budget TFT's

The performance and reliability of deposited gate oxides for thin film transistors (TFT's) has been studied as a function of rapid thermal annealing (RTA) conditions. The effect of temperature ranging from 700 to 950°C and the annealing ambients including oxygen (O₂), argon (Ar), and nitrous oxide (N₂O) is investigated. Improvement in charge to breakdown (Q_bd) is seen starting from 700°C, with marked increase at 900°C temperature and above. The N₂O and Ar ambients result in higher Q_bd compared to O₂ ambient and we attribute this to reduced interfacial stress. Fourier Transform Infrared spectroscopy (FTIR) is used to qualitatively measure the stress. The bias temperature instability is decreased by RTA. The TFT characteristics are significantly improved with RTA gate oxide. The RTA-Ar anneal at 950°C results in the lowest trap density in TFT's as measured from charge pumping technique     

Impact of nitrogen (N14) implantation into polysilicongate on high-performance dual-gate CMOS transistors

The effect of nitrogen (N₁₄)implant into dual-doped polysilicon gates was investigated. The electrical characteristics of sub-0.25-μm dual-gate transistors (both p- and n-channel), MOS capacitor quasi-static C-V curve, SIMS profile, poly-Si gate R_s , and oxide Q_bd were compared at different nitrogen dose levels. A nitrogen dose of 5×10¹⁵ cm^-2 is the optimum choice at an implant energy of 40 KeV in terms of the overall performance of both p- and n-MOSFETs and the oxide Q_bd. The suppression of boron penetration is confirmed by the SIMS profiles to be attributed to the retardation effect in bulk polysilicon with the presence of nitrogen. High nitrogen dose (1×10¹⁶ cm^-2) results in poly depletion and increase of sheet resistance in both unsilicided and silicided p⁺ poly, degrading the transistor performance. Under optimum design, nitrogen implantation into poly-Si gate is effective in suppressing boron penetration without degrading performance of either p- or n-channel transistors     

Argon ion-implantation on polysilicon or amorphous-silicon forboron penetration suppression in p+ pMOSFET

In this paper, a technique to use Ar ion-implantation on the p⁺α-Si or poly-Si gate to suppress the boron penetration in p⁺ pMOSFET is proposed and demonstrated. An Ar-implantation of a dose over 5×10¹⁵ cm^-2 is shown to be able to sustain 900°C annealing for 30 min for the gate without having the underlying gate oxide quality degraded. It is believed to be due to gettering of fluorine, then consequently boron, by the bubble-like defects created by the Ar implantation in the p⁺ gate region to reduce the B penetration. Excellent electrical characteristics like dielectric breakdown (E_bd), interface state density (D_it), and charge-to-breakdown (Q_bd) on the gate oxide are obtained. The technique is compatible to the present CMOS process. The submicron pMOSFET fabricated by applying this technique exhibit better subthreshold characteristics and hot carrier immunity     

High-field breakdown in thin oxides grown in N2O ambient

A detailed study of time-dependent dielectric breakdown (TDDB) in N₂O-grown thin (47-120 Å) silicon oxides is reported. A significant degradation in breakdown properties was observed with increasing oxide growth temperatures. A physical model based on undulations at the Si/SiO₂ interface is proposed to account for the degradation. Accelerated breakdown for higher operating temperatures and higher oxide fields as well as thickness dependence of TDDB are studied under both polarities of injection. Breakdown under unipolar and bipolar stress in N₂O oxides is compared with DC breakdown. An asymmetric improvement in time-to-breakdown under positive versus negative gate unipolar stress is observed and attributed to charge detrapping behavior in N₂O oxides. A large reduction in time-to-breakdown is observed under bipolar stress when the thickness is scaled below 60 Å. A physical model is suggested to explain this behavior. Overall, N₂O oxides show improved breakdown properties compared with pure SiO₂     

Ultradry annealing after polysilicon electrode formation forimproving the TDDB lifetime of ultrathin silicon oxide films in MOSdiodes

Effects of ultradry annealing on time-dependent dielectric breakdown (TDDB) lifetime (T_TDDB) were investigated for Si MOS diodes with 5-nm-thick silicon oxide and P-doped polysilicon gate electrode films. This annealing was performed at 800°C in ultradry N₂ of less than 1-ppm moisture concentration after the electrode formation. Under an accumulation-bias stress condition, T_TDDB for the ultradry-annealed n-type Si diodes was larger than that for the conventionally annealed ones, while such T _TDDB enhancement was not confirmed in the p-type ones. Since positive charges induced near anode-side oxide interfaces are closely related to T_TDDB, the T_TDDB enhancement for the ultradry-annealed n-type Si diodes probably reflects a qualitative improvement of the anode-side, i.e., gate-electrode-oxide, interfaces by ultradry annealing     

Hot-carrier-induced interface state generation in submicrometerreoxidized nitrided oxide transistors stressed at 77 K

The hot carrier degradation at 77 K of silicon MOSFETs fabricated with reoxidized nitrided oxide (ONO) gate dielectrics has been investigated. Measurements have been performed at both room and LN₂ temperatures on n-channel FETs for both ONO and conventional SiO ₂ films. It is found that the hot-carrier immunity of ONO transistors is substantially larger than that of conventional SiO₂ devices, and that the degree of improvement is much larger at room temperature that an 77 K. While the interface state generation does increase dramatically as a result of 77-K stressing, the dominant degradation mechanism can be attributed to a large increase in the drain resistance of the device due to localized charge trapping at the drain side of the channel     

New method for lifetime evaluation of gate oxide damaged by plasmaprocessing

A quantitative model is proposed, clarifying the relationship between the charge-to-breakdown with constant current injection (Q_bd) and the time-to-breakdown with constant-voltage stress (t_bd) for gate oxides damaged by plasma processing. By including the dependence of Q_bd on the stress current density, one can predict the t_bd by means of counting the fraction of the lifetime expenditure; JΔt/Q_bd(J), where J is the current density at each period (Δt) under constant-voltage stressing, until the sum of the ratio is unity. The results show good agreement for the oxides of MOS capacitors with different gate areas. This method is useful for projection of the oxide lifetime     

Time-dependent dielectric breakdown characteristics ofN2O oxide under dynamic stressing

Time-dependent dielectric breakdown (TDDB) characteristics of MOS capacitors with thin (120-Å) N₂O gate oxide under dynamic unipolar and bipolar stress have been studied and compared to those with control thermal gate oxide of identical thickness. Results show that N₂O oxide has significant improvement in t _BD (2×under-V_g unipolar stress, 20×under+V_g unipolar stress, and 10×under bipolar stress). The improvement of t_BD in N₂O oxide is attributed to the suppressed electron trapping and enhanced hole detrapping due to the nitrogen incorporation at the SiO₂/Si interface     

Evaluation of Qbd for electrons tunneling fromthe Si/SiO2 interface compared to electron tunneling from thepoly-Si/SiO2 interface

Electrical time-to-breakdown (TTB) measurements have shown the charge to breakdown Q_bd of gate oxide capacitors fabricated on n-type well (n-well) substrates always to be higher than that of capacitors on p-type well (p-well) substrates on the same wafer when both are biased into accumulation under normal test conditions. Here the authors correlate the higher n-well Q_bd to smooth capacitor oxide/substrate interfaces and minimized grain boundary cusps at the poly-Si gate/oxide interfaces, confirming that Fowler-Nordheim tunneling is the dominant current conduction mechanisms through the oxide. They correlate higher Q_bd to higher barrier height for a given substrate type and observe that the slope of the barrier height versus temperature plot is lower for both p-well and n-well cases with electrons tunneling from the silicon substrate. This is attributed to surface roughness at the poly-Si gate/SiO₂ interface. A poly-Si gate deposition and annealing process with clean, smooth oxide/substrate interfaces will improve the p-well breakdown characteristics and allow higher Q_bd to be achieved     

Ultrathin gate oxide grown on nitrogen-implanted silicon for deepsubmicron CMOS transistors

Nitrogen implantation on the silicon substrate was performed before the gate oxidation at a fixed energy of 30 keV and with the split dose of 1.0×10¹⁴/cm² and 2.0×10¹⁴ /cm². Initial O₂ injection method was applied for gate oxidation. The method is composed of an O₂ injection/N₂ anneal/main oxidation, and the control process is composed of a N₂ anneal/main oxidation. CMOS transistors with gate oxide thickness of 2 nm and channel length of 0.13 μm have been fabricated by use of the method. Compared to the control process, the initial O₂ injection process increases the amount of nitrogen piled up at the Si/SiO₂ interface and suppresses the growth of gate oxide effectively. Using this method, the oxidation retarding effect of nitrogen was enhanced. Driving currents, hot carrier reliability, and time-zero dielectric breakdown (TZDB) characteristics were improved     

Oxynitride gate dielectric grown in nitric oxide (NO): the effectof reoxidation on dielectric reliability of the active edge

Reoxidation of an oxynitride gate dielectric grown by NO anneal of thermal oxide has been studied. This process has demonstrated ~3-5X improvement of Q_BD of active edge intensive capacitors in comparison to thermal oxide, N₂O and NO oxynitride. This improvement is believed to be due to the reduction of local thinning of the gate dielectric at the field oxide edge which also reduces local build-up of positive charge near the gate electrode at the isolation edges     

Suppression of boron penetration in p+ polysilicon gateP-MOSFETs using low-temperature gate-oxide N2O anneal

It has been reported that high-temperature (~1100°C) N₂ O-annealed oxide can block boron penetration from poly-Si gates to the silicon substrate. However, this high-temperature step may be inappropriate for the low thermal budgets required of deep-submicron ULSI MOSFETs. Low-temperature (900~950°C) N₂O-annealed gate oxide is also a good barrier to boron penetration. For the first time, the change in channel doping profile due to compensation of arsenic and boron ionized impurities was resolved using MOS C-V measurement techniques. It was found that the higher the nitrogen concentration incorporated at Si/SiO₂ interface, the more effective is the suppression of boron penetration. The experimental results also suggest that, for 60~110 Å gate oxides, a certain amount of nitrogen (~2.2%) incorporated near the Si/SiO₂ interface is essential to effectively prevent boron diffusing into the underlying silicon substrate