共查询到18条相似文献,搜索用时 125 毫秒
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对MOSFET器件特性、MOSFET建模方法和建模发展历程进行了回顾,分析了在模拟集成电路低功耗设计中比较流行的模型(BSIM3和EKV模型),对它们进行了比较,分析其各自的优点和缺点。结果表明获得能够精确地预测高性能模拟系统的模型是很困难的,而EKV模型在模拟集成电路的低功耗设计中具有一定的优势。 相似文献
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MOSFET晶体管的精确匹配对模拟和混合集成电路最终性能至关重要,因此漏电流失配方差或标准差大小的计算伴随着MOSFET器件特征尺寸的减小一直不断地发展和演进.针对模拟集成电路设计中MOSFET漏电流失配,围绕模型和参数选取这一核心问题进行回顾、分析和总结,并说明其应用.同时研究其最新的进展情况及面临的问题,最后提出了... 相似文献
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随着金属氧化物半导体(MOS)集成电路工艺的飞速发展,体硅金属氧化物半导体场效应晶体管(MOSFET)模型经历了从物理到经验,最后到半经验物理的转变.介绍了以阈值电压和反转电荷为建模基础的伯克利短沟道绝缘栅场效应晶体管模型(BSIM),以及该模型中阈值电压、饱和电流和电容的基本建模理论.回顾了近年来体硅MOSFET BSIM的研究进展,着重从各种模型的优缺点、建模机理和适用范围方面分析了4种最有代表性的BSIM,即BSIM3v3,BSIM4,BSIM5和BSIM6.从模型的发展历史可以看出模型是随着MOSFET尺寸的缩小而不断完善和发展的.最后,对体硅MOSFET的模型发展趋势进行了展望. 相似文献
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衬底寄生网络建模和参数提取,对RF SOI MOSFET器件输出特性的模拟有着非常重要的影响。考虑BOX层引入的体区和Si衬底隔离,将源、体和衬底短接接地,测试栅、漏二端口S参数的传统测试结构,无法准确区分衬底网络影响。文章提出一种改进的测试结构,通过把SOI MOSFET的漏和源短接为信号输出端、栅为信号输入端,测试栅、漏/源短接二端口S参数的方法,把衬底寄生在二端口S参数中直接体现出来,并开发出一种解析提取衬底网络模型参数的方法,支持SOI MOSFET衬底网络模型的精确建立。采用该方法对一组不同栅指数目的SOI MOSFET进行建模,测量和模型仿真所得S参数在20GHz频段范围内得到很好吻合。 相似文献
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Guoyong Shi Jiajun Chen Andy Tai Frank Lee 《Analog Integrated Circuits and Signal Processing》2013,77(2):95-104
A new device sizing method for CMOS analog integrated circuit is proposed. This method employs graphical sensitivity curves of certain performance metric with respect to device sizes, called size sensitivity, to guide the designer to choose proper device sizes semi-automatically. It is shown that the plot of sensitivity curves in the frequency-domain can exhibit quantitative performance dependence to device sizes nearby dominant pole/zero locations. For accurate sensitivity calculation, the dependence on dc sensitivity in the computation of ac sensitivity to device size is emphasized and an EKV model-based implementation is outlined. The proposed graphical semi-automatic analog sizing methodology differentiates itself from the traditional black-box approaches with which the user has no interference in the optimization process. An interactive semi-automatic analog sizing tool with a graphical interface allows the user to decide which device sizes are more rewarding to tune. An operational amplifier is sized by using the proposed interactive tool. 相似文献
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提出了二极管方程一种新的解析近似解。使用精确的一阶及二阶微分和改进的牛顿-拉夫森方法,推导出一个简洁的二极管方程解析近似解。较之先前的二极管方程解法和近似,该解析近似解显著提高了二极管电流计算的精度和效率。同时,用户在将MOSFET模型如ACM、EKV和BSIM5中的二极管模型和反型层电荷模型实现到诸如SPICE等电路仿真模拟器中时,该解析近似解提供了高精度和高效率的计算方法。 相似文献
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Leo H. C. Braga Suzana Domingues Milton F. Rocha Jr. Leonardo B. Sá Fernando S. Campos Filipe V. Santos Antonio C. Mesquita Mário V. Silva Jacobus W. Swart 《Analog Integrated Circuits and Signal Processing》2008,57(1-2):129-139
This article presents a radiation hardened active pixel sensor implemented in a standard 0.35 μm CMOS process. The integrated circuit is composed of a 64 × 64 pixel matrix with a 25 μm pixel pitch and has four different pixel architectures. There are also test structures to permit the characterization of the MOS transistors. The radiation hardening of the circuit is implemented with two layout techniques: enclosed geometry transistors and guard rings. It is shown that, with these techniques, the sensor is able to operate with total ionization doses that surpass 500 krad, which is more than double of the requirement for our application. Also, the techniques do not compromise the optical response of the pixels. To obtain an electrical model of the designed transistors, an EKV MOSFET Model was extracted. 相似文献
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In this paper we present a static method for verifying the proper integration of analog and mixed-signal macroblocks into an integrated circuit. We consider the problem in a setting where there is no golden reference for verifying the validity of the interconnections between the blocks. The proposed verification methodology relies on an abstract modeling of the functional behavior of the blocks and a set of consistency criteria defined over the composition of these abstract models. A new formalism called mode sequence chart (MSeqC) has been presented for capturing the behavior of the blocks at a level of abstraction that is suitable for interconnection verification. We present rules to compose the MSeqCs of each block in an integrated design and present three criteria that indicate possible interconnection faults. We present a tool called AMS-IV (AMS-interconnection verification) that takes the design netlist as input, the MSeqC model of each design block as reference, and tests the three criteria. 相似文献
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Le Masson S. Laflaquiere A. Bal T. Le Masson G. 《IEEE transactions on bio-medical engineering》1999,46(6):638-645
Computational neuroscience is emerging as a new approach in biological neural networks studies. In an attempt to contribute to this field, we present here a modeling work based on the implementation of biological neurons using specific analog integrated circuits. We first describe the mathematical basis of such models, then present analog emulations of different neurons. Each model is compared to its biological real counterpart as well as its numerical computation. Finally, we demonstrate the possible use of these analog models to interact dynamically with real cells through artificial synapses within hybrid networks. This method is currently used to explore neural networks dynamics. 相似文献
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《Solid-State Circuits, IEEE Journal of》1977,12(1):51-58
An analog computer is described which performs transient simulation of nonsaturated transistor circuits with little expense of time. The computer contains models of bipolar transistors and Schottky-barrier diodes as well as variable capacitors and resistors, all realized in plug-in technique. The parameters of the semiconductor devices are directly and continuously adjustable. Therefore, no special knowledge is required to operate the computer. For the display, a dual-trace oscilloscope with low bandwidth is sufficient because the analog time range lies above 0.1 ms. Compared with the digital computer simulation, this analog method has the advantages of lower costs and less simulation time, the latter allowing fast interaction between designer and computer. The good accuracy of the described simulation method is demonstrated by comparing the simulated and the directly measured transient response of an integrated subnanosecond E/SUP 2/CL gate. Also it is shown how the delay time of this gate depends on the transistor parameters. 相似文献
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基于表面势的MOSFET模型 总被引:4,自引:1,他引:3
基于表面势的模型由于其本质上的优点 ,在小尺寸器件建模中日趋得到重视。文中通过对几种典型的表面势模型的分析 ,论述了基于表面势模型的建模思想、特点和在电路模拟中的优越性。分析表明 ,这是一种基于物理描述的模型 ,具有连续性、物理意义明确、结构简明等特点 ,对建立小尺寸器件整体模型非常适合和有效。 相似文献