Built-In Self-Test Techniques

A system that includes self-test features must have facilities for generating test patterns and analyzing the resultant circuit response. This article surveys the structures that are used to implement these self-test functions. The various techniques used to convert the system bistables into test scan paths are discussed. The addition of bistables associated with the I/O bonding pads so that the pads can be accessed via a scan path (external or boundary scan path) is described. Most designs use linear-feedback shift registers for both test pattern generation and response analysis. The various linear-feedback shift register designs for pseudorandom or pseudoexhaustive input test pattern generation and for output response signature analysis are presented.     

Built-In Self-Test Structures

A system that includes self-test features must have facilities for generating test patterns and analyzing the resultant circuit response. This article surveys the structures that are used to implement these self-test functions. The various techniques used to convert the system bistables into test scan paths are discussed. The addition of bistables associated with the I/O bonding pads so that the pads can be accessed via a scan path (external or boundary scan path) is described. Most designs use linear-feedback shift registers for both test pattern generation and response analysis. The various linear-feedback shift register designs for pseudorandom or pseudoexhaustive input test pattern generation and for output response signature analysis are presented.     

A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead

This paper describes a built-in self-test (BIST) hardware overhead minimization technique used during a BIST synthesis process. The technique inserts a minimal amount of BIST resources into a digital system to make it fully testable. The BIST resource insertion is guided by the results of symbolic testability analysis. It takes into consideration both BIST register cost and wiring overhead in order to obtain the minimal area designs. A Simulated Annealing algorithm is used to solve the overhead minimization problem. Experiments show that considering wiring area during BIST synthesis results in smaller final designs as compared to the cases when the wiring impact is ignored.     

Implementing a Built-In Self-Test PLA Design

An NMOS implementation of a new built-in self-test PLA design is presented. The layouts for its additional test circuitry result in appoximately 15-percent overhead for most large PlAS, a significantly better overhead than that of any existing scheme. Both the input test patterns and the output responses, which are compressed intoastring of parity bits, are independent of the functions that the PLA realizes, and the 15-percent overhead includes the storage needed for the fault-free compressed output data. The fault coverage of this approach consists of all single and (1-2 -( 2n + m)) of all multiple stuck, crosspoint, and bridging faults in the original PLA and the additional test circuitry (n and m are the number of input variables and product terms, respectively). The article begins with a short review of existing design schemes.     

Built-In Self-Test Trends in Motorola Microprocessors

The first built-in self-test feature in a Motorola sidered a ?wart? until a RAM test application recast it as a ? feature.? Though the BIST approach?an idea conceived as a way to reduce production costs for the MC6805 family?did not meet its major design objective, the experience provided impetus for the development of BIST techniques for the MC6804P2, which met most of the objectives intended for the MC6805P2. The Motorola microprocessor family has come to incorporate a growing number of testability features; current devices typically employ a combination of BIST and other techniques. If present trends continue, transistor counts for microprocessor-related parts should approach 10 million within 10 years. The authors argue that structured design techniques offer the most promising prospects for solving the design and test problems resulting from this increase in complexity.     

针对嵌入式Cache的内建自测试算法

通过分析嵌入式Cache存储器中使用的双端口字定向静态存储器(SRAM)和内容可寻址存储器(CAM)的功能故障模型,提出了有效地针对嵌入式应用的DS-MarchC E和DC—March CE测试算法,解决了以往算法用于嵌入式系统时故障覆盖率低或测试时间长导致测试效率低的问题．利用March CE算法并结合Cache系统的电路结构特点,设计并实现了一套集中管理的内建自测试测试方案．此方案可以并行测试Cache系统中不同容量、不同端口类型的存储器,并且能够测试地址变换表(TLB)的特殊结构,测试部分面积不到整个Cache系统的2％．     

面向存储器核的内建自测试

存储器内建自测试是当前针对嵌入式随机存储器测试的一种经济有效的途径。它实质是BIST测试算法在芯片内部的硬件实现,形成“片上BIST测试结构999作为E-RAM核与芯片系统其他逻辑电路的接口,负责控制功能,实现片上E-RAM的自动测试。根据一个实际项目,本文介绍了MBIST的整体设计过程,并针对测试开销等给出了定量和定性的讨论。     

基于FPGA的内建自测试的实现研究

内建自测试技术源于激励-响应-比较的测试机理,信号可以通过边界扫描传输到芯片引脚,因而即使BIST本身发生故障也可以通过边界扫描进行检测;为了解决大规模SOC芯片设计中BIST测试时间长和消耗面积大的问题,提出了一种用FPGA实现BIST电路的方法,对测试向量发生器、被测内核和特征分析器进行了研究;通过对被测内核注入故障,然后将正常电路和注入故障后的电路分别进行仿真,比较正常响应和实际响应的特征值,如果相等则认为没有故障,否则发生了特定的故障;利用ModelSim SE 6.1f软件仿真结果表明了该方法的正确有效性和快速性。     

基于多扫描链的内建自测试技术中的测试向量生成

针对基于多扫描链的内建自测试技术,提出了一种测试向量生存方法。该方法用一个线性反馈移位寄存器（LFSR）作为伪随机测试向量生成器,同时给所有扫描链输入测试向量,并通过构造具有最小相关度的多扫描链克服扫描链间的相关性对故障覆盖率的影响。此外该方法经过模拟确定难测故障集,并针对这外难测故障集利用ATPG生成最小确定性测试向量集。最后丙依据得到的最小测试向量集来设计位改变逻辑电路,利用们改变逻辑电路控制改变扫描链上特定的值来实现对难测故障的检测,从而实现被测电路和故障完全检测。     

软件内建自测试及其面向对象模板的设计

论文提出了一种软件可测性设计技术———软件内建自测试及其实施方案,以期提高软件测试效率,改进软件产品质量。论文还重点讨论了方案中面向对象模板设计中的若干问题,并给出了设计实例。     

用内建自测试(BIST)方法测试IP核

近几年基于预定制模块IP(Intellectua lProperty)核的SoC(片上系统)技术得到快速发展，各种功能的IP核可以集成在一块芯片上．从而使得SoC的测试、IP核的验证以及IP核相关性的测试变得非常困难，传统的测试和验证方法难以胜任。本文通过曼彻斯特编码译码器IP核的设计、测试，介绍了广泛应用于IP核测试的方法一内建自测试fBuilt—In SeIf Test)方法，强调了面向IP测试的IP核设计有关方法。     

Built-In Self-Testing RAM: A Practical Alternative

The article investigates the design of a built-in self-testing RAM as an economical way, in terms of silicon area overhead, to test memories?more economical than the use of external testers. The design of a BIST static RAM is given, along with design decisions, retrospectives on how design could have used the area even more efficiently, and results of implementation. The extra silicon area used by the BIST hardware for 64K static memories is only five percent; for larger memories, it is less. BIST RAM, then, is a practical alternative, especially since testing can be done even during burn-in without the aid of an expensive external tester.     

嵌入式反病毒虚拟机

通过对传统反病毒虚拟机运行机制的分析,结合应用程序实际运行特征,指出传统反病毒虚拟机将执行部件包含在虚拟机内部的结构设计对虚拟机的模拟执行能力、实现代价和运行效率等多个方面造成的影响。继而提出将执行部件从虚拟机内部剥离的思想,并以x86体系结构WINDOWS操作系统环境为例,设计了嵌入式反病毒虚拟机,使传统反病毒虚拟机的结构得到简化、实现代价得到降低、扩展能力得到增强。     

Self-Test Components for Highly Reconfigurable Systems

Verification of component-based systems presents new challenges not yet completely addressed by existing testing techniques. This paper proposes a new approach for automatically testing highly reconfigurable component-based systems, i.e., systems that can be obtained by changing some components. The paper presents an industrial case that motivates our research and proposes a testing infrastructure that tracks run-time information for components. The collected information is used for automatic testing new versions of existing components and new configurations of existing systems.     

一种微机械加速度计的自检测特性研究

采用静电力驱动质量块产生等效加速度信号实现了微机械加速度计的自检测功能。分析了平板驱动电极的静电驱动力、吸合电压以及稳定驱动位移条件。采用光学测试技术测试了驱动电压和驱动位移的关系,吸合电压,证实了理论分析。利用理论分析公式计算了低驱动电压情况下的驱动位移。结果表明在10～15V的直流驱动电压下能产生等效于1g加速度的输出。     

Flash存储器的内建自测试设计

内建自测试是一种有效的测试存储器的方法.分析了NOR型flash存储器的故障模型和测试存储器的测试算法,在此基础上,设计了flash存储器的内建自测试控制器.控制器采用了一种23位的指令,并且通过JATG接口来控制,结果通过扫描链输出.验证结果表明,设计的内建自测试结构对固定故障、转换故障、桥接故障、耦合故障、栅极干扰、漏极干扰、过渡擦除和读干扰均有100%的故障覆盖率.     

VLSI中加法器的一种高效自测试设计

基于算术加法测试生成,提出了VLSI中加法器的一种自测试方案:加法器产生自身所需的所有测试矢量.通过优化测试矢量的初值改进这些测试矢量,提高了其故障侦查、定位能力.借助于测试矢量左移、逻辑与操作等方式对加法器自测试进行了设计.对8位、16位、32位行波、超前进位加法器的实验结果表明,该自测试能实现单、双固定型故障的完全测试,其单、双故障定位率分别达到了95.570%,72.656%以上.该自测试方案可实施真速测试且不会降低电路的原有性能,其测试时间与加法器长度无关.