电泳淀积三极管结构的碳纳米管场发射显示阴极

本研究探索了一种电泳选域组装碳纳米管发射器到正栅极结构的衬底中作为三极管结构的场发射显示阴极的工艺.在这个工艺中,悬浊液中的碳纳米管在施加于栅极电极和阴极电极的电压的作用下移向并淀积到三极管结构的衬底中.同时,这个栅极电极的正电压能够排斥悬浊的碳纳米管,使栅极电极不吸附碳纳米管.实验结果表明,碳纳米管选域组装到栅极孔洞中去,并且每一个孔洞中碳纳米管具有相同的组装密度.该工艺成本低、可实现大面积阴极的制备,是一种在制备三极管型碳纳米管场发射显示阴极中可供选择的工艺.     

TFT-LCD中像素电极耦合电容对显示画质的影响

研究了TFT-LCD中像素电极与数据线之间的耦合电容(C_(pd))对显示画质的影响,分析了像素电极发生偏移后显示面板产生横纹不良的机理。研究结果表明,像素电极发生偏移后,数据线与左右两侧像素电极之间的C_(pd)耦合电容大小产生差异,造成相邻行间的像素发生不同方向的电压跳变。实际观察结果显示,当两行像素的亮度差异大于8个灰阶时,即会出现明显可见的横纹不良。提出了一种横纹不良改善方案,通过增加像素电极跨越数据线的条状设计结构,利用二者之间的交叠电容变化来补偿耦合电容的变化。模拟结果显示,当像素电极偏移1.2μm时,相邻行像素的亮度差异为6个灰阶,无水平横纹不良的产生。新型像素结构的开口率无损失,充电率满足产品设计要求,表明此方案可应用于产品设计中。     

电压倍增之像素设计

为了节省面板电路驱动芯片的功率损耗以及制作成本,本研究提出一种新的像素电路设计,而在设计中将会融合电荷泵电路。利用这种电路设计的像素可有效地将像素电极上的驱动电压提高到输入电压的2～3倍以上。此像素电路设计具有两个优势:第一,可以有效降低显示面板的像素功率损耗;第二,不需高电压的面板电路驱动芯片,因此可节省芯片的成本及功率损耗。由模拟结果可知,像素电极上的驱动电压确实可由此像素电路设计而提高到输入电压的2～3倍以上;而像素的功率损耗也可有效地降低,约为传统像素的1/2。     

TFT-LCD的新型VA八畴驱动技术

提出了一种应用于TFT-LCD的新型8畴驱动技术,可以简化现有的驱动电路,节省成本.通过在A、B像素的TFT栅极上施加具有不同削角电压的栅极信号,利用TFT像素的Feed through效应,可以在A、B像素上得到不同的显示电压,实现8畴显示.本技术只需要1组伽玛电压就可以实现8畴显示,而传统的TT-Type则需要2组.模拟结果表明:采用文章中提出的技术可以得到8畴的显示效果.由于栅极线GnA、GnB同时打开,相比两根栅极线分时打开的传统TT-Type结构,液晶电容有更多的充电时间.这样,不需要增加TFT的W/L就可以得到很好的充电效果.同时,由于不同灰阶电压下A、B像素的电压差取决于电容的耦合效应以及削角电压V1和V2的值,因此相对于CC-type而言,由于增加了V1和V2两个变量,所以调试更加灵活.     

隔离式MOSFET驱动器IC功效在轻载时得到改善

许多现代功率MOSFET在5V时达到导通电阻的低值,甚至在栅极到源极电压为5V的情况下也可达到。然而．对于大功率MOSFET．特别是绝缘栅极双极晶体管（IGBT）．工程师更希望栅极到源极电压为12V-15V．因为这些电源开关的导通电阻在高栅极到源极电压情况下会进一步降低。     

基于以顶层ITO为像素电极设计的产品工艺优化

HADS产品通常使用有机膜材料来减小寄生电容,以实现高像素密度(PPI)显示。本文对如何改善以顶层ITO为像素电极(Pixel Top)设计的有机膜产品的公共电极ITO与数据线间短路(DCS)不良进行了工艺优化研究。首先,通过显微镜、聚焦离子束对HADS有机膜产品DCS不良发生机理进行了分析,进而提出了第一钝化绝缘层刻蚀工序省略、保留第一钝化绝缘层至公共电极与像素电极间第二钝化绝缘层刻蚀时进行"一步刻蚀"的工艺流程变更改善方案。针对新工艺流程验证中TFT栅极过孔处第一钝化绝缘层出现的底切不良,通过调整等离子增强化学气相沉积成膜参数改善第一钝化绝缘层膜质,并选取最优成膜条件进一步调整干法刻蚀参数改善刻蚀形貌,获得了优良的栅极过孔刻蚀坡度角。优化后的"一步刻蚀"工艺进行的TFT基板,其栅极过孔第一钝化绝缘层坡度角小于40°,与栅极绝缘层间无明显刻蚀台阶。量产验证有机膜缺失导致的DCS发生率降为0。通过优化工艺,在降低产品不良率的同时还减少了工艺步骤,提升了产能。     

a—SiTFTLCD象素电压跳变特性研究

提出了α-Si TFT 栅源(源端与象素电极相连)电容不仅为栅源电极间交迭所产生的寄生电容 C_(gsp),还应包括源端沟道与栅电极间的本征电容 C_(gsi)。并以缓变沟道近似模型推导了 C_(gsi)的数学表达式。该式计算结果表明:TFT 开态下C_(gsi)为栅介质电容的一半。在此基础上求出了象素跳变电压ΔV_p 的精确计算公式。该公式圆满解释了传统的ΔVp 公式所不能解释的几个实验结果,从而澄清了对ΔVp 产生机理所存在的模糊认识。     

脉冲调制行波管电源 把射频相位不稳定性和高压贮能降到最小值的技术

功率微波电子管电极上的波纹电压,限制了动目标显示雷达系统的性能。当雷达采用不同的脉冲重复频率时,由于负载工作状态的变化,脉冲波纹增大。作为行波管功率放大器,阴极到管壳间电压的变化引起发射波形的相位调制和振幅调制,而动目标显示性能的降低主要原因就是相位调制。△φ(t)=K_φ△V_k(t),其中K_φ是行波管的阴极相位灵敏度,△V_k(t)是阴极电压的变化量。以加大高压电容数值的方法减少△V_k(t)是可能的,但是这样处理贮能也随之增大。串联调节器是另一种可选用的方法,但这意味着电路更加复杂,导致可靠性的降低,而且设计更费力。本文叙述高压电源的组成。它可以解决限制高压贮能问题。     

a－SiTFT LCD象素电压跳变特性研究

ａ－ＳｉＴＦＴ栅源电容Ｃｇｓ不仅为栅源电极交叠所产生的寄生电容Ｃｇｓｐ，还应包括栅电极与源端沟道间的本征电容Ｃｇｓｉ．用缓变沟道近似模型推导了Ｃｇｓｉ的表达式。通过对象素电极电压跳变公式的修正，圆满解释了先前的公式所不能解释的几个实验结果，从而澄清了对电压跳变机理的模糊认识。     

一种缓冲器阻抗动态调整的LDO

提出了一种缓冲器阻抗动态调整的LDO结构。采用并联负反馈和阻抗动态调整技术,显著降低了缓冲级的输出阻抗,没有增加额外的静态电流,功率管栅极极点始终远在单位增益带宽之外,对稳定性没有影响。该缓冲级增大了功率管栅极的摆率,提高了LDO瞬态响应性能。基于TSMC 0.18 μm 3.3 V CMOS工艺进行设计,该LDO的输出电压为1.8 V,压差电压为0.2 V,最大输出电流为100 mA。仿真结果显示,LDO的静态电流只有5 μA,当负载电流在10 ns内从0 mA跳变到100 mA时,输出欠冲和过冲电压分别为88.2 mV和34.8 mV。     

Mirrored OLED pixel circuit for threshold voltage and mobility compensation with IGZO TFTs

In this paper, pixel circuit using mirroring structure with Indium–Gallium–Zinc oxide (IGZO) thin film transistors (TFTs) for active matrix organic light emitting diode (AMOLED) display is proposed. This pixel circuit consists of only four TFTs, and one capacitor. Due to the mirroring structure, characteristic of the driving TFT can be precisely sensed by the sensing TFT, which is deployed in a discharging path for gate electrode of the driving TFT. This discharging process is strongly dependent on threshold voltage (V_T) and effective mobility of the sensing TFT. Circuit operating details are discussed, and compensation effects for threshold voltage shift and mobility variations are verified through numerical derivation and SPICE simulations. Furthermore, compared with conventional schematics, the proposed pixel circuit might have much simplified external driving circuits, and it is a promising alternative solution of high performance AMOLED display.     

有源OLED像素电路的设计与仿真

设计了有源OLED显示用非晶硅薄膜晶体管恒流型4-TFT像素驱动电路，并给出了驱动方法。应用HSPICE仿真了恒流型像素驱动电路的工作过程，详细分析了源（Source）电压VDD、存储电容Cs，以及开关晶体管T1、驱动晶体管T3的宽长比等参数对电路的输出特性的影响。仿真结果表明，此电路可以在整个帧周期持续供给OLED器件电流，并且解决了由于各像素驱动管阈值电压的差异带来的OLED亮度的不均匀问题。     

LCD面板TFT特性相关残像研究

残像是影响TFT-LCD画面品质的重要因素,也是发生原因最为复杂的一种不良。本论文提出了一种定量测量残像水平的方法,同时对TFT特性引起的残像不良进行了实验研究,得到了由TFT特性引起的交流(AC)残像发生规律及发生机理。本文通过对比研究残像画面黑白格亮度与TFT漏电流变化曲线,同时结合像素充放电计算公式进行电压差模拟,发现黑白格像素放电差异导致的像素保持电位差异(ΔV12.5mV)是发生残像的根本原因。根据以上机理,本论文提出了两种方法改善此类残像。第一种是通过改善TFT a-Si成膜工艺减小漏电流(50pA),同时提升TFT特性的稳定性,可以减小棋盘格画面残像评价导致的TFT转移特性曲线偏移;第二种是通过改变栅压低电平,避开关态时不同显示区域的TFT漏电流差异峰值;以上两种方法均可以有效改善残像(ΔL0.5cd/m~2)。     

TFT AMLCD像素矩阵电路中栅延迟的模拟研究

建立了ａ－ＳｉＴＦＴＡＭＬＣＤ的等效电路模型,综合考虑栅信号线电阻、栅与源信号线的交叠电容以及ＴＦＴ导电沟道电容构成的ＲＣ（ＲｅｓｉｓｔｉｖｉｔｙＣａｐａｃｉｔａｎｃｅ）常数,模拟计算了栅信号延迟对液晶显示屏尺寸、显示分辨率及栅信号电极材料的依赖关系,为实现器件优化设计提供参考。     

AM－LCD用TFT有源矩阵的性能研究

ＴＦＴ有源矩阵赋予ＡＭ－ＬＣＤ以所有平板显示器（ＦＰＤ）的最佳性能，使其性能已能够等于或好于最为流行的ＣＲＴ显示器件。本文讨论了ＴＦＴ有源矩阵的性能，描述了在像素电极上充电或放电的电压精度要求，介绍了ＴＦＴ－ＬＣＤ的最新进展。     

Low-temperature polysilicon thin-film transistor driving withintegrated driver for high-resolution light emitting polymerdisplay

A high-resolution low-temperature polysilicon thin-film transistor driven light emitting polymer display (LT p-Si TFT LEPD) with integrated drivers has been developed. We adopted conductance control of the TFT and optimized design and voltage in order to achieve good gray scale and simple pixel circuit. A p-channel TFT is used in order to guarantee reliability in dc bias. An inter-layer reduces parasitic capacitance of bus lines. Because of the combination of the LT p-Si TFT and LEP, the display is thin, compact, and lightweight, as well as having low power consumption, wide viewing angle, and fast response     

Hydrogenated amorphous silicon thin-film transistor with a thingate insulator

Thinning the gate insulator in an hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) has been studied in a coplanar structure. The threshold voltage decreases with decreasing gate insulator thickness without changing the field effect mobility significantly. The reduction in the threshold voltage is due to the decrease in the charge traps in the SiN_x and in its film thickness. The coplanar a-Si:H TFT with a gate insulator thickness of 35 nm exhibited a field effect mobility of 0.45 cm²/Vs and a threshold voltage of 1.5 V. The thickness of the gate insulator can be decreased in the coplanar a-Si:H TFTs because of the planarized gate insulator     

Poly-Si TFTs integrated gate driver circuit with charge-sharing structure

A p-type low-temperature poly-Si thin film transistors (LTPS TFTs) integrated gate driver using 2 non-overlapped clocks is proposed. This gate driver features charge-sharing structure to turn off buffer TFT and suppresses voltage feed-through effects. It is analyzed that the conventional gate driver suffers from waveform distortions due to voltage uncertainty of internal nodes for the initial period. The proposed charge-sharing structure also helps to suppress the unexpected pulses during the initialization phases. The proposed gate driver shows a simple circuit, as only 6 TFTs and 1 capacitor are used for single-stage, and the buffer TFT is used for both pulling-down and pulling-up of output electrode. Feasibility of the proposed gate driver is proven through detailed analyses. Investigations show that voltage bootrapping can be maintained once the bootrapping capacitance is larger than 0.8 pF, and pulse of gate driver outputs can be reduced to 5 μs. The proposed gate driver can still function properly with positive V_TH shift within 0.4 V and negative V_TH shift within-1.2 V and it is robust and promising for high-resolution display.     

An adaptive thin-film transistor

A thin-film transistor (TFT) is described whose transfer characteristic can be reversibly adapted by a short duration voltage pulse applied to a high impedance gate electrode. The device is a four-terminal two-gate structure. A source, drain, and insulator gate contact form the basic TFT, while the amount and polarity of the polarization charge on the surface of the ferroelectric material of a second gate contact determines the pinchoff voltage of the TFT transfer characteristic. Measurements on experimental units demonstrate that the pinchoff voltage is adjustable over a sizable range, and that TFT transconductance changes in excess of 1000 to 1 can be obtained. The time required to change between different states of the TFT characteristic is limited by the switching time of the ferroelectric material which, in general, can be of the order of microseconds. Electrical instabilities in the transfer characteristics of the devices, however, may limit their practical circuit application. The instabilities are observed as a slow time variation of pinchoff voltage after a state has been established. Experimental units use triglycine sulfate for the ferroelectric material and tellurium-silicon monoxide thin film transistors.     

Electrical simulation of the flicker in poly-Si TFT-LCD pixels for the large-area and high-quality TFT-LCD development and manufacturing

In this paper, we present a new flicker evaluation model through the electrical simulation of the optical flicker phenomena in different kinds of poly-Si TFT-LCD arrays for the development and manufacturing of large-area and high-quality TFT-LCDs. We applied our flicker evaluation model to three different types of TFTs; excimer laser annealed (ELA) poly-Si TFT, silicide mediated crystallization (SMC) poly-Si TFT, and counter-doped lateral body terminal (LBT) poly-Si TFT. We compared the flicker quantitatively for these three different TFT-LCDs on 40 in. UXGA scale. We identified three major factors causing the flicker such as charging time, kickback voltage and leakage current, analyzed their relative contributions to the flicker, and evaluated the values of the flicker in decibel (dB) for the three different TFT-LCD arrays. In addition, we show that the flicker is very sensitive to the low-level (minimum) gate voltage due to the large leakage current of the poly-Si TFT, and the low-level gate voltage should be chosen carefully to minimize the flicker.