基于弱晶体管的低功耗XNOR门设计

XNOR门是构成Reed-Muller逻辑的基本门电路,现有的XNOR门电路由于信号摆幅的不完全性而导致后级亚阈功耗的存在.本文通过在信号非全摆幅的节点上增加弱晶体管来实现信号的全摆幅,达到消除亚阈功耗,实现低功耗设计的目的.所提出的方法应用于两个典型的XNOR门电路的改进设计中,经PSpice模拟,其功耗改进超过20%.进一步应用到全加器的设计中,结果也证实了此方法的有效性.     

Improved performance of nanoscale junctionless transistor based on gate engineering approach

In this paper, we propose an effective method to improve the electrical characteristics of dual-material-gate (DMG) junctionless transistor (JLT) based on gate engineering approach, with the example of n-type double gate (DG) JLT with total channel length down to 30 nm. The characteristics are demonstrated and compared with conventional DMG DGJLT and single-material gate (SMG) DGJLT. The results show that the novel DMG DGJLT presents superior subthreshold swing (SS), drain-induced barrier lowering (DIBL), transconductance (G_m), ON/OFF current ratio, and intrinsic delay (τ). Moreover, these unique features can be controlled by engineering the length and workfunction of the gate material. In addition, the sensitivities of the novel DMG device with respect to structural parameters are investigated.     

The resonant gate transistor

A device is described which permits high-Qfrequency selection to be incorporated into silicon integrated circuits. It is essentially an electrostatically excited tuning fork employing field-effect transistor "readout." The device, which is called the resonant gate transistor (RGT), can be batch-fabricated in a manner consistent with silicon technology. Experimental RGT's with gold vibrating beams operating in the frequency range 1 kHz < f0< 100 kHz are described. As an example of size, a 5-kHz device is about 0.1 mm long (0.040 inch). Experimental units possessingQ's as high as 500 and overall input-output voltage gain approaching + 10 dB have been constructed. The mechanical and electrical operation of the RGT is analyzed. Expressions are derived for both the beam and the detector characteristic voltage, the device center frequency, as well as the device gain and gain-stability product. A batch-fabrication procedure for the RGT is demonstrated and theory and experiment corroborated. Both single- and multiple-pole pair band pass filters are fabricated and discussed. Temperature coefficients of frequency as low as 90- 150 ppm/°C for the finished batch-fabricated device were demonstrated.     

Impact of different transistor arrangements on gate variability

This paper evaluates a set of complex cells with different transistor arrangements that implement the same logic function. These cells were evaluated under nominal conditions and with gate variability at layout level. The purpose is to verify what topology is more appropriate to increase the robustness of cells regarding the process variability issues. Results emphasize the importance of investigating the effects caused by process variability in FinFET technologies, as the electrical characteristics of circuits suffer significant changes. In general, the best choice is to use the network that the transistor in series is as far as possible to the output node. However, a trade-off needs to be done due to performance and power consumption penalties.     

IGBT发展概述

本文概述了IGBT自发明以来主要的结构改进和相应的性能改进。包括芯片集电结附近（下层）结构改进（透明集电区）、耐压层附近（中层）结构改进（NPT、FS／SPT等）和近表面层（上层）结构改进（沟槽栅结构、注入增强结构等），以及由它们组合成的NPT—IGBT、TrenchIGBT、FS—IGBT、Trench FS-IGBT、SPT、SPT＋、IEGT、HiGT、CSTBT等。     

A semi-insulated gate gallium-arsenide field-effect transistor

Proton bombardment has been used to make a semi-insulated gate gallium-arsenide field-effect transistor. This technique combines the simplicity of the metal semiconductor FET technique, the advantage of operating the device using positive as well as negative bias on the gate, and the possible use of higher conductivity material for the channel, which may result in a higher transconductance and a higher saturated current density.     

Inverted transistor gate with FET load

The letter outlines preliminary results on a new logic gate for silicon bipolar VLSI. Gate delays below 4 ns have been achieved at 2 ?W dissipation, demonstrating a power-delay product of only 8 fJ. These results are achieved on a 3 ?m minimum feature size oxide isolated process.     

An ion-implanted Schottky-barrier gate field-effect transistor

Techniques of fabricating an n-channel silicon field-effect transistor using phosphorus ion implantation and a platinum silicide Schottky-barrier gate (SB-FET) have been developed. The platinum silicide Schottky-barrier top gate is part of the contact metallization process. The phosphorus-doped channel is obtained by using a 50-keV ion-implanted predeposition and an 1100°C drive-in. A range of implantation doses and drive-in times were used to achieve various SB-FET characteristics. A threshold/pinchoff voltage range of +0.4 to -7.5 V has been obtained with typical spreads of approximately 0.1 V across the slice. A positive threshold voltage represents a SB-FET that is normally off and is turned on by a forward-biased gate. Results have been obtained for     

An artifical synapse based on graphene field-effect transistor with silver gel/polarized-aptamer gate

In this work, we present an artificial synapse based on side-gate graphene-field-effect-transistor (GFET) using biocompatible silver gel/polarized-aptamer as gate dielectric. The gate functions as the presynaptic membrane, while the drain works as postsynaptic membrane. Various synaptic plasticities, including short-term enhancement (STE), short-term depression (STD), long-term potentiation (LTP), long-term depression (LTD) and the transformation from short-term plasticity to long-term plasticity have been emulated by the GFET artificial synapse. A model based on the function of a difference of two exponentials that is widely used to model the biological synapses is proposed, well fitting the behavior of the fabricated artificial synapses under different presynaptic spikes. With a fixed current of −1 μA applied to postsynaptic membrane, the excitatory-postsynaptic-potential-like spikes can be generated at postsynaptic membrane under the positive spikes applied to presynaptic membrane, suggesting the similarities between the artificial and biological synapses.     

A voltage tunable threshold logic gate based on multiquantum-wellheterojunction bipolar transistor for multifunction logic

The properties of a heterojunction bipolar transistor with a multiquantum-well collector region for its application as a voltage tunable logic element are examined. The quantum confined Stark effect gives rise to a strong negative differential resistance in the photocurrent-voltage characteristic of the device, which allows the device to be switched optically and/or electronically. This permits the realization of a circuit where the NAND, INVERSE CARRY, and NOR logic functions can be implemented by simply changing the biasing     

Insulated gate bipolar transistor with trench gate structure of accumulation channel

An accumulation channel trench gate insulated gate bipolar transistor (ACT-IGBT) is proposed. The simu-lation results show that for a blocking capability of 1200 V, the on-state voltage drops of ACT-IGBT are 1.5 and 2 V at a temperature of 300 and 400 K, respectively, at a collector current density of 100 A/cm~2. In contrast, the on-state voltage drops of a conventional trench gate IGBT (CT-IGBT) are 1.7 and 2.4 V at a temperature of 300 and 400 K,respectively. Compared to the CT-IGBT, the ACT-IGBT has a lower on-state voltage drop and a larger forward bias safe operating area. Meanwhile, the forward blocking characteristics and turn-off performance of the ACT-IGBT are also analyzed.     

具有积累层沟道的槽栅IGBT结构

提出了一种具有积累层沟道的槽栅IGBT结构。仿真结果表明：在阻断电压为1200V,集电极电流密度为100 A/cm2,温度分别为300K和400K下的情况下,积累层沟道槽栅IGBT的正向压降分别为1.5V 和2V而常规槽栅IGBT分别为1.7V和2.4V。新结构比常规槽栅IGBT具有更低的开态压降和更大的正向安全工作区。文中同时分析了积累层沟道槽栅IGBT的阻断特性和关断特性。     

Impact of interface traps on gate-induced drain leakage current in n-type metal oxide semiconductor field effect transistor

As the features sizes of metal oxide semiconductor field effect transistor (MOSFET) are aggressively scaled into the submicron domain, hot carriers generated by the very large electric fields of drain region create serious reliability problems for the integrated circuit in MOS technology. The charges trapping in the gate oxide and the defects at the Si/SiO₂ interface have also undesirable effects on the degradation and ageing of MOSFET. Among the problems caused by these effects is the band-to-band tunnelling (BBT) of hot carriers in the gate-to-drain overlap region which is the source of the gate-induced drain leakage current I _gidl. The oxide charges shift the flat-band voltage and result in an enhancement of the I _gidl current. On the other hand, the generation of interface traps introduce an additional band-trap-band (BTB) leakage mechanism and lead to a significant increase ?I _gidl in a drain leakage current. In this work we propose a new method to calculate the I _gidl current which takes into account of the BTB leakage mechanism in order to clarify the impact of interface traps located in the gate-to-drain overlap region on the I _gidl current.     

Analysis of insulated gate transistor turn-off characteristics

A model based upon a MOSFET driving a wide-base p-n-p transistor is presented for analysis of the turn-off behavior of n-channel insulated gate transistors. This model is found to provide a very good quantitative explanation of the shape of the collector current waveform during turn-off. Verification was accomplished using insulated gate transistors (IGT's) fabricated with two voltage ratings and a variety of radiation doses. This analysis allows the separation of the channel (electron) and minority carrier (hole) current flow in the IGT for the first time.     

Temperature behavior of insulated gate transistor characteristics

The Insulated Gate Transistor (IGT) is a new power semiconductor device with the high input impedance features of the power MOSFET and the ability to operate at high current densities even exceeding that of power bipolar transistors. The high temperature operating characteristics of the device are discussed here. Unlike the power MOSFET whose operating current density decreases by over a factor of 2 when the ambient temperature is raised to 150°C, the IGT is found to maintain its high operating current density at elevated temperatures. The temperature coefficient of the output current is found to be positive at forward drops below 1.5 V and negative at forward drops above 1.5 V. These characteristics make the IGT suitable for applications with high ambient temperatures. The results also indicate that these devices can be paralleled without current hogging problems if the forward conduction occurs at forward voltage drops in excess of 1.5 V.     

InGaAsP/InP optoelectronic exclusive-OR (XOR) gate operating with optical inputs and outputs

An optoelectronic exclusive-OR (XOR) gate operating with optical inputs and outputs was fabricated. The gate is based on an optoelectronic bistable switch consisting of a light emitting diode (LED) and a heterojunction phototransistor (HPT). The inverter function indispensable for the XOR logic is attained optically by connecting an additional HPT to the bistable switch in parallel. Successful operation of the XOR logic was demonstrated.<>     

SiGe-collector trench gate insulated gate bipolar transistor fabricated using multiple target sputtering

A new type of trench gate IGBT (insulated gate bipolar transistor) which uses a SiGe layer for the collector is experimentally investigated. SiGe collectors with different Ge content are deposited by multiple cathode sputtering making low temperature processing possible. The change in turn-off characteristics with Ge content is also investigated. Results indicate that the use of a SiGe collector reduces the tail current at turn-off due to the reduced injection of holes to the n⁻ drift region.     

MIM gate FET: new GaAs enhancement-mode transistor

A new type of GaAs FET, the metal-insulator-metal gate FET, is proposed, which combines the advantages of both the GaAs MESFET and the GaAs MISFET. The device is especially suitable for the enhancement mode of operation.     

Channel shape in a insulated gate field-effect transistor

By defining the channel thickness of an IGFET in terms of the total mobile charge in the channel, it is shown that the channel thickness decreases with increasing surface field and increases from source to drain, being undefined beyond the pinch-off point if the IGFET is operated in saturation.     

A new LDD transistor with inverse-T gate structure

A new submicrometer inverse-T lightly doped drain (ITLDD) transistor structure for alleviating hot-electron effects is demonstrated. A thin extension of the polysilicon gate under the oxide sidewall spacer is formed, giving the gate cross section the appearance of an inverted letter T. Due to the unique self-aligned n+ T-to-gate feature facilitated by the conducting polysilicon extension, the "spacer-induced degradation" existing in a conventional LDD transistor is eliminated in ITLDD devices. This allows the use of low n- LDD doses for optimum channel electric field reduction and minimum post-implant drive-in for future VLSI compatibility. Submicrometer ITLDD transistors with good transconductance and hot-electron reliability have been achieved. The new ITLDD transistor offers a promising device structure for future VLSI applications.